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cmd/compile: remove unused ISELB PPC64 ssa opcode

The usage of ISELB has been removed as part of changes
made to support Power10 SETBC instructions.

Change-Id: I2fce4370f48c1eeee65d411dfd1bea4201f45b45
Reviewed-on: https://go-review.googlesource.com/c/go/+/465575
TryBot-Result: Gopher Robot <gobot@golang.org>
Reviewed-by: Ian Lance Taylor <iant@google.com>
Run-TryBot: Paul Murphy <murp@ibm.com>
Reviewed-by: Archana Ravindar <aravind5@in.ibm.com>
Reviewed-by: David Chase <drchase@google.com>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com>
This commit is contained in:
Paul E. Murphy 2022-10-13 11:37:37 -05:00 committed by Paul Murphy
parent 9ddf748d87
commit f9da938614
3 changed files with 8 additions and 32 deletions

View File

@ -963,9 +963,8 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
p.To.Type = obj.TYPE_MEM p.To.Type = obj.TYPE_MEM
p.To.Reg = v.Args[0].Reg() p.To.Reg = v.Args[0].Reg()
case ssa.OpPPC64ISEL, ssa.OpPPC64ISELB, ssa.OpPPC64ISELZ: case ssa.OpPPC64ISEL, ssa.OpPPC64ISELZ:
// ISEL AuxInt ? arg0 : arg1 // ISEL AuxInt ? arg0 : arg1
// ISELB is a special case of ISEL where AuxInt ? $1 (arg0) : $0.
// ISELZ is a special case of ISEL where arg1 is implicitly $0. // ISELZ is a special case of ISEL where arg1 is implicitly $0.
// //
// AuxInt value indicates conditions 0=LT 1=GT 2=EQ 3=SO 4=GE 5=LE 6=NE 7=NSO. // AuxInt value indicates conditions 0=LT 1=GT 2=EQ 3=SO 4=GE 5=LE 6=NE 7=NSO.
@ -974,24 +973,18 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
// //
// AuxInt&3 ? arg0 : arg1 for conditions LT, GT, EQ, SO // AuxInt&3 ? arg0 : arg1 for conditions LT, GT, EQ, SO
// AuxInt&3 ? arg1 : arg0 for conditions GE, LE, NE, NSO // AuxInt&3 ? arg1 : arg0 for conditions GE, LE, NE, NSO
p := s.Prog(ppc64.AISEL) p := s.Prog(v.Op.Asm())
p.To.Type = obj.TYPE_REG p.To = obj.Addr{Type: obj.TYPE_REG, Reg: v.Reg()}
p.To.Reg = v.Reg() p.Reg = v.Args[0].Reg()
// For ISELB/ISELZ Use R0 for 0 operand to avoid load. p.SetFrom3Reg(ppc64.REG_R0)
r := obj.Addr{Type: obj.TYPE_REG, Reg: ppc64.REG_R0}
if v.Op == ssa.OpPPC64ISEL { if v.Op == ssa.OpPPC64ISEL {
r.Reg = v.Args[1].Reg() p.SetFrom3Reg(v.Args[1].Reg())
} }
// AuxInt values 4,5,6 implemented with reverse operand order from 0,1,2 // AuxInt values 4,5,6 implemented with reverse operand order from 0,1,2
if v.AuxInt > 3 { if v.AuxInt > 3 {
p.Reg = r.Reg p.Reg, p.GetFrom3().Reg = p.GetFrom3().Reg, p.Reg
p.SetFrom3Reg(v.Args[0].Reg())
} else {
p.Reg = v.Args[0].Reg()
p.SetFrom3(r)
} }
p.From.Type = obj.TYPE_CONST p.From.SetConst(v.AuxInt & 3)
p.From.Offset = v.AuxInt & 3
case ssa.OpPPC64SETBC, ssa.OpPPC64SETBCR: case ssa.OpPPC64SETBC, ssa.OpPPC64SETBCR:
p := s.Prog(v.Op.Asm()) p := s.Prog(v.Op.Asm())

View File

@ -408,12 +408,10 @@ func init() {
{name: "CMPWUconst", argLength: 1, reg: gp1cr, asm: "CMPWU", aux: "Int32", typ: "Flags"}, {name: "CMPWUconst", argLength: 1, reg: gp1cr, asm: "CMPWU", aux: "Int32", typ: "Flags"},
// ISEL arg2 ? arg0 : arg1 // ISEL arg2 ? arg0 : arg1
// ISELB arg1 ? arg0 : $0. arg0 is some register holding $1.
// ISELZ arg1 ? arg0 : $0 // ISELZ arg1 ? arg0 : $0
// auxInt values 0=LT 1=GT 2=EQ 3=SO (summary overflow/unordered) 4=GE 5=LE 6=NE 7=NSO (not summary overflow/not unordered) // auxInt values 0=LT 1=GT 2=EQ 3=SO (summary overflow/unordered) 4=GE 5=LE 6=NE 7=NSO (not summary overflow/not unordered)
// Note, auxInt^4 inverts the comparison condition. For example, LT^4 becomes GE, and "ISEL [a] x y z" is equivalent to ISEL [a^4] y x z". // Note, auxInt^4 inverts the comparison condition. For example, LT^4 becomes GE, and "ISEL [a] x y z" is equivalent to ISEL [a^4] y x z".
{name: "ISEL", argLength: 3, reg: crgp21, asm: "ISEL", aux: "Int32", typ: "Int32"}, {name: "ISEL", argLength: 3, reg: crgp21, asm: "ISEL", aux: "Int32", typ: "Int32"},
{name: "ISELB", argLength: 2, reg: crgp11, asm: "ISEL", aux: "Int32", typ: "Int32"},
{name: "ISELZ", argLength: 2, reg: crgp11, asm: "ISEL", aux: "Int32"}, {name: "ISELZ", argLength: 2, reg: crgp11, asm: "ISEL", aux: "Int32"},
// SETBC auxInt values 0=LT 1=GT 2=EQ (CRbit=1)? 1 : 0 // SETBC auxInt values 0=LT 1=GT 2=EQ (CRbit=1)? 1 : 0

View File

@ -2242,7 +2242,6 @@ const (
OpPPC64CMPWconst OpPPC64CMPWconst
OpPPC64CMPWUconst OpPPC64CMPWUconst
OpPPC64ISEL OpPPC64ISEL
OpPPC64ISELB
OpPPC64ISELZ OpPPC64ISELZ
OpPPC64SETBC OpPPC64SETBC
OpPPC64SETBCR OpPPC64SETBCR
@ -30104,20 +30103,6 @@ var opcodeTable = [...]opInfo{
}, },
}, },
}, },
{
name: "ISELB",
auxType: auxInt32,
argLen: 2,
asm: ppc64.AISEL,
reg: regInfo{
inputs: []inputInfo{
{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
outputs: []outputInfo{
{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
},
},
},
{ {
name: "ISELZ", name: "ISELZ",
auxType: auxInt32, auxType: auxInt32,