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cmd/compile: make LR allocatable in non-leaf functions on ARM
The mechanism is initially introduced (and reviewed) in CL 30597 on S390X. Reduce number of "spilled value remains" by 0.4% in cmd/go. Disabled on ARMv5 because LR is clobbered almost everywhere with inserted softfloat calls. Change-Id: I2934737ce2455909647ed2118fe2bd6f0aa5ac52 Reviewed-on: https://go-review.googlesource.com/32178 Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: David Chase <drchase@google.com>
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@ -87,7 +87,7 @@ func init() {
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// Common individual register masks
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var (
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gp = buildReg("R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12")
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gp = buildReg("R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14")
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gpg = gp | buildReg("g")
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gpsp = gp | buildReg("SP")
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gpspg = gpg | buildReg("SP")
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@ -148,7 +148,7 @@ func init() {
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reg: regInfo{
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inputs: []regMask{buildReg("R1"), buildReg("R0")},
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outputs: []regMask{buildReg("R0"), buildReg("R1")},
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clobbers: buildReg("R2 R3"), // also clobbers R12 on NaCl (modified in ../config.go)
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clobbers: buildReg("R2 R3 R14"), // also clobbers R12 on NaCl (modified in ../config.go)
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},
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clobberFlags: true,
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typ: "(UInt32,UInt32)",
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@ -406,7 +406,7 @@ func init() {
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argLength: 3,
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reg: regInfo{
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inputs: []regMask{buildReg("R1"), buildReg("R0")},
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clobbers: buildReg("R1"),
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clobbers: buildReg("R1 R14"),
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},
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faultOnNilArg0: true,
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},
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@ -423,7 +423,7 @@ func init() {
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argLength: 3,
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reg: regInfo{
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inputs: []regMask{buildReg("R2"), buildReg("R1")},
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clobbers: buildReg("R0 R1 R2"),
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clobbers: buildReg("R0 R1 R2 R14"),
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},
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faultOnNilArg0: true,
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faultOnNilArg1: true,
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@ -526,6 +526,6 @@ func init() {
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gpregmask: gp,
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fpregmask: fp,
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framepointerreg: -1, // not used
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linkreg: -1, // not used
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linkreg: int8(num["R14"]),
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})
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}
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File diff suppressed because it is too large
Load Diff
@ -106,6 +106,7 @@
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package ssa
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import (
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"cmd/internal/obj"
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"fmt"
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"unsafe"
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)
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@ -527,6 +528,12 @@ func (s *regAllocState) init(f *Func) {
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// Leaf functions don't save/restore the link register.
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s.allocatable &^= 1 << uint(s.f.Config.LinkReg)
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}
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if s.f.Config.arch == "arm" && obj.GOARM == 5 {
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// On ARMv5 we insert softfloat calls at each FP instruction.
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// This clobbers LR almost everywhere. Disable allocating LR
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// on ARMv5.
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s.allocatable &^= 1 << uint(s.f.Config.LinkReg)
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}
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}
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if s.f.Config.ctxt.Flag_dynlink {
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switch s.f.Config.arch {
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