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https://github.com/golang/go
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cmd/compile: rename memory-using operations
Some *mem ops are loads, some are stores, some are modifications. Replace mem->load for the loads. Replace mem->store for the stores. Replace mem->modify for the load-modify-stores. The only semantic change in this CL is to mark ADD(Q|L)constmodify (which used to be ADD(Q|L)constmem) as both a read and a write, instead of just a write. This is arguably a bug fix, but the bug isn't triggerable at the moment, see CL 112157. Change-Id: Iccb45aea817b606adb2d712ff99b10ee28e4616a Reviewed-on: https://go-review.googlesource.com/112159 Run-TryBot: Keith Randall <khr@golang.org> Reviewed-by: Brad Fitzpatrick <bradfitz@golang.org> TryBot-Result: Gobot Gobot <gobot@golang.org>
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@ -587,14 +587,14 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.From.Offset = v.AuxInt
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Args[0].Reg()
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case ssa.OpAMD64CMPQmem, ssa.OpAMD64CMPLmem, ssa.OpAMD64CMPWmem, ssa.OpAMD64CMPBmem:
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case ssa.OpAMD64CMPQload, ssa.OpAMD64CMPLload, ssa.OpAMD64CMPWload, ssa.OpAMD64CMPBload:
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = v.Args[0].Reg()
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gc.AddAux(&p.From, v)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Args[1].Reg()
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case ssa.OpAMD64CMPQconstmem, ssa.OpAMD64CMPLconstmem, ssa.OpAMD64CMPWconstmem, ssa.OpAMD64CMPBconstmem:
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case ssa.OpAMD64CMPQconstload, ssa.OpAMD64CMPLconstload, ssa.OpAMD64CMPWconstload, ssa.OpAMD64CMPBconstload:
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sc := v.AuxValAndOff()
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_MEM
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@ -731,13 +731,13 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.To.Scale = 1
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p.To.Index = i
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gc.AddAux(&p.To, v)
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case ssa.OpAMD64ADDQconstmem, ssa.OpAMD64ADDLconstmem:
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case ssa.OpAMD64ADDQconstmodify, ssa.OpAMD64ADDLconstmodify:
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sc := v.AuxValAndOff()
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off := sc.Off()
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val := sc.Val()
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if val == 1 {
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var asm obj.As
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if v.Op == ssa.OpAMD64ADDQconstmem {
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if v.Op == ssa.OpAMD64ADDQconstmodify {
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asm = x86.AINCQ
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} else {
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asm = x86.AINCL
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@ -807,10 +807,10 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.From.Reg = v.Args[0].Reg()
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.OpAMD64ADDQmem, ssa.OpAMD64ADDLmem, ssa.OpAMD64SUBQmem, ssa.OpAMD64SUBLmem,
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ssa.OpAMD64ANDQmem, ssa.OpAMD64ANDLmem, ssa.OpAMD64ORQmem, ssa.OpAMD64ORLmem,
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ssa.OpAMD64XORQmem, ssa.OpAMD64XORLmem, ssa.OpAMD64ADDSDmem, ssa.OpAMD64ADDSSmem,
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ssa.OpAMD64SUBSDmem, ssa.OpAMD64SUBSSmem, ssa.OpAMD64MULSDmem, ssa.OpAMD64MULSSmem:
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case ssa.OpAMD64ADDQload, ssa.OpAMD64ADDLload, ssa.OpAMD64SUBQload, ssa.OpAMD64SUBLload,
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ssa.OpAMD64ANDQload, ssa.OpAMD64ANDLload, ssa.OpAMD64ORQload, ssa.OpAMD64ORLload,
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ssa.OpAMD64XORQload, ssa.OpAMD64XORLload, ssa.OpAMD64ADDSDload, ssa.OpAMD64ADDSSload,
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ssa.OpAMD64SUBSDload, ssa.OpAMD64SUBSSload, ssa.OpAMD64MULSDload, ssa.OpAMD64MULSSload:
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p := s.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = v.Args[1].Reg()
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@ -1003,11 +1003,11 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.To.Type = obj.TYPE_REG
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p.To.Reg = v.Reg()
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case ssa.OpAMD64SETEQmem, ssa.OpAMD64SETNEmem,
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ssa.OpAMD64SETLmem, ssa.OpAMD64SETLEmem,
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ssa.OpAMD64SETGmem, ssa.OpAMD64SETGEmem,
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ssa.OpAMD64SETBmem, ssa.OpAMD64SETBEmem,
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ssa.OpAMD64SETAmem, ssa.OpAMD64SETAEmem:
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case ssa.OpAMD64SETEQstore, ssa.OpAMD64SETNEstore,
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ssa.OpAMD64SETLstore, ssa.OpAMD64SETLEstore,
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ssa.OpAMD64SETGstore, ssa.OpAMD64SETGEstore,
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ssa.OpAMD64SETBstore, ssa.OpAMD64SETBEstore,
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ssa.OpAMD64SETAstore, ssa.OpAMD64SETAEstore:
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p := s.Prog(v.Op.Asm())
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p.To.Type = obj.TYPE_MEM
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p.To.Reg = v.Args[0].Reg()
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@ -121,53 +121,53 @@ func flagalloc(f *Func) {
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// TODO: figure out how to do this without arch-dependent code.
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if spill[v.ID] && v.MemoryArg() != nil {
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switch v.Op {
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case OpAMD64CMPQmem:
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case OpAMD64CMPQload:
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load := b.NewValue2IA(v.Pos, OpAMD64MOVQload, f.Config.Types.UInt64, v.AuxInt, v.Aux, v.Args[0], v.Args[2])
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v.Op = OpAMD64CMPQ
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v.AuxInt = 0
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v.Aux = nil
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v.SetArgs2(load, v.Args[1])
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case OpAMD64CMPLmem:
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case OpAMD64CMPLload:
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load := b.NewValue2IA(v.Pos, OpAMD64MOVLload, f.Config.Types.UInt32, v.AuxInt, v.Aux, v.Args[0], v.Args[2])
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v.Op = OpAMD64CMPL
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v.AuxInt = 0
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v.Aux = nil
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v.SetArgs2(load, v.Args[1])
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case OpAMD64CMPWmem:
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case OpAMD64CMPWload:
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load := b.NewValue2IA(v.Pos, OpAMD64MOVWload, f.Config.Types.UInt16, v.AuxInt, v.Aux, v.Args[0], v.Args[2])
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v.Op = OpAMD64CMPW
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v.AuxInt = 0
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v.Aux = nil
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v.SetArgs2(load, v.Args[1])
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case OpAMD64CMPBmem:
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case OpAMD64CMPBload:
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load := b.NewValue2IA(v.Pos, OpAMD64MOVBload, f.Config.Types.UInt8, v.AuxInt, v.Aux, v.Args[0], v.Args[2])
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v.Op = OpAMD64CMPB
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v.AuxInt = 0
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v.Aux = nil
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v.SetArgs2(load, v.Args[1])
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case OpAMD64CMPQconstmem:
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case OpAMD64CMPQconstload:
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vo := v.AuxValAndOff()
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load := b.NewValue2IA(v.Pos, OpAMD64MOVQload, f.Config.Types.UInt64, vo.Off(), v.Aux, v.Args[0], v.Args[1])
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v.Op = OpAMD64CMPQconst
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v.AuxInt = vo.Val()
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v.Aux = nil
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v.SetArgs1(load)
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case OpAMD64CMPLconstmem:
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case OpAMD64CMPLconstload:
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vo := v.AuxValAndOff()
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load := b.NewValue2IA(v.Pos, OpAMD64MOVLload, f.Config.Types.UInt32, vo.Off(), v.Aux, v.Args[0], v.Args[1])
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v.Op = OpAMD64CMPLconst
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v.AuxInt = vo.Val()
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v.Aux = nil
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v.SetArgs1(load)
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case OpAMD64CMPWconstmem:
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case OpAMD64CMPWconstload:
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vo := v.AuxValAndOff()
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load := b.NewValue2IA(v.Pos, OpAMD64MOVWload, f.Config.Types.UInt16, vo.Off(), v.Aux, v.Args[0], v.Args[1])
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v.Op = OpAMD64CMPWconst
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v.AuxInt = vo.Val()
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v.Aux = nil
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v.SetArgs1(load)
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case OpAMD64CMPBconstmem:
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case OpAMD64CMPBconstload:
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vo := v.AuxValAndOff()
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load := b.NewValue2IA(v.Pos, OpAMD64MOVBload, f.Config.Types.UInt8, vo.Off(), v.Aux, v.Args[0], v.Args[1])
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v.Op = OpAMD64CMPBconst
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@ -635,12 +635,12 @@
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(MOVSSstore [off1] {sym} (ADDLconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVSSstore [off1+off2] {sym} ptr val mem)
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(MOVSDstore [off1] {sym} (ADDLconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVSDstore [off1+off2] {sym} ptr val mem)
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((ADD|SUB|AND|OR|XOR)Lmem [off1] {sym} val (ADDLconst [off2] base) mem) && is32Bit(off1+off2) ->
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((ADD|SUB|AND|OR|XOR)Lmem [off1+off2] {sym} val base mem)
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((ADD|SUB|MUL)SSmem [off1] {sym} val (ADDLconst [off2] base) mem) && is32Bit(off1+off2) ->
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((ADD|SUB|MUL)SSmem [off1+off2] {sym} val base mem)
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((ADD|SUB|MUL)SDmem [off1] {sym} val (ADDLconst [off2] base) mem) && is32Bit(off1+off2) ->
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((ADD|SUB|MUL)SDmem [off1+off2] {sym} val base mem)
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((ADD|SUB|AND|OR|XOR)Lload [off1] {sym} val (ADDLconst [off2] base) mem) && is32Bit(off1+off2) ->
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((ADD|SUB|AND|OR|XOR)Lload [off1+off2] {sym} val base mem)
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((ADD|SUB|MUL)SSload [off1] {sym} val (ADDLconst [off2] base) mem) && is32Bit(off1+off2) ->
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((ADD|SUB|MUL)SSload [off1+off2] {sym} val base mem)
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((ADD|SUB|MUL)SDload [off1] {sym} val (ADDLconst [off2] base) mem) && is32Bit(off1+off2) ->
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((ADD|SUB|MUL)SDload [off1+off2] {sym} val base mem)
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((ADD|SUB|AND|OR|XOR)Lmodify [off1] {sym} (ADDLconst [off2] base) val mem) && is32Bit(off1+off2) ->
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((ADD|SUB|AND|OR|XOR)Lmodify [off1+off2] {sym} base val mem)
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@ -756,15 +756,15 @@
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(MOVSDstore [off1] {sym1} (LEAL8 [off2] {sym2} ptr idx) val mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
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(MOVSDstoreidx8 [off1+off2] {mergeSym(sym1,sym2)} ptr idx val mem)
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((ADD|SUB|AND|OR|XOR)Lmem [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
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((ADD|SUB|AND|OR|XOR)Lload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
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&& is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) ->
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((ADD|SUB|AND|OR|XOR)Lmem [off1+off2] {mergeSym(sym1,sym2)} val base mem)
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((ADD|SUB|MUL)SSmem [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
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((ADD|SUB|AND|OR|XOR)Lload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
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((ADD|SUB|MUL)SSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
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&& is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) ->
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((ADD|SUB|MUL)SSmem [off1+off2] {mergeSym(sym1,sym2)} val base mem)
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((ADD|SUB|MUL)SDmem [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
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((ADD|SUB|MUL)SSload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
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((ADD|SUB|MUL)SDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
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&& is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) ->
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((ADD|SUB|MUL)SDmem [off1+off2] {mergeSym(sym1,sym2)} val base mem)
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((ADD|SUB|MUL)SDload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
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((ADD|SUB|AND|OR|XOR)Lmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
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&& is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared) ->
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((ADD|SUB|AND|OR|XOR)Lmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
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@ -845,10 +845,10 @@
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(MOVSDstoreidx8 [c] {sym} ptr (ADDLconst [d] idx) val mem) -> (MOVSDstoreidx8 [int64(int32(c+8*d))] {sym} ptr idx val mem)
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// Merge load/store to op
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((ADD|AND|OR|XOR|SUB)L x l:(MOVLload [off] {sym} ptr mem)) && canMergeLoad(v, l, x) && clobber(l) -> ((ADD|AND|OR|XOR|SUB)Lmem x [off] {sym} ptr mem)
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((ADD|SUB|MUL)SD x l:(MOVSDload [off] {sym} ptr mem)) && canMergeLoad(v, l, x) && !config.use387 && clobber(l) -> ((ADD|SUB|MUL)SDmem x [off] {sym} ptr mem)
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((ADD|SUB|MUL)SS x l:(MOVSSload [off] {sym} ptr mem)) && canMergeLoad(v, l, x) && !config.use387 && clobber(l) -> ((ADD|SUB|MUL)SSmem x [off] {sym} ptr mem)
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(MOVLstore {sym} [off] ptr y:((ADD|AND|OR|XOR)Lmem x [off] {sym} ptr mem) mem) && y.Uses==1 && clobber(y) -> ((ADD|AND|OR|XOR)Lmodify [off] {sym} ptr x mem)
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((ADD|AND|OR|XOR|SUB)L x l:(MOVLload [off] {sym} ptr mem)) && canMergeLoad(v, l, x) && clobber(l) -> ((ADD|AND|OR|XOR|SUB)Lload x [off] {sym} ptr mem)
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((ADD|SUB|MUL)SD x l:(MOVSDload [off] {sym} ptr mem)) && canMergeLoad(v, l, x) && !config.use387 && clobber(l) -> ((ADD|SUB|MUL)SDload x [off] {sym} ptr mem)
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((ADD|SUB|MUL)SS x l:(MOVSSload [off] {sym} ptr mem)) && canMergeLoad(v, l, x) && !config.use387 && clobber(l) -> ((ADD|SUB|MUL)SSload x [off] {sym} ptr mem)
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(MOVLstore {sym} [off] ptr y:((ADD|AND|OR|XOR)Lload x [off] {sym} ptr mem) mem) && y.Uses==1 && clobber(y) -> ((ADD|AND|OR|XOR)Lmodify [off] {sym} ptr x mem)
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(MOVLstore {sym} [off] ptr y:((ADD|SUB|AND|OR|XOR)L l:(MOVLload [off] {sym} ptr mem) x) mem) && y.Uses==1 && l.Uses==1 && clobber(y) && clobber(l) ->
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((ADD|SUB|AND|OR|XOR)Lmodify [off] {sym} ptr x mem)
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@ -175,12 +175,12 @@ func init() {
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{name: "MOVSDstoreidx1", argLength: 4, reg: fpstoreidx, asm: "MOVSD", aux: "SymOff", symEffect: "Write"}, // fp64 indexed by i store
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{name: "MOVSDstoreidx8", argLength: 4, reg: fpstoreidx, asm: "MOVSD", aux: "SymOff", symEffect: "Write"}, // fp64 indexed by 8i store
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{name: "ADDSSmem", argLength: 3, reg: fp21load, asm: "ADDSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
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{name: "ADDSDmem", argLength: 3, reg: fp21load, asm: "ADDSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp64 arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
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{name: "SUBSSmem", argLength: 3, reg: fp21load, asm: "SUBSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
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{name: "SUBSDmem", argLength: 3, reg: fp21load, asm: "SUBSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp64 arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
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{name: "MULSSmem", argLength: 3, reg: fp21load, asm: "MULSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 * tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
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{name: "MULSDmem", argLength: 3, reg: fp21load, asm: "MULSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp64 arg0 * tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
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{name: "ADDSSload", argLength: 3, reg: fp21load, asm: "ADDSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
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{name: "ADDSDload", argLength: 3, reg: fp21load, asm: "ADDSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp64 arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
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{name: "SUBSSload", argLength: 3, reg: fp21load, asm: "SUBSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
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{name: "SUBSDload", argLength: 3, reg: fp21load, asm: "SUBSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp64 arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
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{name: "MULSSload", argLength: 3, reg: fp21load, asm: "MULSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 * tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
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{name: "MULSDload", argLength: 3, reg: fp21load, asm: "MULSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp64 arg0 * tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
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// binary ops
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{name: "ADDL", argLength: 2, reg: gp21sp, asm: "ADDL", commutative: true, clobberFlags: true}, // arg0 + arg1
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@ -267,11 +267,11 @@ func init() {
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{name: "ROLWconst", argLength: 1, reg: gp11, asm: "ROLW", aux: "Int16", resultInArg0: true, clobberFlags: true}, // arg0 rotate left auxint, rotate amount 0-15
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{name: "ROLBconst", argLength: 1, reg: gp11, asm: "ROLB", aux: "Int8", resultInArg0: true, clobberFlags: true}, // arg0 rotate left auxint, rotate amount 0-7
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{name: "ADDLmem", argLength: 3, reg: gp21load, asm: "ADDL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
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{name: "SUBLmem", argLength: 3, reg: gp21load, asm: "SUBL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
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{name: "ANDLmem", argLength: 3, reg: gp21load, asm: "ANDL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 & tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
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{name: "ORLmem", argLength: 3, reg: gp21load, asm: "ORL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 | tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
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{name: "XORLmem", argLength: 3, reg: gp21load, asm: "XORL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 ^ tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
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{name: "ADDLload", argLength: 3, reg: gp21load, asm: "ADDL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "SUBLload", argLength: 3, reg: gp21load, asm: "SUBL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "ANDLload", argLength: 3, reg: gp21load, asm: "ANDL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 & tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "ORLload", argLength: 3, reg: gp21load, asm: "ORL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 | tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "XORLload", argLength: 3, reg: gp21load, asm: "XORL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 ^ tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
|
||||
// unary ops
|
||||
{name: "NEGL", argLength: 1, reg: gp11, asm: "NEGL", resultInArg0: true, clobberFlags: true}, // -arg0
|
||||
|
@ -456,16 +456,16 @@
|
||||
(Addr {sym} base) && config.PtrSize == 8 -> (LEAQ {sym} base)
|
||||
(Addr {sym} base) && config.PtrSize == 4 -> (LEAL {sym} base)
|
||||
|
||||
(MOVBstore [off] {sym} ptr y:(SETL x) mem) && y.Uses == 1 -> (SETLmem [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr y:(SETLE x) mem) && y.Uses == 1 -> (SETLEmem [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr y:(SETG x) mem) && y.Uses == 1 -> (SETGmem [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr y:(SETGE x) mem) && y.Uses == 1 -> (SETGEmem [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr y:(SETEQ x) mem) && y.Uses == 1 -> (SETEQmem [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr y:(SETNE x) mem) && y.Uses == 1 -> (SETNEmem [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr y:(SETB x) mem) && y.Uses == 1 -> (SETBmem [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr y:(SETBE x) mem) && y.Uses == 1 -> (SETBEmem [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr y:(SETA x) mem) && y.Uses == 1 -> (SETAmem [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr y:(SETAE x) mem) && y.Uses == 1 -> (SETAEmem [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr y:(SETL x) mem) && y.Uses == 1 -> (SETLstore [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr y:(SETLE x) mem) && y.Uses == 1 -> (SETLEstore [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr y:(SETG x) mem) && y.Uses == 1 -> (SETGstore [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr y:(SETGE x) mem) && y.Uses == 1 -> (SETGEstore [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr y:(SETEQ x) mem) && y.Uses == 1 -> (SETEQstore [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr y:(SETNE x) mem) && y.Uses == 1 -> (SETNEstore [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr y:(SETB x) mem) && y.Uses == 1 -> (SETBstore [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr y:(SETBE x) mem) && y.Uses == 1 -> (SETBEstore [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr y:(SETA x) mem) && y.Uses == 1 -> (SETAstore [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr y:(SETAE x) mem) && y.Uses == 1 -> (SETAEstore [off] {sym} ptr x mem)
|
||||
|
||||
// block rewrites
|
||||
(If (SETL cmp) yes no) -> (LT cmp yes no)
|
||||
@ -562,17 +562,17 @@
|
||||
-> (SET(B|AE) (BTQconst [log2(c)] x))
|
||||
(SET(NE|EQ) (TESTQ (MOVQconst [c]) x)) && isUint64PowerOfTwo(c) && !config.nacl
|
||||
-> (SET(B|AE) (BTQconst [log2(c)] x))
|
||||
// SET..mem variant
|
||||
(SET(NE|EQ)mem [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) && !config.nacl
|
||||
-> (SET(B|AE)mem [off] {sym} ptr (BTL x y) mem)
|
||||
(SET(NE|EQ)mem [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) && !config.nacl
|
||||
-> (SET(B|AE)mem [off] {sym} ptr (BTQ x y) mem)
|
||||
(SET(NE|EQ)mem [off] {sym} ptr (TESTLconst [c] x) mem) && isUint32PowerOfTwo(c) && !config.nacl
|
||||
-> (SET(B|AE)mem [off] {sym} ptr (BTLconst [log2uint32(c)] x) mem)
|
||||
(SET(NE|EQ)mem [off] {sym} ptr (TESTQconst [c] x) mem) && isUint64PowerOfTwo(c) && !config.nacl
|
||||
-> (SET(B|AE)mem [off] {sym} ptr (BTQconst [log2(c)] x) mem)
|
||||
(SET(NE|EQ)mem [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) && isUint64PowerOfTwo(c) && !config.nacl
|
||||
-> (SET(B|AE)mem [off] {sym} ptr (BTQconst [log2(c)] x) mem)
|
||||
// SET..store variant
|
||||
(SET(NE|EQ)store [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem) && !config.nacl
|
||||
-> (SET(B|AE)store [off] {sym} ptr (BTL x y) mem)
|
||||
(SET(NE|EQ)store [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem) && !config.nacl
|
||||
-> (SET(B|AE)store [off] {sym} ptr (BTQ x y) mem)
|
||||
(SET(NE|EQ)store [off] {sym} ptr (TESTLconst [c] x) mem) && isUint32PowerOfTwo(c) && !config.nacl
|
||||
-> (SET(B|AE)store [off] {sym} ptr (BTLconst [log2uint32(c)] x) mem)
|
||||
(SET(NE|EQ)store [off] {sym} ptr (TESTQconst [c] x) mem) && isUint64PowerOfTwo(c) && !config.nacl
|
||||
-> (SET(B|AE)store [off] {sym} ptr (BTQconst [log2(c)] x) mem)
|
||||
(SET(NE|EQ)store [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem) && isUint64PowerOfTwo(c) && !config.nacl
|
||||
-> (SET(B|AE)store [off] {sym} ptr (BTQconst [log2(c)] x) mem)
|
||||
|
||||
// Handle bit-testing in the form (a>>b)&1 != 0 by building the above rules
|
||||
// and further combining shifts.
|
||||
@ -586,9 +586,9 @@
|
||||
// Rewrite a & 1 != 1 into a & 1 == 0.
|
||||
// Among other things, this lets us turn (a>>b)&1 != 1 into a bit test.
|
||||
(SET(NE|EQ) (CMPLconst [1] s:(ANDLconst [1] _))) -> (SET(EQ|NE) (CMPLconst [0] s))
|
||||
(SET(NE|EQ)mem [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) -> (SET(EQ|NE)mem [off] {sym} ptr (CMPLconst [0] s) mem)
|
||||
(SET(NE|EQ)store [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem) -> (SET(EQ|NE)store [off] {sym} ptr (CMPLconst [0] s) mem)
|
||||
(SET(NE|EQ) (CMPQconst [1] s:(ANDQconst [1] _))) -> (SET(EQ|NE) (CMPQconst [0] s))
|
||||
(SET(NE|EQ)mem [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) -> (SET(EQ|NE)mem [off] {sym} ptr (CMPQconst [0] s) mem)
|
||||
(SET(NE|EQ)store [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem) -> (SET(EQ|NE)store [off] {sym} ptr (CMPQconst [0] s) mem)
|
||||
|
||||
// Recognize bit setting (a |= 1<<b) and toggling (a ^= 1<<b)
|
||||
(OR(Q|L) (SHL(Q|L) (MOV(Q|L)const [1]) y) x) && !config.nacl -> (BTS(Q|L) x y)
|
||||
@ -639,29 +639,29 @@
|
||||
-> ((SETB|SETAE|ULT|UGE) (BTQconst [63] x))
|
||||
((SETNE|SETEQ|NE|EQ) (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2)) && z1==z2 && !config.nacl
|
||||
-> ((SETB|SETAE|ULT|UGE) (BTQconst [31] x))
|
||||
(SET(NE|EQ)mem [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) && z1==z2 && !config.nacl
|
||||
-> (SET(B|AE)mem [off] {sym} ptr (BTQconst [63] x) mem)
|
||||
(SET(NE|EQ)mem [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) && z1==z2 && !config.nacl
|
||||
-> (SET(B|AE)mem [off] {sym} ptr (BTLconst [31] x) mem)
|
||||
(SET(NE|EQ)store [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem) && z1==z2 && !config.nacl
|
||||
-> (SET(B|AE)store [off] {sym} ptr (BTQconst [63] x) mem)
|
||||
(SET(NE|EQ)store [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem) && z1==z2 && !config.nacl
|
||||
-> (SET(B|AE)store [off] {sym} ptr (BTLconst [31] x) mem)
|
||||
|
||||
((SETNE|SETEQ|NE|EQ) (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2)) && z1==z2 && !config.nacl
|
||||
-> ((SETB|SETAE|ULT|UGE) (BTQconst [0] x))
|
||||
((SETNE|SETEQ|NE|EQ) (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2)) && z1==z2 && !config.nacl
|
||||
-> ((SETB|SETAE|ULT|UGE) (BTLconst [0] x))
|
||||
(SET(NE|EQ)mem [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) && z1==z2 && !config.nacl
|
||||
-> (SET(B|AE)mem [off] {sym} ptr (BTQconst [0] x) mem)
|
||||
(SET(NE|EQ)mem [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) && z1==z2 && !config.nacl
|
||||
-> (SET(B|AE)mem [off] {sym} ptr (BTLconst [0] x) mem)
|
||||
(SET(NE|EQ)store [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem) && z1==z2 && !config.nacl
|
||||
-> (SET(B|AE)store [off] {sym} ptr (BTQconst [0] x) mem)
|
||||
(SET(NE|EQ)store [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem) && z1==z2 && !config.nacl
|
||||
-> (SET(B|AE)store [off] {sym} ptr (BTLconst [0] x) mem)
|
||||
|
||||
// Special-case manually testing last bit with "a>>63 != 0" (without "&1")
|
||||
((SETNE|SETEQ|NE|EQ) (TESTQ z1:(SHRQconst [63] x) z2)) && z1==z2 && !config.nacl
|
||||
-> ((SETB|SETAE|ULT|UGE) (BTQconst [63] x))
|
||||
((SETNE|SETEQ|NE|EQ) (TESTL z1:(SHRLconst [31] x) z2)) && z1==z2 && !config.nacl
|
||||
-> ((SETB|SETAE|ULT|UGE) (BTLconst [31] x))
|
||||
(SET(NE|EQ)mem [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) && z1==z2 && !config.nacl
|
||||
-> (SET(B|AE)mem [off] {sym} ptr (BTQconst [63] x) mem)
|
||||
(SET(NE|EQ)mem [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) && z1==z2 && !config.nacl
|
||||
-> (SET(B|AE)mem [off] {sym} ptr (BTLconst [31] x) mem)
|
||||
(SET(NE|EQ)store [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem) && z1==z2 && !config.nacl
|
||||
-> (SET(B|AE)store [off] {sym} ptr (BTQconst [63] x) mem)
|
||||
(SET(NE|EQ)store [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem) && z1==z2 && !config.nacl
|
||||
-> (SET(B|AE)store [off] {sym} ptr (BTLconst [31] x) mem)
|
||||
|
||||
// Fold combinations of bit ops on same bit. An example is math.Copysign(c,-1)
|
||||
(BTS(Q|L)const [c] (BTR(Q|L)const [c] x)) -> (BTS(Q|L)const [c] x)
|
||||
@ -947,16 +947,16 @@
|
||||
(SETEQ (InvertFlags x)) -> (SETEQ x)
|
||||
(SETNE (InvertFlags x)) -> (SETNE x)
|
||||
|
||||
(SETLmem [off] {sym} ptr (InvertFlags x) mem) -> (SETGmem [off] {sym} ptr x mem)
|
||||
(SETGmem [off] {sym} ptr (InvertFlags x) mem) -> (SETLmem [off] {sym} ptr x mem)
|
||||
(SETBmem [off] {sym} ptr (InvertFlags x) mem) -> (SETAmem [off] {sym} ptr x mem)
|
||||
(SETAmem [off] {sym} ptr (InvertFlags x) mem) -> (SETBmem [off] {sym} ptr x mem)
|
||||
(SETLEmem [off] {sym} ptr (InvertFlags x) mem) -> (SETGEmem [off] {sym} ptr x mem)
|
||||
(SETGEmem [off] {sym} ptr (InvertFlags x) mem) -> (SETLEmem [off] {sym} ptr x mem)
|
||||
(SETBEmem [off] {sym} ptr (InvertFlags x) mem) -> (SETAEmem [off] {sym} ptr x mem)
|
||||
(SETAEmem [off] {sym} ptr (InvertFlags x) mem) -> (SETBEmem [off] {sym} ptr x mem)
|
||||
(SETEQmem [off] {sym} ptr (InvertFlags x) mem) -> (SETEQmem [off] {sym} ptr x mem)
|
||||
(SETNEmem [off] {sym} ptr (InvertFlags x) mem) -> (SETNEmem [off] {sym} ptr x mem)
|
||||
(SETLstore [off] {sym} ptr (InvertFlags x) mem) -> (SETGstore [off] {sym} ptr x mem)
|
||||
(SETGstore [off] {sym} ptr (InvertFlags x) mem) -> (SETLstore [off] {sym} ptr x mem)
|
||||
(SETBstore [off] {sym} ptr (InvertFlags x) mem) -> (SETAstore [off] {sym} ptr x mem)
|
||||
(SETAstore [off] {sym} ptr (InvertFlags x) mem) -> (SETBstore [off] {sym} ptr x mem)
|
||||
(SETLEstore [off] {sym} ptr (InvertFlags x) mem) -> (SETGEstore [off] {sym} ptr x mem)
|
||||
(SETGEstore [off] {sym} ptr (InvertFlags x) mem) -> (SETLEstore [off] {sym} ptr x mem)
|
||||
(SETBEstore [off] {sym} ptr (InvertFlags x) mem) -> (SETAEstore [off] {sym} ptr x mem)
|
||||
(SETAEstore [off] {sym} ptr (InvertFlags x) mem) -> (SETBEstore [off] {sym} ptr x mem)
|
||||
(SETEQstore [off] {sym} ptr (InvertFlags x) mem) -> (SETEQstore [off] {sym} ptr x mem)
|
||||
(SETNEstore [off] {sym} ptr (InvertFlags x) mem) -> (SETNEstore [off] {sym} ptr x mem)
|
||||
|
||||
// sign extended loads
|
||||
// Note: The combined instruction must end up in the same block
|
||||
@ -1027,18 +1027,18 @@
|
||||
(MOV(Q|L|W|B|SS|SD|O)load [off1+off2] {sym} ptr mem)
|
||||
(MOV(Q|L|W|B|SS|SD|O)store [off1] {sym} (ADDQconst [off2] ptr) val mem) && is32Bit(off1+off2) ->
|
||||
(MOV(Q|L|W|B|SS|SD|O)store [off1+off2] {sym} ptr val mem)
|
||||
(SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)mem [off1] {sym} (ADDQconst [off2] base) val mem) && is32Bit(off1+off2) ->
|
||||
(SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)mem [off1+off2] {sym} base val mem)
|
||||
((ADD|SUB|AND|OR|XOR)Qmem [off1] {sym} val (ADDQconst [off2] base) mem) && is32Bit(off1+off2) ->
|
||||
((ADD|SUB|AND|OR|XOR)Qmem [off1+off2] {sym} val base mem)
|
||||
((ADD|SUB|AND|OR|XOR)Lmem [off1] {sym} val (ADDQconst [off2] base) mem) && is32Bit(off1+off2) ->
|
||||
((ADD|SUB|AND|OR|XOR)Lmem [off1+off2] {sym} val base mem)
|
||||
((ADD|SUB|MUL)SSmem [off1] {sym} val (ADDQconst [off2] base) mem) && is32Bit(off1+off2) ->
|
||||
((ADD|SUB|MUL)SSmem [off1+off2] {sym} val base mem)
|
||||
((ADD|SUB|MUL)SDmem [off1] {sym} val (ADDQconst [off2] base) mem) && is32Bit(off1+off2) ->
|
||||
((ADD|SUB|MUL)SDmem [off1+off2] {sym} val base mem)
|
||||
(ADD(L|Q)constmem [valoff1] {sym} (ADDQconst [off2] base) mem) && ValAndOff(valoff1).canAdd(off2) ->
|
||||
(ADD(L|Q)constmem [ValAndOff(valoff1).add(off2)] {sym} base mem)
|
||||
(SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)store [off1] {sym} (ADDQconst [off2] base) val mem) && is32Bit(off1+off2) ->
|
||||
(SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)store [off1+off2] {sym} base val mem)
|
||||
((ADD|SUB|AND|OR|XOR)Qload [off1] {sym} val (ADDQconst [off2] base) mem) && is32Bit(off1+off2) ->
|
||||
((ADD|SUB|AND|OR|XOR)Qload [off1+off2] {sym} val base mem)
|
||||
((ADD|SUB|AND|OR|XOR)Lload [off1] {sym} val (ADDQconst [off2] base) mem) && is32Bit(off1+off2) ->
|
||||
((ADD|SUB|AND|OR|XOR)Lload [off1+off2] {sym} val base mem)
|
||||
((ADD|SUB|MUL)SSload [off1] {sym} val (ADDQconst [off2] base) mem) && is32Bit(off1+off2) ->
|
||||
((ADD|SUB|MUL)SSload [off1+off2] {sym} val base mem)
|
||||
((ADD|SUB|MUL)SDload [off1] {sym} val (ADDQconst [off2] base) mem) && is32Bit(off1+off2) ->
|
||||
((ADD|SUB|MUL)SDload [off1+off2] {sym} val base mem)
|
||||
(ADD(L|Q)constmodify [valoff1] {sym} (ADDQconst [off2] base) mem) && ValAndOff(valoff1).canAdd(off2) ->
|
||||
(ADD(L|Q)constmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
|
||||
|
||||
// Fold constants into stores.
|
||||
(MOVQstore [off] {sym} ptr (MOVQconst [c]) mem) && validValAndOff(c,off) ->
|
||||
@ -1064,24 +1064,24 @@
|
||||
(MOV(Q|L|W|B|SS|SD|O)store [off1+off2] {mergeSym(sym1,sym2)} base val mem)
|
||||
(MOV(Q|L|W|B)storeconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem) && canMergeSym(sym1, sym2) && ValAndOff(sc).canAdd(off) ->
|
||||
(MOV(Q|L|W|B)storeconst [ValAndOff(sc).add(off)] {mergeSym(sym1, sym2)} ptr mem)
|
||||
(SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)mem [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
|
||||
(SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)store [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
|
||||
&& is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
|
||||
(SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)mem [off1+off2] {mergeSym(sym1,sym2)} base val mem)
|
||||
((ADD|SUB|AND|OR|XOR)Qmem [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
|
||||
(SET(L|G|B|A|LE|GE|BE|AE|EQ|NE)store [off1+off2] {mergeSym(sym1,sym2)} base val mem)
|
||||
((ADD|SUB|AND|OR|XOR)Qload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
|
||||
&& is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
|
||||
((ADD|SUB|AND|OR|XOR)Qmem [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
((ADD|SUB|AND|OR|XOR)Lmem [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
|
||||
((ADD|SUB|AND|OR|XOR)Qload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
((ADD|SUB|AND|OR|XOR)Lload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
|
||||
&& is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
|
||||
((ADD|SUB|AND|OR|XOR)Lmem [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
((ADD|SUB|MUL)SSmem [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
|
||||
((ADD|SUB|AND|OR|XOR)Lload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
((ADD|SUB|MUL)SSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
|
||||
&& is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
|
||||
((ADD|SUB|MUL)SSmem [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
((ADD|SUB|MUL)SDmem [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
|
||||
((ADD|SUB|MUL)SSload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
((ADD|SUB|MUL)SDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
|
||||
&& is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
|
||||
((ADD|SUB|MUL)SDmem [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
(ADD(L|Q)constmem [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
|
||||
((ADD|SUB|MUL)SDload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
(ADD(L|Q)constmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
|
||||
&& ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) ->
|
||||
(ADD(L|Q)constmem [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
|
||||
(ADD(L|Q)constmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
|
||||
|
||||
// generating indexed loads and stores
|
||||
(MOV(B|W|L|Q|SS|SD)load [off1] {sym1} (LEAQ1 [off2] {sym2} ptr idx) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
|
||||
@ -1275,65 +1275,65 @@
|
||||
((SETNE|SETG|SETGE|SETA|SETAE) (FlagGT_UGT)) -> (MOVLconst [1])
|
||||
((SETEQ|SETL|SETLE|SETB|SETBE) (FlagGT_UGT)) -> (MOVLconst [0])
|
||||
|
||||
(SETEQmem [off] {sym} ptr x:(FlagEQ) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETEQmem [off] {sym} ptr x:(FlagLT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETEQmem [off] {sym} ptr x:(FlagLT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETEQmem [off] {sym} ptr x:(FlagGT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETEQmem [off] {sym} ptr x:(FlagGT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETEQstore [off] {sym} ptr x:(FlagEQ) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETEQstore [off] {sym} ptr x:(FlagLT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETEQstore [off] {sym} ptr x:(FlagLT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETEQstore [off] {sym} ptr x:(FlagGT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETEQstore [off] {sym} ptr x:(FlagGT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
|
||||
(SETNEmem [off] {sym} ptr x:(FlagEQ) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETNEmem [off] {sym} ptr x:(FlagLT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETNEmem [off] {sym} ptr x:(FlagLT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETNEmem [off] {sym} ptr x:(FlagGT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETNEmem [off] {sym} ptr x:(FlagGT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETNEstore [off] {sym} ptr x:(FlagEQ) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETNEstore [off] {sym} ptr x:(FlagLT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETNEstore [off] {sym} ptr x:(FlagLT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETNEstore [off] {sym} ptr x:(FlagGT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETNEstore [off] {sym} ptr x:(FlagGT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
|
||||
(SETLmem [off] {sym} ptr x:(FlagEQ) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETLmem [off] {sym} ptr x:(FlagLT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETLmem [off] {sym} ptr x:(FlagLT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETLmem [off] {sym} ptr x:(FlagGT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETLmem [off] {sym} ptr x:(FlagGT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETLstore [off] {sym} ptr x:(FlagEQ) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETLstore [off] {sym} ptr x:(FlagLT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETLstore [off] {sym} ptr x:(FlagLT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETLstore [off] {sym} ptr x:(FlagGT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETLstore [off] {sym} ptr x:(FlagGT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
|
||||
(SETLEmem [off] {sym} ptr x:(FlagEQ) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETLEmem [off] {sym} ptr x:(FlagLT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETLEmem [off] {sym} ptr x:(FlagLT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETLEmem [off] {sym} ptr x:(FlagGT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETLEmem [off] {sym} ptr x:(FlagGT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETLEstore [off] {sym} ptr x:(FlagEQ) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETLEstore [off] {sym} ptr x:(FlagLT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETLEstore [off] {sym} ptr x:(FlagLT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETLEstore [off] {sym} ptr x:(FlagGT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETLEstore [off] {sym} ptr x:(FlagGT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
|
||||
(SETGmem [off] {sym} ptr x:(FlagEQ) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETGmem [off] {sym} ptr x:(FlagLT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETGmem [off] {sym} ptr x:(FlagLT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETGmem [off] {sym} ptr x:(FlagGT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETGmem [off] {sym} ptr x:(FlagGT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETGstore [off] {sym} ptr x:(FlagEQ) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETGstore [off] {sym} ptr x:(FlagLT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETGstore [off] {sym} ptr x:(FlagLT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETGstore [off] {sym} ptr x:(FlagGT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETGstore [off] {sym} ptr x:(FlagGT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
|
||||
(SETGEmem [off] {sym} ptr x:(FlagEQ) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETGEmem [off] {sym} ptr x:(FlagLT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETGEmem [off] {sym} ptr x:(FlagLT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETGEmem [off] {sym} ptr x:(FlagGT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETGEmem [off] {sym} ptr x:(FlagGT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETGEstore [off] {sym} ptr x:(FlagEQ) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETGEstore [off] {sym} ptr x:(FlagLT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETGEstore [off] {sym} ptr x:(FlagLT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETGEstore [off] {sym} ptr x:(FlagGT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETGEstore [off] {sym} ptr x:(FlagGT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
|
||||
(SETBmem [off] {sym} ptr x:(FlagEQ) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETBmem [off] {sym} ptr x:(FlagLT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETBmem [off] {sym} ptr x:(FlagLT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETBmem [off] {sym} ptr x:(FlagGT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETBmem [off] {sym} ptr x:(FlagGT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETBstore [off] {sym} ptr x:(FlagEQ) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETBstore [off] {sym} ptr x:(FlagLT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETBstore [off] {sym} ptr x:(FlagLT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETBstore [off] {sym} ptr x:(FlagGT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETBstore [off] {sym} ptr x:(FlagGT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
|
||||
(SETBEmem [off] {sym} ptr x:(FlagEQ) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETBEmem [off] {sym} ptr x:(FlagLT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETBEmem [off] {sym} ptr x:(FlagLT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETBEmem [off] {sym} ptr x:(FlagGT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETBEmem [off] {sym} ptr x:(FlagGT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETBEstore [off] {sym} ptr x:(FlagEQ) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETBEstore [off] {sym} ptr x:(FlagLT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETBEstore [off] {sym} ptr x:(FlagLT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETBEstore [off] {sym} ptr x:(FlagGT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETBEstore [off] {sym} ptr x:(FlagGT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
|
||||
(SETAmem [off] {sym} ptr x:(FlagEQ) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETAmem [off] {sym} ptr x:(FlagLT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETAmem [off] {sym} ptr x:(FlagLT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETAmem [off] {sym} ptr x:(FlagGT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETAmem [off] {sym} ptr x:(FlagGT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETAstore [off] {sym} ptr x:(FlagEQ) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETAstore [off] {sym} ptr x:(FlagLT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETAstore [off] {sym} ptr x:(FlagLT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETAstore [off] {sym} ptr x:(FlagGT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETAstore [off] {sym} ptr x:(FlagGT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
|
||||
(SETAEmem [off] {sym} ptr x:(FlagEQ) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETAEmem [off] {sym} ptr x:(FlagLT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETAEmem [off] {sym} ptr x:(FlagLT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETAEmem [off] {sym} ptr x:(FlagGT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETAEmem [off] {sym} ptr x:(FlagGT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETAEstore [off] {sym} ptr x:(FlagEQ) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETAEstore [off] {sym} ptr x:(FlagLT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETAEstore [off] {sym} ptr x:(FlagLT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
(SETAEstore [off] {sym} ptr x:(FlagGT_ULT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [0]) mem)
|
||||
(SETAEstore [off] {sym} ptr x:(FlagGT_UGT) mem) -> (MOVBstore [off] {sym} ptr (MOVLconst <x.Type> [1]) mem)
|
||||
|
||||
// Remove redundant *const ops
|
||||
(ADDQconst [0] x) -> x
|
||||
@ -2263,10 +2263,10 @@
|
||||
|
||||
// Merge load and op
|
||||
// TODO: add indexed variants?
|
||||
((ADD|SUB|AND|OR|XOR)Q x l:(MOVQload [off] {sym} ptr mem)) && canMergeLoad(v, l, x) && clobber(l) -> ((ADD|SUB|AND|OR|XOR)Qmem x [off] {sym} ptr mem)
|
||||
((ADD|SUB|AND|OR|XOR)L x l:(MOVLload [off] {sym} ptr mem)) && canMergeLoad(v, l, x) && clobber(l) -> ((ADD|SUB|AND|OR|XOR)Lmem x [off] {sym} ptr mem)
|
||||
((ADD|SUB|MUL)SD x l:(MOVSDload [off] {sym} ptr mem)) && canMergeLoad(v, l, x) && clobber(l) -> ((ADD|SUB|MUL)SDmem x [off] {sym} ptr mem)
|
||||
((ADD|SUB|MUL)SS x l:(MOVSSload [off] {sym} ptr mem)) && canMergeLoad(v, l, x) && clobber(l) -> ((ADD|SUB|MUL)SSmem x [off] {sym} ptr mem)
|
||||
((ADD|SUB|AND|OR|XOR)Q x l:(MOVQload [off] {sym} ptr mem)) && canMergeLoad(v, l, x) && clobber(l) -> ((ADD|SUB|AND|OR|XOR)Qload x [off] {sym} ptr mem)
|
||||
((ADD|SUB|AND|OR|XOR)L x l:(MOVLload [off] {sym} ptr mem)) && canMergeLoad(v, l, x) && clobber(l) -> ((ADD|SUB|AND|OR|XOR)Lload x [off] {sym} ptr mem)
|
||||
((ADD|SUB|MUL)SD x l:(MOVSDload [off] {sym} ptr mem)) && canMergeLoad(v, l, x) && clobber(l) -> ((ADD|SUB|MUL)SDload x [off] {sym} ptr mem)
|
||||
((ADD|SUB|MUL)SS x l:(MOVSSload [off] {sym} ptr mem)) && canMergeLoad(v, l, x) && clobber(l) -> ((ADD|SUB|MUL)SSload x [off] {sym} ptr mem)
|
||||
|
||||
// Merge ADDQconst and LEAQ into atomic loads.
|
||||
(MOVQatomicload [off1] {sym} (ADDQconst [off2] ptr) mem) && is32Bit(off1+off2) ->
|
||||
@ -2352,10 +2352,10 @@
|
||||
|
||||
(MOVQstore [off] {sym} ptr a:(ADDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem)
|
||||
&& isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) ->
|
||||
(ADDQconstmem {sym} [makeValAndOff(c,off)] ptr mem)
|
||||
(ADDQconstmodify {sym} [makeValAndOff(c,off)] ptr mem)
|
||||
(MOVLstore [off] {sym} ptr a:(ADDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem)
|
||||
&& isSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && validValAndOff(c,off) ->
|
||||
(ADDLconstmem {sym} [makeValAndOff(c,off)] ptr mem)
|
||||
(ADDLconstmodify {sym} [makeValAndOff(c,off)] ptr mem)
|
||||
|
||||
// float <-> int register moves, with no conversion.
|
||||
// These come up when compiling math.{Float{32,64}bits,Float{32,64}frombits}.
|
||||
@ -2365,28 +2365,28 @@
|
||||
(MOVSSload [off] {sym} ptr (MOVLstore [off] {sym} ptr val _)) -> (MOVLi2f val)
|
||||
|
||||
// Other load-like ops.
|
||||
(ADDQmem x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) -> (ADDQ x (MOVQf2i y))
|
||||
(ADDLmem x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) -> (ADDL x (MOVLf2i y))
|
||||
(SUBQmem x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) -> (SUBQ x (MOVQf2i y))
|
||||
(SUBLmem x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) -> (SUBL x (MOVLf2i y))
|
||||
(ANDQmem x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) -> (ANDQ x (MOVQf2i y))
|
||||
(ANDLmem x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) -> (ANDL x (MOVLf2i y))
|
||||
( ORQmem x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) -> ( ORQ x (MOVQf2i y))
|
||||
( ORLmem x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) -> ( ORL x (MOVLf2i y))
|
||||
(XORQmem x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) -> (XORQ x (MOVQf2i y))
|
||||
(XORLmem x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) -> (XORL x (MOVLf2i y))
|
||||
(ADDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) -> (ADDQ x (MOVQf2i y))
|
||||
(ADDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) -> (ADDL x (MOVLf2i y))
|
||||
(SUBQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) -> (SUBQ x (MOVQf2i y))
|
||||
(SUBLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) -> (SUBL x (MOVLf2i y))
|
||||
(ANDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) -> (ANDQ x (MOVQf2i y))
|
||||
(ANDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) -> (ANDL x (MOVLf2i y))
|
||||
( ORQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) -> ( ORQ x (MOVQf2i y))
|
||||
( ORLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) -> ( ORL x (MOVLf2i y))
|
||||
(XORQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _)) -> (XORQ x (MOVQf2i y))
|
||||
(XORLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _)) -> (XORL x (MOVLf2i y))
|
||||
|
||||
(ADDQconstmem [valOff] {sym} ptr (MOVSDstore [ValAndOff(valOff).Off()] {sym} ptr x _)) ->
|
||||
(ADDQconstmodify [valOff] {sym} ptr (MOVSDstore [ValAndOff(valOff).Off()] {sym} ptr x _)) ->
|
||||
(ADDQconst [ValAndOff(valOff).Val()] (MOVQf2i x))
|
||||
(ADDLconstmem [valOff] {sym} ptr (MOVSSstore [ValAndOff(valOff).Off()] {sym} ptr x _)) ->
|
||||
(ADDLconstmodify [valOff] {sym} ptr (MOVSSstore [ValAndOff(valOff).Off()] {sym} ptr x _)) ->
|
||||
(ADDLconst [ValAndOff(valOff).Val()] (MOVLf2i x))
|
||||
|
||||
(ADDSDmem x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) -> (ADDSD x (MOVQi2f y))
|
||||
(ADDSSmem x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) -> (ADDSS x (MOVLi2f y))
|
||||
(SUBSDmem x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) -> (SUBSD x (MOVQi2f y))
|
||||
(SUBSSmem x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) -> (SUBSS x (MOVLi2f y))
|
||||
(MULSDmem x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) -> (MULSD x (MOVQi2f y))
|
||||
(MULSSmem x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) -> (MULSS x (MOVLi2f y))
|
||||
(ADDSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) -> (ADDSD x (MOVQi2f y))
|
||||
(ADDSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) -> (ADDSS x (MOVLi2f y))
|
||||
(SUBSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) -> (SUBSD x (MOVQi2f y))
|
||||
(SUBSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) -> (SUBSS x (MOVLi2f y))
|
||||
(MULSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _)) -> (MULSD x (MOVQi2f y))
|
||||
(MULSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _)) -> (MULSS x (MOVLi2f y))
|
||||
|
||||
// Redirect stores to use the other register set.
|
||||
(MOVQstore [off] {sym} ptr (MOVQf2i val) mem) -> (MOVSDstore [off] {sym} ptr val mem)
|
||||
@ -2407,23 +2407,23 @@
|
||||
|
||||
// Fold loads into compares
|
||||
// Note: these may be undone by the flagalloc pass.
|
||||
(CMP(Q|L|W|B) l:(MOV(Q|L|W|B)load {sym} [off] ptr mem) x) && canMergeLoad(v, l, x) && clobber(l) -> (CMP(Q|L|W|B)mem {sym} [off] ptr x mem)
|
||||
(CMP(Q|L|W|B) x l:(MOV(Q|L|W|B)load {sym} [off] ptr mem)) && canMergeLoad(v, l, x) && clobber(l) -> (InvertFlags (CMP(Q|L|W|B)mem {sym} [off] ptr x mem))
|
||||
(CMP(Q|L|W|B) l:(MOV(Q|L|W|B)load {sym} [off] ptr mem) x) && canMergeLoad(v, l, x) && clobber(l) -> (CMP(Q|L|W|B)load {sym} [off] ptr x mem)
|
||||
(CMP(Q|L|W|B) x l:(MOV(Q|L|W|B)load {sym} [off] ptr mem)) && canMergeLoad(v, l, x) && clobber(l) -> (InvertFlags (CMP(Q|L|W|B)load {sym} [off] ptr x mem))
|
||||
|
||||
(CMP(Q|L|W|B)const l:(MOV(Q|L|W|B)load {sym} [off] ptr mem) [c])
|
||||
&& l.Uses == 1
|
||||
&& validValAndOff(c, off)
|
||||
&& clobber(l) ->
|
||||
@l.Block (CMP(Q|L|W|B)constmem {sym} [makeValAndOff(c,off)] ptr mem)
|
||||
@l.Block (CMP(Q|L|W|B)constload {sym} [makeValAndOff(c,off)] ptr mem)
|
||||
|
||||
(CMPQmem {sym} [off] ptr (MOVQconst [c]) mem) && validValAndOff(c,off) -> (CMPQconstmem {sym} [makeValAndOff(c,off)] ptr mem)
|
||||
(CMPLmem {sym} [off] ptr (MOVLconst [c]) mem) && validValAndOff(c,off) -> (CMPLconstmem {sym} [makeValAndOff(c,off)] ptr mem)
|
||||
(CMPWmem {sym} [off] ptr (MOVLconst [c]) mem) && validValAndOff(int64(int16(c)),off) -> (CMPWconstmem {sym} [makeValAndOff(int64(int16(c)),off)] ptr mem)
|
||||
(CMPBmem {sym} [off] ptr (MOVLconst [c]) mem) && validValAndOff(int64(int8(c)),off) -> (CMPBconstmem {sym} [makeValAndOff(int64(int8(c)),off)] ptr mem)
|
||||
(CMPQload {sym} [off] ptr (MOVQconst [c]) mem) && validValAndOff(c,off) -> (CMPQconstload {sym} [makeValAndOff(c,off)] ptr mem)
|
||||
(CMPLload {sym} [off] ptr (MOVLconst [c]) mem) && validValAndOff(c,off) -> (CMPLconstload {sym} [makeValAndOff(c,off)] ptr mem)
|
||||
(CMPWload {sym} [off] ptr (MOVLconst [c]) mem) && validValAndOff(int64(int16(c)),off) -> (CMPWconstload {sym} [makeValAndOff(int64(int16(c)),off)] ptr mem)
|
||||
(CMPBload {sym} [off] ptr (MOVLconst [c]) mem) && validValAndOff(int64(int8(c)),off) -> (CMPBconstload {sym} [makeValAndOff(int64(int8(c)),off)] ptr mem)
|
||||
|
||||
(TEST(Q|L|W|B) l:(MOV(Q|L|W|B)load {sym} [off] ptr mem) l2)
|
||||
&& l == l2
|
||||
&& l.Uses == 2
|
||||
&& validValAndOff(0,off)
|
||||
&& clobber(l) ->
|
||||
@l.Block (CMP(Q|L|W|B)constmem {sym} [makeValAndOff(0,off)] ptr mem)
|
||||
@l.Block (CMP(Q|L|W|B)constload {sym} [makeValAndOff(0,off)] ptr mem)
|
||||
|
@ -183,20 +183,20 @@ func init() {
|
||||
{name: "MOVSDstoreidx1", argLength: 4, reg: fpstoreidx, asm: "MOVSD", aux: "SymOff", symEffect: "Write"}, // fp64 indexed by i store
|
||||
{name: "MOVSDstoreidx8", argLength: 4, reg: fpstoreidx, asm: "MOVSD", aux: "SymOff", symEffect: "Write"}, // fp64 indexed by 8i store
|
||||
|
||||
{name: "ADDSSmem", argLength: 3, reg: fp21load, asm: "ADDSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "ADDSDmem", argLength: 3, reg: fp21load, asm: "ADDSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp64 arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "SUBSSmem", argLength: 3, reg: fp21load, asm: "SUBSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "SUBSDmem", argLength: 3, reg: fp21load, asm: "SUBSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp64 arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "MULSSmem", argLength: 3, reg: fp21load, asm: "MULSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 * tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "MULSDmem", argLength: 3, reg: fp21load, asm: "MULSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp64 arg0 * tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "ADDSSload", argLength: 3, reg: fp21load, asm: "ADDSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "ADDSDload", argLength: 3, reg: fp21load, asm: "ADDSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp64 arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "SUBSSload", argLength: 3, reg: fp21load, asm: "SUBSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "SUBSDload", argLength: 3, reg: fp21load, asm: "SUBSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp64 arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "MULSSload", argLength: 3, reg: fp21load, asm: "MULSS", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp32 arg0 * tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "MULSDload", argLength: 3, reg: fp21load, asm: "MULSD", aux: "SymOff", resultInArg0: true, faultOnNilArg1: true, symEffect: "Read"}, // fp64 arg0 * tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
|
||||
// binary ops
|
||||
{name: "ADDQ", argLength: 2, reg: gp21sp, asm: "ADDQ", commutative: true, clobberFlags: true}, // arg0 + arg1
|
||||
{name: "ADDL", argLength: 2, reg: gp21sp, asm: "ADDL", commutative: true, clobberFlags: true}, // arg0 + arg1
|
||||
{name: "ADDQconst", argLength: 1, reg: gp11sp, asm: "ADDQ", aux: "Int32", typ: "UInt64", clobberFlags: true}, // arg0 + auxint
|
||||
{name: "ADDLconst", argLength: 1, reg: gp11sp, asm: "ADDL", aux: "Int32", clobberFlags: true}, // arg0 + auxint
|
||||
{name: "ADDQconstmem", argLength: 2, reg: gpstoreconst, asm: "ADDQ", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Write"}, // add ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux, arg1=mem
|
||||
{name: "ADDLconstmem", argLength: 2, reg: gpstoreconst, asm: "ADDL", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Write"}, // add ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux, arg1=mem
|
||||
{name: "ADDQ", argLength: 2, reg: gp21sp, asm: "ADDQ", commutative: true, clobberFlags: true}, // arg0 + arg1
|
||||
{name: "ADDL", argLength: 2, reg: gp21sp, asm: "ADDL", commutative: true, clobberFlags: true}, // arg0 + arg1
|
||||
{name: "ADDQconst", argLength: 1, reg: gp11sp, asm: "ADDQ", aux: "Int32", typ: "UInt64", clobberFlags: true}, // arg0 + auxint
|
||||
{name: "ADDLconst", argLength: 1, reg: gp11sp, asm: "ADDL", aux: "Int32", clobberFlags: true}, // arg0 + auxint
|
||||
{name: "ADDQconstmodify", argLength: 2, reg: gpstoreconst, asm: "ADDQ", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write"}, // add ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux, arg1=mem
|
||||
{name: "ADDLconstmodify", argLength: 2, reg: gpstoreconst, asm: "ADDL", aux: "SymValAndOff", clobberFlags: true, faultOnNilArg0: true, symEffect: "Read,Write"}, // add ValAndOff(AuxInt).Val() to arg0+ValAndOff(AuxInt).Off()+aux, arg1=mem
|
||||
|
||||
{name: "SUBQ", argLength: 2, reg: gp21, asm: "SUBQ", resultInArg0: true, clobberFlags: true}, // arg0 - arg1
|
||||
{name: "SUBL", argLength: 2, reg: gp21, asm: "SUBL", resultInArg0: true, clobberFlags: true}, // arg0 - arg1
|
||||
@ -250,16 +250,16 @@ func init() {
|
||||
{name: "CMPBconst", argLength: 1, reg: gp1flags, asm: "CMPB", typ: "Flags", aux: "Int8"}, // arg0 compare to auxint
|
||||
|
||||
// compare *(arg0+auxint+aux) to arg1 (in that order). arg2=mem.
|
||||
{name: "CMPQmem", argLength: 3, reg: gp1flagsLoad, asm: "CMPQ", aux: "SymOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true},
|
||||
{name: "CMPLmem", argLength: 3, reg: gp1flagsLoad, asm: "CMPL", aux: "SymOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true},
|
||||
{name: "CMPWmem", argLength: 3, reg: gp1flagsLoad, asm: "CMPW", aux: "SymOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true},
|
||||
{name: "CMPBmem", argLength: 3, reg: gp1flagsLoad, asm: "CMPB", aux: "SymOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true},
|
||||
{name: "CMPQload", argLength: 3, reg: gp1flagsLoad, asm: "CMPQ", aux: "SymOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true},
|
||||
{name: "CMPLload", argLength: 3, reg: gp1flagsLoad, asm: "CMPL", aux: "SymOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true},
|
||||
{name: "CMPWload", argLength: 3, reg: gp1flagsLoad, asm: "CMPW", aux: "SymOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true},
|
||||
{name: "CMPBload", argLength: 3, reg: gp1flagsLoad, asm: "CMPB", aux: "SymOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true},
|
||||
|
||||
// compare *(arg0+ValAndOff(AuxInt).Off()+aux) to ValAndOff(AuxInt).Val() (in that order). arg1=mem.
|
||||
{name: "CMPQconstmem", argLength: 2, reg: gp0flagsLoad, asm: "CMPQ", aux: "SymValAndOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true},
|
||||
{name: "CMPLconstmem", argLength: 2, reg: gp0flagsLoad, asm: "CMPL", aux: "SymValAndOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true},
|
||||
{name: "CMPWconstmem", argLength: 2, reg: gp0flagsLoad, asm: "CMPW", aux: "SymValAndOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true},
|
||||
{name: "CMPBconstmem", argLength: 2, reg: gp0flagsLoad, asm: "CMPB", aux: "SymValAndOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true},
|
||||
{name: "CMPQconstload", argLength: 2, reg: gp0flagsLoad, asm: "CMPQ", aux: "SymValAndOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true},
|
||||
{name: "CMPLconstload", argLength: 2, reg: gp0flagsLoad, asm: "CMPL", aux: "SymValAndOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true},
|
||||
{name: "CMPWconstload", argLength: 2, reg: gp0flagsLoad, asm: "CMPW", aux: "SymValAndOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true},
|
||||
{name: "CMPBconstload", argLength: 2, reg: gp0flagsLoad, asm: "CMPB", aux: "SymValAndOff", typ: "Flags", symEffect: "Read", faultOnNilArg0: true},
|
||||
|
||||
{name: "UCOMISS", argLength: 2, reg: fp2flags, asm: "UCOMISS", typ: "Flags"}, // arg0 compare to arg1, f32
|
||||
{name: "UCOMISD", argLength: 2, reg: fp2flags, asm: "UCOMISD", typ: "Flags"}, // arg0 compare to arg1, f64
|
||||
@ -327,16 +327,16 @@ func init() {
|
||||
{name: "ROLWconst", argLength: 1, reg: gp11, asm: "ROLW", aux: "Int8", resultInArg0: true, clobberFlags: true}, // arg0 rotate left auxint, rotate amount 0-15
|
||||
{name: "ROLBconst", argLength: 1, reg: gp11, asm: "ROLB", aux: "Int8", resultInArg0: true, clobberFlags: true}, // arg0 rotate left auxint, rotate amount 0-7
|
||||
|
||||
{name: "ADDLmem", argLength: 3, reg: gp21load, asm: "ADDL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "ADDQmem", argLength: 3, reg: gp21load, asm: "ADDQ", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "SUBQmem", argLength: 3, reg: gp21load, asm: "SUBQ", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "SUBLmem", argLength: 3, reg: gp21load, asm: "SUBL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "ANDLmem", argLength: 3, reg: gp21load, asm: "ANDL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 & tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "ANDQmem", argLength: 3, reg: gp21load, asm: "ANDQ", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 & tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "ORQmem", argLength: 3, reg: gp21load, asm: "ORQ", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 | tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "ORLmem", argLength: 3, reg: gp21load, asm: "ORL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 | tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "XORQmem", argLength: 3, reg: gp21load, asm: "XORQ", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 ^ tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "XORLmem", argLength: 3, reg: gp21load, asm: "XORL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 ^ tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "ADDLload", argLength: 3, reg: gp21load, asm: "ADDL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "ADDQload", argLength: 3, reg: gp21load, asm: "ADDQ", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 + tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "SUBQload", argLength: 3, reg: gp21load, asm: "SUBQ", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "SUBLload", argLength: 3, reg: gp21load, asm: "SUBL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 - tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "ANDLload", argLength: 3, reg: gp21load, asm: "ANDL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 & tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "ANDQload", argLength: 3, reg: gp21load, asm: "ANDQ", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 & tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "ORQload", argLength: 3, reg: gp21load, asm: "ORQ", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 | tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "ORLload", argLength: 3, reg: gp21load, asm: "ORL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 | tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "XORQload", argLength: 3, reg: gp21load, asm: "XORQ", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 ^ tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
{name: "XORLload", argLength: 3, reg: gp21load, asm: "XORL", aux: "SymOff", resultInArg0: true, clobberFlags: true, faultOnNilArg1: true, symEffect: "Read"}, // arg0 ^ tmp, tmp loaded from arg1+auxint+aux, arg2 = mem
|
||||
|
||||
// unary ops
|
||||
{name: "NEGQ", argLength: 1, reg: gp11, asm: "NEGQ", resultInArg0: true, clobberFlags: true}, // -arg0
|
||||
@ -435,16 +435,16 @@ func init() {
|
||||
{name: "SETA", argLength: 1, reg: readflags, asm: "SETHI"}, // extract unsigned > condition from arg0
|
||||
{name: "SETAE", argLength: 1, reg: readflags, asm: "SETCC"}, // extract unsigned >= condition from arg0
|
||||
// Variants that store result to memory
|
||||
{name: "SETEQmem", argLength: 3, reg: gpstoreconst, asm: "SETEQ", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract == condition from arg1 to arg0+auxint+aux, arg2=mem
|
||||
{name: "SETNEmem", argLength: 3, reg: gpstoreconst, asm: "SETNE", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract != condition from arg1 to arg0+auxint+aux, arg2=mem
|
||||
{name: "SETLmem", argLength: 3, reg: gpstoreconst, asm: "SETLT", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract signed < condition from arg1 to arg0+auxint+aux, arg2=mem
|
||||
{name: "SETLEmem", argLength: 3, reg: gpstoreconst, asm: "SETLE", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract signed <= condition from arg1 to arg0+auxint+aux, arg2=mem
|
||||
{name: "SETGmem", argLength: 3, reg: gpstoreconst, asm: "SETGT", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract signed > condition from arg1 to arg0+auxint+aux, arg2=mem
|
||||
{name: "SETGEmem", argLength: 3, reg: gpstoreconst, asm: "SETGE", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract signed >= condition from arg1 to arg0+auxint+aux, arg2=mem
|
||||
{name: "SETBmem", argLength: 3, reg: gpstoreconst, asm: "SETCS", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract unsigned < condition from arg1 to arg0+auxint+aux, arg2=mem
|
||||
{name: "SETBEmem", argLength: 3, reg: gpstoreconst, asm: "SETLS", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract unsigned <= condition from arg1 to arg0+auxint+aux, arg2=mem
|
||||
{name: "SETAmem", argLength: 3, reg: gpstoreconst, asm: "SETHI", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract unsigned > condition from arg1 to arg0+auxint+aux, arg2=mem
|
||||
{name: "SETAEmem", argLength: 3, reg: gpstoreconst, asm: "SETCC", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract unsigned >= condition from arg1 to arg0+auxint+aux, arg2=mem
|
||||
{name: "SETEQstore", argLength: 3, reg: gpstoreconst, asm: "SETEQ", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract == condition from arg1 to arg0+auxint+aux, arg2=mem
|
||||
{name: "SETNEstore", argLength: 3, reg: gpstoreconst, asm: "SETNE", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract != condition from arg1 to arg0+auxint+aux, arg2=mem
|
||||
{name: "SETLstore", argLength: 3, reg: gpstoreconst, asm: "SETLT", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract signed < condition from arg1 to arg0+auxint+aux, arg2=mem
|
||||
{name: "SETLEstore", argLength: 3, reg: gpstoreconst, asm: "SETLE", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract signed <= condition from arg1 to arg0+auxint+aux, arg2=mem
|
||||
{name: "SETGstore", argLength: 3, reg: gpstoreconst, asm: "SETGT", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract signed > condition from arg1 to arg0+auxint+aux, arg2=mem
|
||||
{name: "SETGEstore", argLength: 3, reg: gpstoreconst, asm: "SETGE", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract signed >= condition from arg1 to arg0+auxint+aux, arg2=mem
|
||||
{name: "SETBstore", argLength: 3, reg: gpstoreconst, asm: "SETCS", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract unsigned < condition from arg1 to arg0+auxint+aux, arg2=mem
|
||||
{name: "SETBEstore", argLength: 3, reg: gpstoreconst, asm: "SETLS", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract unsigned <= condition from arg1 to arg0+auxint+aux, arg2=mem
|
||||
{name: "SETAstore", argLength: 3, reg: gpstoreconst, asm: "SETHI", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract unsigned > condition from arg1 to arg0+auxint+aux, arg2=mem
|
||||
{name: "SETAEstore", argLength: 3, reg: gpstoreconst, asm: "SETCC", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // extract unsigned >= condition from arg1 to arg0+auxint+aux, arg2=mem
|
||||
// Need different opcodes for floating point conditions because
|
||||
// any comparison involving a NaN is always FALSE and thus
|
||||
// the patterns for inverting conditions cannot be used.
|
||||
|
@ -256,12 +256,12 @@ const (
|
||||
Op386MOVSSstoreidx4
|
||||
Op386MOVSDstoreidx1
|
||||
Op386MOVSDstoreidx8
|
||||
Op386ADDSSmem
|
||||
Op386ADDSDmem
|
||||
Op386SUBSSmem
|
||||
Op386SUBSDmem
|
||||
Op386MULSSmem
|
||||
Op386MULSDmem
|
||||
Op386ADDSSload
|
||||
Op386ADDSDload
|
||||
Op386SUBSSload
|
||||
Op386SUBSDload
|
||||
Op386MULSSload
|
||||
Op386MULSDload
|
||||
Op386ADDL
|
||||
Op386ADDLconst
|
||||
Op386ADDLcarry
|
||||
@ -325,11 +325,11 @@ const (
|
||||
Op386ROLLconst
|
||||
Op386ROLWconst
|
||||
Op386ROLBconst
|
||||
Op386ADDLmem
|
||||
Op386SUBLmem
|
||||
Op386ANDLmem
|
||||
Op386ORLmem
|
||||
Op386XORLmem
|
||||
Op386ADDLload
|
||||
Op386SUBLload
|
||||
Op386ANDLload
|
||||
Op386ORLload
|
||||
Op386XORLload
|
||||
Op386NEGL
|
||||
Op386NOTL
|
||||
Op386BSFL
|
||||
@ -450,18 +450,18 @@ const (
|
||||
OpAMD64MOVSSstoreidx4
|
||||
OpAMD64MOVSDstoreidx1
|
||||
OpAMD64MOVSDstoreidx8
|
||||
OpAMD64ADDSSmem
|
||||
OpAMD64ADDSDmem
|
||||
OpAMD64SUBSSmem
|
||||
OpAMD64SUBSDmem
|
||||
OpAMD64MULSSmem
|
||||
OpAMD64MULSDmem
|
||||
OpAMD64ADDSSload
|
||||
OpAMD64ADDSDload
|
||||
OpAMD64SUBSSload
|
||||
OpAMD64SUBSDload
|
||||
OpAMD64MULSSload
|
||||
OpAMD64MULSDload
|
||||
OpAMD64ADDQ
|
||||
OpAMD64ADDL
|
||||
OpAMD64ADDQconst
|
||||
OpAMD64ADDLconst
|
||||
OpAMD64ADDQconstmem
|
||||
OpAMD64ADDLconstmem
|
||||
OpAMD64ADDQconstmodify
|
||||
OpAMD64ADDLconstmodify
|
||||
OpAMD64SUBQ
|
||||
OpAMD64SUBL
|
||||
OpAMD64SUBQconst
|
||||
@ -503,14 +503,14 @@ const (
|
||||
OpAMD64CMPLconst
|
||||
OpAMD64CMPWconst
|
||||
OpAMD64CMPBconst
|
||||
OpAMD64CMPQmem
|
||||
OpAMD64CMPLmem
|
||||
OpAMD64CMPWmem
|
||||
OpAMD64CMPBmem
|
||||
OpAMD64CMPQconstmem
|
||||
OpAMD64CMPLconstmem
|
||||
OpAMD64CMPWconstmem
|
||||
OpAMD64CMPBconstmem
|
||||
OpAMD64CMPQload
|
||||
OpAMD64CMPLload
|
||||
OpAMD64CMPWload
|
||||
OpAMD64CMPBload
|
||||
OpAMD64CMPQconstload
|
||||
OpAMD64CMPLconstload
|
||||
OpAMD64CMPWconstload
|
||||
OpAMD64CMPBconstload
|
||||
OpAMD64UCOMISS
|
||||
OpAMD64UCOMISD
|
||||
OpAMD64BTL
|
||||
@ -569,16 +569,16 @@ const (
|
||||
OpAMD64ROLLconst
|
||||
OpAMD64ROLWconst
|
||||
OpAMD64ROLBconst
|
||||
OpAMD64ADDLmem
|
||||
OpAMD64ADDQmem
|
||||
OpAMD64SUBQmem
|
||||
OpAMD64SUBLmem
|
||||
OpAMD64ANDLmem
|
||||
OpAMD64ANDQmem
|
||||
OpAMD64ORQmem
|
||||
OpAMD64ORLmem
|
||||
OpAMD64XORQmem
|
||||
OpAMD64XORLmem
|
||||
OpAMD64ADDLload
|
||||
OpAMD64ADDQload
|
||||
OpAMD64SUBQload
|
||||
OpAMD64SUBLload
|
||||
OpAMD64ANDLload
|
||||
OpAMD64ANDQload
|
||||
OpAMD64ORQload
|
||||
OpAMD64ORLload
|
||||
OpAMD64XORQload
|
||||
OpAMD64XORLload
|
||||
OpAMD64NEGQ
|
||||
OpAMD64NEGL
|
||||
OpAMD64NOTQ
|
||||
@ -647,16 +647,16 @@ const (
|
||||
OpAMD64SETBE
|
||||
OpAMD64SETA
|
||||
OpAMD64SETAE
|
||||
OpAMD64SETEQmem
|
||||
OpAMD64SETNEmem
|
||||
OpAMD64SETLmem
|
||||
OpAMD64SETLEmem
|
||||
OpAMD64SETGmem
|
||||
OpAMD64SETGEmem
|
||||
OpAMD64SETBmem
|
||||
OpAMD64SETBEmem
|
||||
OpAMD64SETAmem
|
||||
OpAMD64SETAEmem
|
||||
OpAMD64SETEQstore
|
||||
OpAMD64SETNEstore
|
||||
OpAMD64SETLstore
|
||||
OpAMD64SETLEstore
|
||||
OpAMD64SETGstore
|
||||
OpAMD64SETGEstore
|
||||
OpAMD64SETBstore
|
||||
OpAMD64SETBEstore
|
||||
OpAMD64SETAstore
|
||||
OpAMD64SETAEstore
|
||||
OpAMD64SETEQF
|
||||
OpAMD64SETNEF
|
||||
OpAMD64SETORD
|
||||
@ -2626,7 +2626,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ADDSSmem",
|
||||
name: "ADDSSload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -2644,7 +2644,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ADDSDmem",
|
||||
name: "ADDSDload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -2662,7 +2662,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "SUBSSmem",
|
||||
name: "SUBSSload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -2680,7 +2680,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "SUBSDmem",
|
||||
name: "SUBSDload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -2698,7 +2698,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MULSSmem",
|
||||
name: "MULSSload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -2716,7 +2716,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MULSDmem",
|
||||
name: "MULSDload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -3684,7 +3684,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ADDLmem",
|
||||
name: "ADDLload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -3703,7 +3703,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "SUBLmem",
|
||||
name: "SUBLload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -3722,7 +3722,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ANDLmem",
|
||||
name: "ANDLload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -3741,7 +3741,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ORLmem",
|
||||
name: "ORLload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -3760,7 +3760,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "XORLmem",
|
||||
name: "XORLload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -5333,7 +5333,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ADDSSmem",
|
||||
name: "ADDSSload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -5351,7 +5351,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ADDSDmem",
|
||||
name: "ADDSDload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -5369,7 +5369,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "SUBSSmem",
|
||||
name: "SUBSSload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -5387,7 +5387,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "SUBSDmem",
|
||||
name: "SUBSDload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -5405,7 +5405,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MULSSmem",
|
||||
name: "MULSSload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -5423,7 +5423,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MULSDmem",
|
||||
name: "MULSDload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -5503,12 +5503,12 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ADDQconstmem",
|
||||
name: "ADDQconstmodify",
|
||||
auxType: auxSymValAndOff,
|
||||
argLen: 2,
|
||||
clobberFlags: true,
|
||||
faultOnNilArg0: true,
|
||||
symEffect: SymWrite,
|
||||
symEffect: SymRead | SymWrite,
|
||||
asm: x86.AADDQ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
@ -5517,12 +5517,12 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ADDLconstmem",
|
||||
name: "ADDLconstmodify",
|
||||
auxType: auxSymValAndOff,
|
||||
argLen: 2,
|
||||
clobberFlags: true,
|
||||
faultOnNilArg0: true,
|
||||
symEffect: SymWrite,
|
||||
symEffect: SymRead | SymWrite,
|
||||
asm: x86.AADDL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
@ -6159,7 +6159,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CMPQmem",
|
||||
name: "CMPQload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
faultOnNilArg0: true,
|
||||
@ -6173,7 +6173,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CMPLmem",
|
||||
name: "CMPLload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
faultOnNilArg0: true,
|
||||
@ -6187,7 +6187,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CMPWmem",
|
||||
name: "CMPWload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
faultOnNilArg0: true,
|
||||
@ -6201,7 +6201,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CMPBmem",
|
||||
name: "CMPBload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
faultOnNilArg0: true,
|
||||
@ -6215,7 +6215,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CMPQconstmem",
|
||||
name: "CMPQconstload",
|
||||
auxType: auxSymValAndOff,
|
||||
argLen: 2,
|
||||
faultOnNilArg0: true,
|
||||
@ -6228,7 +6228,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CMPLconstmem",
|
||||
name: "CMPLconstload",
|
||||
auxType: auxSymValAndOff,
|
||||
argLen: 2,
|
||||
faultOnNilArg0: true,
|
||||
@ -6241,7 +6241,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CMPWconstmem",
|
||||
name: "CMPWconstload",
|
||||
auxType: auxSymValAndOff,
|
||||
argLen: 2,
|
||||
faultOnNilArg0: true,
|
||||
@ -6254,7 +6254,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "CMPBconstmem",
|
||||
name: "CMPBconstload",
|
||||
auxType: auxSymValAndOff,
|
||||
argLen: 2,
|
||||
faultOnNilArg0: true,
|
||||
@ -7129,7 +7129,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ADDLmem",
|
||||
name: "ADDLload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -7148,7 +7148,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ADDQmem",
|
||||
name: "ADDQload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -7167,7 +7167,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "SUBQmem",
|
||||
name: "SUBQload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -7186,7 +7186,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "SUBLmem",
|
||||
name: "SUBLload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -7205,7 +7205,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ANDLmem",
|
||||
name: "ANDLload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -7224,7 +7224,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ANDQmem",
|
||||
name: "ANDQload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -7243,7 +7243,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ORQmem",
|
||||
name: "ORQload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -7262,7 +7262,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "ORLmem",
|
||||
name: "ORLload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -7281,7 +7281,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "XORQmem",
|
||||
name: "XORQload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -7300,7 +7300,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "XORLmem",
|
||||
name: "XORLload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
resultInArg0: true,
|
||||
@ -8269,7 +8269,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "SETEQmem",
|
||||
name: "SETEQstore",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
faultOnNilArg0: true,
|
||||
@ -8282,7 +8282,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "SETNEmem",
|
||||
name: "SETNEstore",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
faultOnNilArg0: true,
|
||||
@ -8295,7 +8295,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "SETLmem",
|
||||
name: "SETLstore",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
faultOnNilArg0: true,
|
||||
@ -8308,7 +8308,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "SETLEmem",
|
||||
name: "SETLEstore",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
faultOnNilArg0: true,
|
||||
@ -8321,7 +8321,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "SETGmem",
|
||||
name: "SETGstore",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
faultOnNilArg0: true,
|
||||
@ -8334,7 +8334,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "SETGEmem",
|
||||
name: "SETGEstore",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
faultOnNilArg0: true,
|
||||
@ -8347,7 +8347,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "SETBmem",
|
||||
name: "SETBstore",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
faultOnNilArg0: true,
|
||||
@ -8360,7 +8360,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "SETBEmem",
|
||||
name: "SETBEstore",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
faultOnNilArg0: true,
|
||||
@ -8373,7 +8373,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "SETAmem",
|
||||
name: "SETAstore",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
faultOnNilArg0: true,
|
||||
@ -8386,7 +8386,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "SETAEmem",
|
||||
name: "SETAEstore",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
faultOnNilArg0: true,
|
||||
|
@ -848,8 +848,8 @@ func zeroUpper32Bits(x *Value, depth int) bool {
|
||||
switch x.Op {
|
||||
case OpAMD64MOVLconst, OpAMD64MOVLload, OpAMD64MOVLQZX, OpAMD64MOVLloadidx1,
|
||||
OpAMD64MOVWload, OpAMD64MOVWloadidx1, OpAMD64MOVBload, OpAMD64MOVBloadidx1,
|
||||
OpAMD64MOVLloadidx4, OpAMD64ADDLmem, OpAMD64SUBLmem, OpAMD64ANDLmem,
|
||||
OpAMD64ORLmem, OpAMD64XORLmem, OpAMD64CVTTSD2SL,
|
||||
OpAMD64MOVLloadidx4, OpAMD64ADDLload, OpAMD64SUBLload, OpAMD64ANDLload,
|
||||
OpAMD64ORLload, OpAMD64XORLload, OpAMD64CVTTSD2SL,
|
||||
OpAMD64ADDL, OpAMD64ADDLconst, OpAMD64SUBL, OpAMD64SUBLconst,
|
||||
OpAMD64ANDL, OpAMD64ANDLconst, OpAMD64ORL, OpAMD64ORLconst,
|
||||
OpAMD64XORL, OpAMD64XORLconst, OpAMD64NEGL, OpAMD64NOTL:
|
||||
|
@ -23,24 +23,24 @@ func rewriteValue386(v *Value) bool {
|
||||
return rewriteValue386_Op386ADDLcarry_0(v)
|
||||
case Op386ADDLconst:
|
||||
return rewriteValue386_Op386ADDLconst_0(v)
|
||||
case Op386ADDLmem:
|
||||
return rewriteValue386_Op386ADDLmem_0(v)
|
||||
case Op386ADDLload:
|
||||
return rewriteValue386_Op386ADDLload_0(v)
|
||||
case Op386ADDLmodify:
|
||||
return rewriteValue386_Op386ADDLmodify_0(v)
|
||||
case Op386ADDSD:
|
||||
return rewriteValue386_Op386ADDSD_0(v)
|
||||
case Op386ADDSDmem:
|
||||
return rewriteValue386_Op386ADDSDmem_0(v)
|
||||
case Op386ADDSDload:
|
||||
return rewriteValue386_Op386ADDSDload_0(v)
|
||||
case Op386ADDSS:
|
||||
return rewriteValue386_Op386ADDSS_0(v)
|
||||
case Op386ADDSSmem:
|
||||
return rewriteValue386_Op386ADDSSmem_0(v)
|
||||
case Op386ADDSSload:
|
||||
return rewriteValue386_Op386ADDSSload_0(v)
|
||||
case Op386ANDL:
|
||||
return rewriteValue386_Op386ANDL_0(v)
|
||||
case Op386ANDLconst:
|
||||
return rewriteValue386_Op386ANDLconst_0(v)
|
||||
case Op386ANDLmem:
|
||||
return rewriteValue386_Op386ANDLmem_0(v)
|
||||
case Op386ANDLload:
|
||||
return rewriteValue386_Op386ANDLload_0(v)
|
||||
case Op386ANDLmodify:
|
||||
return rewriteValue386_Op386ANDLmodify_0(v)
|
||||
case Op386CMPB:
|
||||
@ -159,12 +159,12 @@ func rewriteValue386(v *Value) bool {
|
||||
return rewriteValue386_Op386MULLconst_0(v) || rewriteValue386_Op386MULLconst_10(v) || rewriteValue386_Op386MULLconst_20(v) || rewriteValue386_Op386MULLconst_30(v)
|
||||
case Op386MULSD:
|
||||
return rewriteValue386_Op386MULSD_0(v)
|
||||
case Op386MULSDmem:
|
||||
return rewriteValue386_Op386MULSDmem_0(v)
|
||||
case Op386MULSDload:
|
||||
return rewriteValue386_Op386MULSDload_0(v)
|
||||
case Op386MULSS:
|
||||
return rewriteValue386_Op386MULSS_0(v)
|
||||
case Op386MULSSmem:
|
||||
return rewriteValue386_Op386MULSSmem_0(v)
|
||||
case Op386MULSSload:
|
||||
return rewriteValue386_Op386MULSSload_0(v)
|
||||
case Op386NEGL:
|
||||
return rewriteValue386_Op386NEGL_0(v)
|
||||
case Op386NOTL:
|
||||
@ -173,8 +173,8 @@ func rewriteValue386(v *Value) bool {
|
||||
return rewriteValue386_Op386ORL_0(v) || rewriteValue386_Op386ORL_10(v) || rewriteValue386_Op386ORL_20(v) || rewriteValue386_Op386ORL_30(v) || rewriteValue386_Op386ORL_40(v) || rewriteValue386_Op386ORL_50(v)
|
||||
case Op386ORLconst:
|
||||
return rewriteValue386_Op386ORLconst_0(v)
|
||||
case Op386ORLmem:
|
||||
return rewriteValue386_Op386ORLmem_0(v)
|
||||
case Op386ORLload:
|
||||
return rewriteValue386_Op386ORLload_0(v)
|
||||
case Op386ORLmodify:
|
||||
return rewriteValue386_Op386ORLmodify_0(v)
|
||||
case Op386ROLBconst:
|
||||
@ -241,24 +241,24 @@ func rewriteValue386(v *Value) bool {
|
||||
return rewriteValue386_Op386SUBLcarry_0(v)
|
||||
case Op386SUBLconst:
|
||||
return rewriteValue386_Op386SUBLconst_0(v)
|
||||
case Op386SUBLmem:
|
||||
return rewriteValue386_Op386SUBLmem_0(v)
|
||||
case Op386SUBLload:
|
||||
return rewriteValue386_Op386SUBLload_0(v)
|
||||
case Op386SUBLmodify:
|
||||
return rewriteValue386_Op386SUBLmodify_0(v)
|
||||
case Op386SUBSD:
|
||||
return rewriteValue386_Op386SUBSD_0(v)
|
||||
case Op386SUBSDmem:
|
||||
return rewriteValue386_Op386SUBSDmem_0(v)
|
||||
case Op386SUBSDload:
|
||||
return rewriteValue386_Op386SUBSDload_0(v)
|
||||
case Op386SUBSS:
|
||||
return rewriteValue386_Op386SUBSS_0(v)
|
||||
case Op386SUBSSmem:
|
||||
return rewriteValue386_Op386SUBSSmem_0(v)
|
||||
case Op386SUBSSload:
|
||||
return rewriteValue386_Op386SUBSSload_0(v)
|
||||
case Op386XORL:
|
||||
return rewriteValue386_Op386XORL_0(v) || rewriteValue386_Op386XORL_10(v)
|
||||
case Op386XORLconst:
|
||||
return rewriteValue386_Op386XORLconst_0(v)
|
||||
case Op386XORLmem:
|
||||
return rewriteValue386_Op386XORLmem_0(v)
|
||||
case Op386XORLload:
|
||||
return rewriteValue386_Op386XORLload_0(v)
|
||||
case Op386XORLmodify:
|
||||
return rewriteValue386_Op386XORLmodify_0(v)
|
||||
case OpAdd16:
|
||||
@ -1238,7 +1238,7 @@ func rewriteValue386_Op386ADDL_20(v *Value) bool {
|
||||
}
|
||||
// match: (ADDL x l:(MOVLload [off] {sym} ptr mem))
|
||||
// cond: canMergeLoad(v, l, x) && clobber(l)
|
||||
// result: (ADDLmem x [off] {sym} ptr mem)
|
||||
// result: (ADDLload x [off] {sym} ptr mem)
|
||||
for {
|
||||
_ = v.Args[1]
|
||||
x := v.Args[0]
|
||||
@ -1254,7 +1254,7 @@ func rewriteValue386_Op386ADDL_20(v *Value) bool {
|
||||
if !(canMergeLoad(v, l, x) && clobber(l)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386ADDLmem)
|
||||
v.reset(Op386ADDLload)
|
||||
v.AuxInt = off
|
||||
v.Aux = sym
|
||||
v.AddArg(x)
|
||||
@ -1264,7 +1264,7 @@ func rewriteValue386_Op386ADDL_20(v *Value) bool {
|
||||
}
|
||||
// match: (ADDL l:(MOVLload [off] {sym} ptr mem) x)
|
||||
// cond: canMergeLoad(v, l, x) && clobber(l)
|
||||
// result: (ADDLmem x [off] {sym} ptr mem)
|
||||
// result: (ADDLload x [off] {sym} ptr mem)
|
||||
for {
|
||||
_ = v.Args[1]
|
||||
l := v.Args[0]
|
||||
@ -1280,7 +1280,7 @@ func rewriteValue386_Op386ADDL_20(v *Value) bool {
|
||||
if !(canMergeLoad(v, l, x) && clobber(l)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386ADDLmem)
|
||||
v.reset(Op386ADDLload)
|
||||
v.AuxInt = off
|
||||
v.Aux = sym
|
||||
v.AddArg(x)
|
||||
@ -1539,14 +1539,14 @@ func rewriteValue386_Op386ADDLconst_0(v *Value) bool {
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValue386_Op386ADDLmem_0(v *Value) bool {
|
||||
func rewriteValue386_Op386ADDLload_0(v *Value) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
config := b.Func.Config
|
||||
_ = config
|
||||
// match: (ADDLmem [off1] {sym} val (ADDLconst [off2] base) mem)
|
||||
// match: (ADDLload [off1] {sym} val (ADDLconst [off2] base) mem)
|
||||
// cond: is32Bit(off1+off2)
|
||||
// result: (ADDLmem [off1+off2] {sym} val base mem)
|
||||
// result: (ADDLload [off1+off2] {sym} val base mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym := v.Aux
|
||||
@ -1562,7 +1562,7 @@ func rewriteValue386_Op386ADDLmem_0(v *Value) bool {
|
||||
if !(is32Bit(off1 + off2)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386ADDLmem)
|
||||
v.reset(Op386ADDLload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = sym
|
||||
v.AddArg(val)
|
||||
@ -1570,9 +1570,9 @@ func rewriteValue386_Op386ADDLmem_0(v *Value) bool {
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
// match: (ADDLmem [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
|
||||
// match: (ADDLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
|
||||
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
|
||||
// result: (ADDLmem [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
// result: (ADDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym1 := v.Aux
|
||||
@ -1589,7 +1589,7 @@ func rewriteValue386_Op386ADDLmem_0(v *Value) bool {
|
||||
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386ADDLmem)
|
||||
v.reset(Op386ADDLload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = mergeSym(sym1, sym2)
|
||||
v.AddArg(val)
|
||||
@ -1666,7 +1666,7 @@ func rewriteValue386_Op386ADDSD_0(v *Value) bool {
|
||||
_ = config
|
||||
// match: (ADDSD x l:(MOVSDload [off] {sym} ptr mem))
|
||||
// cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l)
|
||||
// result: (ADDSDmem x [off] {sym} ptr mem)
|
||||
// result: (ADDSDload x [off] {sym} ptr mem)
|
||||
for {
|
||||
_ = v.Args[1]
|
||||
x := v.Args[0]
|
||||
@ -1682,7 +1682,7 @@ func rewriteValue386_Op386ADDSD_0(v *Value) bool {
|
||||
if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386ADDSDmem)
|
||||
v.reset(Op386ADDSDload)
|
||||
v.AuxInt = off
|
||||
v.Aux = sym
|
||||
v.AddArg(x)
|
||||
@ -1692,7 +1692,7 @@ func rewriteValue386_Op386ADDSD_0(v *Value) bool {
|
||||
}
|
||||
// match: (ADDSD l:(MOVSDload [off] {sym} ptr mem) x)
|
||||
// cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l)
|
||||
// result: (ADDSDmem x [off] {sym} ptr mem)
|
||||
// result: (ADDSDload x [off] {sym} ptr mem)
|
||||
for {
|
||||
_ = v.Args[1]
|
||||
l := v.Args[0]
|
||||
@ -1708,7 +1708,7 @@ func rewriteValue386_Op386ADDSD_0(v *Value) bool {
|
||||
if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386ADDSDmem)
|
||||
v.reset(Op386ADDSDload)
|
||||
v.AuxInt = off
|
||||
v.Aux = sym
|
||||
v.AddArg(x)
|
||||
@ -1718,14 +1718,14 @@ func rewriteValue386_Op386ADDSD_0(v *Value) bool {
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValue386_Op386ADDSDmem_0(v *Value) bool {
|
||||
func rewriteValue386_Op386ADDSDload_0(v *Value) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
config := b.Func.Config
|
||||
_ = config
|
||||
// match: (ADDSDmem [off1] {sym} val (ADDLconst [off2] base) mem)
|
||||
// match: (ADDSDload [off1] {sym} val (ADDLconst [off2] base) mem)
|
||||
// cond: is32Bit(off1+off2)
|
||||
// result: (ADDSDmem [off1+off2] {sym} val base mem)
|
||||
// result: (ADDSDload [off1+off2] {sym} val base mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym := v.Aux
|
||||
@ -1741,7 +1741,7 @@ func rewriteValue386_Op386ADDSDmem_0(v *Value) bool {
|
||||
if !(is32Bit(off1 + off2)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386ADDSDmem)
|
||||
v.reset(Op386ADDSDload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = sym
|
||||
v.AddArg(val)
|
||||
@ -1749,9 +1749,9 @@ func rewriteValue386_Op386ADDSDmem_0(v *Value) bool {
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
// match: (ADDSDmem [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
|
||||
// match: (ADDSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
|
||||
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
|
||||
// result: (ADDSDmem [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
// result: (ADDSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym1 := v.Aux
|
||||
@ -1768,7 +1768,7 @@ func rewriteValue386_Op386ADDSDmem_0(v *Value) bool {
|
||||
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386ADDSDmem)
|
||||
v.reset(Op386ADDSDload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = mergeSym(sym1, sym2)
|
||||
v.AddArg(val)
|
||||
@ -1785,7 +1785,7 @@ func rewriteValue386_Op386ADDSS_0(v *Value) bool {
|
||||
_ = config
|
||||
// match: (ADDSS x l:(MOVSSload [off] {sym} ptr mem))
|
||||
// cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l)
|
||||
// result: (ADDSSmem x [off] {sym} ptr mem)
|
||||
// result: (ADDSSload x [off] {sym} ptr mem)
|
||||
for {
|
||||
_ = v.Args[1]
|
||||
x := v.Args[0]
|
||||
@ -1801,7 +1801,7 @@ func rewriteValue386_Op386ADDSS_0(v *Value) bool {
|
||||
if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386ADDSSmem)
|
||||
v.reset(Op386ADDSSload)
|
||||
v.AuxInt = off
|
||||
v.Aux = sym
|
||||
v.AddArg(x)
|
||||
@ -1811,7 +1811,7 @@ func rewriteValue386_Op386ADDSS_0(v *Value) bool {
|
||||
}
|
||||
// match: (ADDSS l:(MOVSSload [off] {sym} ptr mem) x)
|
||||
// cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l)
|
||||
// result: (ADDSSmem x [off] {sym} ptr mem)
|
||||
// result: (ADDSSload x [off] {sym} ptr mem)
|
||||
for {
|
||||
_ = v.Args[1]
|
||||
l := v.Args[0]
|
||||
@ -1827,7 +1827,7 @@ func rewriteValue386_Op386ADDSS_0(v *Value) bool {
|
||||
if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386ADDSSmem)
|
||||
v.reset(Op386ADDSSload)
|
||||
v.AuxInt = off
|
||||
v.Aux = sym
|
||||
v.AddArg(x)
|
||||
@ -1837,14 +1837,14 @@ func rewriteValue386_Op386ADDSS_0(v *Value) bool {
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValue386_Op386ADDSSmem_0(v *Value) bool {
|
||||
func rewriteValue386_Op386ADDSSload_0(v *Value) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
config := b.Func.Config
|
||||
_ = config
|
||||
// match: (ADDSSmem [off1] {sym} val (ADDLconst [off2] base) mem)
|
||||
// match: (ADDSSload [off1] {sym} val (ADDLconst [off2] base) mem)
|
||||
// cond: is32Bit(off1+off2)
|
||||
// result: (ADDSSmem [off1+off2] {sym} val base mem)
|
||||
// result: (ADDSSload [off1+off2] {sym} val base mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym := v.Aux
|
||||
@ -1860,7 +1860,7 @@ func rewriteValue386_Op386ADDSSmem_0(v *Value) bool {
|
||||
if !(is32Bit(off1 + off2)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386ADDSSmem)
|
||||
v.reset(Op386ADDSSload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = sym
|
||||
v.AddArg(val)
|
||||
@ -1868,9 +1868,9 @@ func rewriteValue386_Op386ADDSSmem_0(v *Value) bool {
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
// match: (ADDSSmem [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
|
||||
// match: (ADDSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
|
||||
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
|
||||
// result: (ADDSSmem [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
// result: (ADDSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym1 := v.Aux
|
||||
@ -1887,7 +1887,7 @@ func rewriteValue386_Op386ADDSSmem_0(v *Value) bool {
|
||||
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386ADDSSmem)
|
||||
v.reset(Op386ADDSSload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = mergeSym(sym1, sym2)
|
||||
v.AddArg(val)
|
||||
@ -1932,7 +1932,7 @@ func rewriteValue386_Op386ANDL_0(v *Value) bool {
|
||||
}
|
||||
// match: (ANDL x l:(MOVLload [off] {sym} ptr mem))
|
||||
// cond: canMergeLoad(v, l, x) && clobber(l)
|
||||
// result: (ANDLmem x [off] {sym} ptr mem)
|
||||
// result: (ANDLload x [off] {sym} ptr mem)
|
||||
for {
|
||||
_ = v.Args[1]
|
||||
x := v.Args[0]
|
||||
@ -1948,7 +1948,7 @@ func rewriteValue386_Op386ANDL_0(v *Value) bool {
|
||||
if !(canMergeLoad(v, l, x) && clobber(l)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386ANDLmem)
|
||||
v.reset(Op386ANDLload)
|
||||
v.AuxInt = off
|
||||
v.Aux = sym
|
||||
v.AddArg(x)
|
||||
@ -1958,7 +1958,7 @@ func rewriteValue386_Op386ANDL_0(v *Value) bool {
|
||||
}
|
||||
// match: (ANDL l:(MOVLload [off] {sym} ptr mem) x)
|
||||
// cond: canMergeLoad(v, l, x) && clobber(l)
|
||||
// result: (ANDLmem x [off] {sym} ptr mem)
|
||||
// result: (ANDLload x [off] {sym} ptr mem)
|
||||
for {
|
||||
_ = v.Args[1]
|
||||
l := v.Args[0]
|
||||
@ -1974,7 +1974,7 @@ func rewriteValue386_Op386ANDL_0(v *Value) bool {
|
||||
if !(canMergeLoad(v, l, x) && clobber(l)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386ANDLmem)
|
||||
v.reset(Op386ANDLload)
|
||||
v.AuxInt = off
|
||||
v.Aux = sym
|
||||
v.AddArg(x)
|
||||
@ -2057,14 +2057,14 @@ func rewriteValue386_Op386ANDLconst_0(v *Value) bool {
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValue386_Op386ANDLmem_0(v *Value) bool {
|
||||
func rewriteValue386_Op386ANDLload_0(v *Value) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
config := b.Func.Config
|
||||
_ = config
|
||||
// match: (ANDLmem [off1] {sym} val (ADDLconst [off2] base) mem)
|
||||
// match: (ANDLload [off1] {sym} val (ADDLconst [off2] base) mem)
|
||||
// cond: is32Bit(off1+off2)
|
||||
// result: (ANDLmem [off1+off2] {sym} val base mem)
|
||||
// result: (ANDLload [off1+off2] {sym} val base mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym := v.Aux
|
||||
@ -2080,7 +2080,7 @@ func rewriteValue386_Op386ANDLmem_0(v *Value) bool {
|
||||
if !(is32Bit(off1 + off2)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386ANDLmem)
|
||||
v.reset(Op386ANDLload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = sym
|
||||
v.AddArg(val)
|
||||
@ -2088,9 +2088,9 @@ func rewriteValue386_Op386ANDLmem_0(v *Value) bool {
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
// match: (ANDLmem [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
|
||||
// match: (ANDLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
|
||||
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
|
||||
// result: (ANDLmem [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
// result: (ANDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym1 := v.Aux
|
||||
@ -2107,7 +2107,7 @@ func rewriteValue386_Op386ANDLmem_0(v *Value) bool {
|
||||
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386ANDLmem)
|
||||
v.reset(Op386ANDLload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = mergeSym(sym1, sym2)
|
||||
v.AddArg(val)
|
||||
@ -5427,7 +5427,7 @@ func rewriteValue386_Op386MOVLstore_0(v *Value) bool {
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
// match: (MOVLstore {sym} [off] ptr y:(ADDLmem x [off] {sym} ptr mem) mem)
|
||||
// match: (MOVLstore {sym} [off] ptr y:(ADDLload x [off] {sym} ptr mem) mem)
|
||||
// cond: y.Uses==1 && clobber(y)
|
||||
// result: (ADDLmodify [off] {sym} ptr x mem)
|
||||
for {
|
||||
@ -5436,7 +5436,7 @@ func rewriteValue386_Op386MOVLstore_0(v *Value) bool {
|
||||
_ = v.Args[2]
|
||||
ptr := v.Args[0]
|
||||
y := v.Args[1]
|
||||
if y.Op != Op386ADDLmem {
|
||||
if y.Op != Op386ADDLload {
|
||||
break
|
||||
}
|
||||
if y.AuxInt != off {
|
||||
@ -5465,7 +5465,7 @@ func rewriteValue386_Op386MOVLstore_0(v *Value) bool {
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
// match: (MOVLstore {sym} [off] ptr y:(ANDLmem x [off] {sym} ptr mem) mem)
|
||||
// match: (MOVLstore {sym} [off] ptr y:(ANDLload x [off] {sym} ptr mem) mem)
|
||||
// cond: y.Uses==1 && clobber(y)
|
||||
// result: (ANDLmodify [off] {sym} ptr x mem)
|
||||
for {
|
||||
@ -5474,7 +5474,7 @@ func rewriteValue386_Op386MOVLstore_0(v *Value) bool {
|
||||
_ = v.Args[2]
|
||||
ptr := v.Args[0]
|
||||
y := v.Args[1]
|
||||
if y.Op != Op386ANDLmem {
|
||||
if y.Op != Op386ANDLload {
|
||||
break
|
||||
}
|
||||
if y.AuxInt != off {
|
||||
@ -5503,7 +5503,7 @@ func rewriteValue386_Op386MOVLstore_0(v *Value) bool {
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
// match: (MOVLstore {sym} [off] ptr y:(ORLmem x [off] {sym} ptr mem) mem)
|
||||
// match: (MOVLstore {sym} [off] ptr y:(ORLload x [off] {sym} ptr mem) mem)
|
||||
// cond: y.Uses==1 && clobber(y)
|
||||
// result: (ORLmodify [off] {sym} ptr x mem)
|
||||
for {
|
||||
@ -5512,7 +5512,7 @@ func rewriteValue386_Op386MOVLstore_0(v *Value) bool {
|
||||
_ = v.Args[2]
|
||||
ptr := v.Args[0]
|
||||
y := v.Args[1]
|
||||
if y.Op != Op386ORLmem {
|
||||
if y.Op != Op386ORLload {
|
||||
break
|
||||
}
|
||||
if y.AuxInt != off {
|
||||
@ -5541,7 +5541,7 @@ func rewriteValue386_Op386MOVLstore_0(v *Value) bool {
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
// match: (MOVLstore {sym} [off] ptr y:(XORLmem x [off] {sym} ptr mem) mem)
|
||||
// match: (MOVLstore {sym} [off] ptr y:(XORLload x [off] {sym} ptr mem) mem)
|
||||
// cond: y.Uses==1 && clobber(y)
|
||||
// result: (XORLmodify [off] {sym} ptr x mem)
|
||||
for {
|
||||
@ -5550,7 +5550,7 @@ func rewriteValue386_Op386MOVLstore_0(v *Value) bool {
|
||||
_ = v.Args[2]
|
||||
ptr := v.Args[0]
|
||||
y := v.Args[1]
|
||||
if y.Op != Op386XORLmem {
|
||||
if y.Op != Op386XORLload {
|
||||
break
|
||||
}
|
||||
if y.AuxInt != off {
|
||||
@ -9998,7 +9998,7 @@ func rewriteValue386_Op386MULSD_0(v *Value) bool {
|
||||
_ = config
|
||||
// match: (MULSD x l:(MOVSDload [off] {sym} ptr mem))
|
||||
// cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l)
|
||||
// result: (MULSDmem x [off] {sym} ptr mem)
|
||||
// result: (MULSDload x [off] {sym} ptr mem)
|
||||
for {
|
||||
_ = v.Args[1]
|
||||
x := v.Args[0]
|
||||
@ -10014,7 +10014,7 @@ func rewriteValue386_Op386MULSD_0(v *Value) bool {
|
||||
if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386MULSDmem)
|
||||
v.reset(Op386MULSDload)
|
||||
v.AuxInt = off
|
||||
v.Aux = sym
|
||||
v.AddArg(x)
|
||||
@ -10024,7 +10024,7 @@ func rewriteValue386_Op386MULSD_0(v *Value) bool {
|
||||
}
|
||||
// match: (MULSD l:(MOVSDload [off] {sym} ptr mem) x)
|
||||
// cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l)
|
||||
// result: (MULSDmem x [off] {sym} ptr mem)
|
||||
// result: (MULSDload x [off] {sym} ptr mem)
|
||||
for {
|
||||
_ = v.Args[1]
|
||||
l := v.Args[0]
|
||||
@ -10040,7 +10040,7 @@ func rewriteValue386_Op386MULSD_0(v *Value) bool {
|
||||
if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386MULSDmem)
|
||||
v.reset(Op386MULSDload)
|
||||
v.AuxInt = off
|
||||
v.Aux = sym
|
||||
v.AddArg(x)
|
||||
@ -10050,14 +10050,14 @@ func rewriteValue386_Op386MULSD_0(v *Value) bool {
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValue386_Op386MULSDmem_0(v *Value) bool {
|
||||
func rewriteValue386_Op386MULSDload_0(v *Value) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
config := b.Func.Config
|
||||
_ = config
|
||||
// match: (MULSDmem [off1] {sym} val (ADDLconst [off2] base) mem)
|
||||
// match: (MULSDload [off1] {sym} val (ADDLconst [off2] base) mem)
|
||||
// cond: is32Bit(off1+off2)
|
||||
// result: (MULSDmem [off1+off2] {sym} val base mem)
|
||||
// result: (MULSDload [off1+off2] {sym} val base mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym := v.Aux
|
||||
@ -10073,7 +10073,7 @@ func rewriteValue386_Op386MULSDmem_0(v *Value) bool {
|
||||
if !(is32Bit(off1 + off2)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386MULSDmem)
|
||||
v.reset(Op386MULSDload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = sym
|
||||
v.AddArg(val)
|
||||
@ -10081,9 +10081,9 @@ func rewriteValue386_Op386MULSDmem_0(v *Value) bool {
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
// match: (MULSDmem [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
|
||||
// match: (MULSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
|
||||
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
|
||||
// result: (MULSDmem [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
// result: (MULSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym1 := v.Aux
|
||||
@ -10100,7 +10100,7 @@ func rewriteValue386_Op386MULSDmem_0(v *Value) bool {
|
||||
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386MULSDmem)
|
||||
v.reset(Op386MULSDload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = mergeSym(sym1, sym2)
|
||||
v.AddArg(val)
|
||||
@ -10117,7 +10117,7 @@ func rewriteValue386_Op386MULSS_0(v *Value) bool {
|
||||
_ = config
|
||||
// match: (MULSS x l:(MOVSSload [off] {sym} ptr mem))
|
||||
// cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l)
|
||||
// result: (MULSSmem x [off] {sym} ptr mem)
|
||||
// result: (MULSSload x [off] {sym} ptr mem)
|
||||
for {
|
||||
_ = v.Args[1]
|
||||
x := v.Args[0]
|
||||
@ -10133,7 +10133,7 @@ func rewriteValue386_Op386MULSS_0(v *Value) bool {
|
||||
if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386MULSSmem)
|
||||
v.reset(Op386MULSSload)
|
||||
v.AuxInt = off
|
||||
v.Aux = sym
|
||||
v.AddArg(x)
|
||||
@ -10143,7 +10143,7 @@ func rewriteValue386_Op386MULSS_0(v *Value) bool {
|
||||
}
|
||||
// match: (MULSS l:(MOVSSload [off] {sym} ptr mem) x)
|
||||
// cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l)
|
||||
// result: (MULSSmem x [off] {sym} ptr mem)
|
||||
// result: (MULSSload x [off] {sym} ptr mem)
|
||||
for {
|
||||
_ = v.Args[1]
|
||||
l := v.Args[0]
|
||||
@ -10159,7 +10159,7 @@ func rewriteValue386_Op386MULSS_0(v *Value) bool {
|
||||
if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386MULSSmem)
|
||||
v.reset(Op386MULSSload)
|
||||
v.AuxInt = off
|
||||
v.Aux = sym
|
||||
v.AddArg(x)
|
||||
@ -10169,14 +10169,14 @@ func rewriteValue386_Op386MULSS_0(v *Value) bool {
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValue386_Op386MULSSmem_0(v *Value) bool {
|
||||
func rewriteValue386_Op386MULSSload_0(v *Value) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
config := b.Func.Config
|
||||
_ = config
|
||||
// match: (MULSSmem [off1] {sym} val (ADDLconst [off2] base) mem)
|
||||
// match: (MULSSload [off1] {sym} val (ADDLconst [off2] base) mem)
|
||||
// cond: is32Bit(off1+off2)
|
||||
// result: (MULSSmem [off1+off2] {sym} val base mem)
|
||||
// result: (MULSSload [off1+off2] {sym} val base mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym := v.Aux
|
||||
@ -10192,7 +10192,7 @@ func rewriteValue386_Op386MULSSmem_0(v *Value) bool {
|
||||
if !(is32Bit(off1 + off2)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386MULSSmem)
|
||||
v.reset(Op386MULSSload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = sym
|
||||
v.AddArg(val)
|
||||
@ -10200,9 +10200,9 @@ func rewriteValue386_Op386MULSSmem_0(v *Value) bool {
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
// match: (MULSSmem [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
|
||||
// match: (MULSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
|
||||
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
|
||||
// result: (MULSSmem [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
// result: (MULSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym1 := v.Aux
|
||||
@ -10219,7 +10219,7 @@ func rewriteValue386_Op386MULSSmem_0(v *Value) bool {
|
||||
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386MULSSmem)
|
||||
v.reset(Op386MULSSload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = mergeSym(sym1, sym2)
|
||||
v.AddArg(val)
|
||||
@ -10462,7 +10462,7 @@ func rewriteValue386_Op386ORL_0(v *Value) bool {
|
||||
}
|
||||
// match: (ORL x l:(MOVLload [off] {sym} ptr mem))
|
||||
// cond: canMergeLoad(v, l, x) && clobber(l)
|
||||
// result: (ORLmem x [off] {sym} ptr mem)
|
||||
// result: (ORLload x [off] {sym} ptr mem)
|
||||
for {
|
||||
_ = v.Args[1]
|
||||
x := v.Args[0]
|
||||
@ -10478,7 +10478,7 @@ func rewriteValue386_Op386ORL_0(v *Value) bool {
|
||||
if !(canMergeLoad(v, l, x) && clobber(l)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386ORLmem)
|
||||
v.reset(Op386ORLload)
|
||||
v.AuxInt = off
|
||||
v.Aux = sym
|
||||
v.AddArg(x)
|
||||
@ -10488,7 +10488,7 @@ func rewriteValue386_Op386ORL_0(v *Value) bool {
|
||||
}
|
||||
// match: (ORL l:(MOVLload [off] {sym} ptr mem) x)
|
||||
// cond: canMergeLoad(v, l, x) && clobber(l)
|
||||
// result: (ORLmem x [off] {sym} ptr mem)
|
||||
// result: (ORLload x [off] {sym} ptr mem)
|
||||
for {
|
||||
_ = v.Args[1]
|
||||
l := v.Args[0]
|
||||
@ -10504,7 +10504,7 @@ func rewriteValue386_Op386ORL_0(v *Value) bool {
|
||||
if !(canMergeLoad(v, l, x) && clobber(l)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386ORLmem)
|
||||
v.reset(Op386ORLload)
|
||||
v.AuxInt = off
|
||||
v.Aux = sym
|
||||
v.AddArg(x)
|
||||
@ -14120,14 +14120,14 @@ func rewriteValue386_Op386ORLconst_0(v *Value) bool {
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValue386_Op386ORLmem_0(v *Value) bool {
|
||||
func rewriteValue386_Op386ORLload_0(v *Value) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
config := b.Func.Config
|
||||
_ = config
|
||||
// match: (ORLmem [off1] {sym} val (ADDLconst [off2] base) mem)
|
||||
// match: (ORLload [off1] {sym} val (ADDLconst [off2] base) mem)
|
||||
// cond: is32Bit(off1+off2)
|
||||
// result: (ORLmem [off1+off2] {sym} val base mem)
|
||||
// result: (ORLload [off1+off2] {sym} val base mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym := v.Aux
|
||||
@ -14143,7 +14143,7 @@ func rewriteValue386_Op386ORLmem_0(v *Value) bool {
|
||||
if !(is32Bit(off1 + off2)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386ORLmem)
|
||||
v.reset(Op386ORLload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = sym
|
||||
v.AddArg(val)
|
||||
@ -14151,9 +14151,9 @@ func rewriteValue386_Op386ORLmem_0(v *Value) bool {
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
// match: (ORLmem [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
|
||||
// match: (ORLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
|
||||
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
|
||||
// result: (ORLmem [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
// result: (ORLload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym1 := v.Aux
|
||||
@ -14170,7 +14170,7 @@ func rewriteValue386_Op386ORLmem_0(v *Value) bool {
|
||||
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386ORLmem)
|
||||
v.reset(Op386ORLload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = mergeSym(sym1, sym2)
|
||||
v.AddArg(val)
|
||||
@ -15603,7 +15603,7 @@ func rewriteValue386_Op386SUBL_0(v *Value) bool {
|
||||
}
|
||||
// match: (SUBL x l:(MOVLload [off] {sym} ptr mem))
|
||||
// cond: canMergeLoad(v, l, x) && clobber(l)
|
||||
// result: (SUBLmem x [off] {sym} ptr mem)
|
||||
// result: (SUBLload x [off] {sym} ptr mem)
|
||||
for {
|
||||
_ = v.Args[1]
|
||||
x := v.Args[0]
|
||||
@ -15619,7 +15619,7 @@ func rewriteValue386_Op386SUBL_0(v *Value) bool {
|
||||
if !(canMergeLoad(v, l, x) && clobber(l)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386SUBLmem)
|
||||
v.reset(Op386SUBLload)
|
||||
v.AuxInt = off
|
||||
v.Aux = sym
|
||||
v.AddArg(x)
|
||||
@ -15688,14 +15688,14 @@ func rewriteValue386_Op386SUBLconst_0(v *Value) bool {
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValue386_Op386SUBLmem_0(v *Value) bool {
|
||||
func rewriteValue386_Op386SUBLload_0(v *Value) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
config := b.Func.Config
|
||||
_ = config
|
||||
// match: (SUBLmem [off1] {sym} val (ADDLconst [off2] base) mem)
|
||||
// match: (SUBLload [off1] {sym} val (ADDLconst [off2] base) mem)
|
||||
// cond: is32Bit(off1+off2)
|
||||
// result: (SUBLmem [off1+off2] {sym} val base mem)
|
||||
// result: (SUBLload [off1+off2] {sym} val base mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym := v.Aux
|
||||
@ -15711,7 +15711,7 @@ func rewriteValue386_Op386SUBLmem_0(v *Value) bool {
|
||||
if !(is32Bit(off1 + off2)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386SUBLmem)
|
||||
v.reset(Op386SUBLload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = sym
|
||||
v.AddArg(val)
|
||||
@ -15719,9 +15719,9 @@ func rewriteValue386_Op386SUBLmem_0(v *Value) bool {
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
// match: (SUBLmem [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
|
||||
// match: (SUBLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
|
||||
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
|
||||
// result: (SUBLmem [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
// result: (SUBLload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym1 := v.Aux
|
||||
@ -15738,7 +15738,7 @@ func rewriteValue386_Op386SUBLmem_0(v *Value) bool {
|
||||
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386SUBLmem)
|
||||
v.reset(Op386SUBLload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = mergeSym(sym1, sym2)
|
||||
v.AddArg(val)
|
||||
@ -15815,7 +15815,7 @@ func rewriteValue386_Op386SUBSD_0(v *Value) bool {
|
||||
_ = config
|
||||
// match: (SUBSD x l:(MOVSDload [off] {sym} ptr mem))
|
||||
// cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l)
|
||||
// result: (SUBSDmem x [off] {sym} ptr mem)
|
||||
// result: (SUBSDload x [off] {sym} ptr mem)
|
||||
for {
|
||||
_ = v.Args[1]
|
||||
x := v.Args[0]
|
||||
@ -15831,7 +15831,7 @@ func rewriteValue386_Op386SUBSD_0(v *Value) bool {
|
||||
if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386SUBSDmem)
|
||||
v.reset(Op386SUBSDload)
|
||||
v.AuxInt = off
|
||||
v.Aux = sym
|
||||
v.AddArg(x)
|
||||
@ -15841,14 +15841,14 @@ func rewriteValue386_Op386SUBSD_0(v *Value) bool {
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValue386_Op386SUBSDmem_0(v *Value) bool {
|
||||
func rewriteValue386_Op386SUBSDload_0(v *Value) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
config := b.Func.Config
|
||||
_ = config
|
||||
// match: (SUBSDmem [off1] {sym} val (ADDLconst [off2] base) mem)
|
||||
// match: (SUBSDload [off1] {sym} val (ADDLconst [off2] base) mem)
|
||||
// cond: is32Bit(off1+off2)
|
||||
// result: (SUBSDmem [off1+off2] {sym} val base mem)
|
||||
// result: (SUBSDload [off1+off2] {sym} val base mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym := v.Aux
|
||||
@ -15864,7 +15864,7 @@ func rewriteValue386_Op386SUBSDmem_0(v *Value) bool {
|
||||
if !(is32Bit(off1 + off2)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386SUBSDmem)
|
||||
v.reset(Op386SUBSDload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = sym
|
||||
v.AddArg(val)
|
||||
@ -15872,9 +15872,9 @@ func rewriteValue386_Op386SUBSDmem_0(v *Value) bool {
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
// match: (SUBSDmem [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
|
||||
// match: (SUBSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
|
||||
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
|
||||
// result: (SUBSDmem [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
// result: (SUBSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym1 := v.Aux
|
||||
@ -15891,7 +15891,7 @@ func rewriteValue386_Op386SUBSDmem_0(v *Value) bool {
|
||||
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386SUBSDmem)
|
||||
v.reset(Op386SUBSDload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = mergeSym(sym1, sym2)
|
||||
v.AddArg(val)
|
||||
@ -15908,7 +15908,7 @@ func rewriteValue386_Op386SUBSS_0(v *Value) bool {
|
||||
_ = config
|
||||
// match: (SUBSS x l:(MOVSSload [off] {sym} ptr mem))
|
||||
// cond: canMergeLoad(v, l, x) && !config.use387 && clobber(l)
|
||||
// result: (SUBSSmem x [off] {sym} ptr mem)
|
||||
// result: (SUBSSload x [off] {sym} ptr mem)
|
||||
for {
|
||||
_ = v.Args[1]
|
||||
x := v.Args[0]
|
||||
@ -15924,7 +15924,7 @@ func rewriteValue386_Op386SUBSS_0(v *Value) bool {
|
||||
if !(canMergeLoad(v, l, x) && !config.use387 && clobber(l)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386SUBSSmem)
|
||||
v.reset(Op386SUBSSload)
|
||||
v.AuxInt = off
|
||||
v.Aux = sym
|
||||
v.AddArg(x)
|
||||
@ -15934,14 +15934,14 @@ func rewriteValue386_Op386SUBSS_0(v *Value) bool {
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValue386_Op386SUBSSmem_0(v *Value) bool {
|
||||
func rewriteValue386_Op386SUBSSload_0(v *Value) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
config := b.Func.Config
|
||||
_ = config
|
||||
// match: (SUBSSmem [off1] {sym} val (ADDLconst [off2] base) mem)
|
||||
// match: (SUBSSload [off1] {sym} val (ADDLconst [off2] base) mem)
|
||||
// cond: is32Bit(off1+off2)
|
||||
// result: (SUBSSmem [off1+off2] {sym} val base mem)
|
||||
// result: (SUBSSload [off1+off2] {sym} val base mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym := v.Aux
|
||||
@ -15957,7 +15957,7 @@ func rewriteValue386_Op386SUBSSmem_0(v *Value) bool {
|
||||
if !(is32Bit(off1 + off2)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386SUBSSmem)
|
||||
v.reset(Op386SUBSSload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = sym
|
||||
v.AddArg(val)
|
||||
@ -15965,9 +15965,9 @@ func rewriteValue386_Op386SUBSSmem_0(v *Value) bool {
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
// match: (SUBSSmem [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
|
||||
// match: (SUBSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
|
||||
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
|
||||
// result: (SUBSSmem [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
// result: (SUBSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym1 := v.Aux
|
||||
@ -15984,7 +15984,7 @@ func rewriteValue386_Op386SUBSSmem_0(v *Value) bool {
|
||||
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386SUBSSmem)
|
||||
v.reset(Op386SUBSSload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = mergeSym(sym1, sym2)
|
||||
v.AddArg(val)
|
||||
@ -16195,7 +16195,7 @@ func rewriteValue386_Op386XORL_0(v *Value) bool {
|
||||
}
|
||||
// match: (XORL x l:(MOVLload [off] {sym} ptr mem))
|
||||
// cond: canMergeLoad(v, l, x) && clobber(l)
|
||||
// result: (XORLmem x [off] {sym} ptr mem)
|
||||
// result: (XORLload x [off] {sym} ptr mem)
|
||||
for {
|
||||
_ = v.Args[1]
|
||||
x := v.Args[0]
|
||||
@ -16211,7 +16211,7 @@ func rewriteValue386_Op386XORL_0(v *Value) bool {
|
||||
if !(canMergeLoad(v, l, x) && clobber(l)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386XORLmem)
|
||||
v.reset(Op386XORLload)
|
||||
v.AuxInt = off
|
||||
v.Aux = sym
|
||||
v.AddArg(x)
|
||||
@ -16221,7 +16221,7 @@ func rewriteValue386_Op386XORL_0(v *Value) bool {
|
||||
}
|
||||
// match: (XORL l:(MOVLload [off] {sym} ptr mem) x)
|
||||
// cond: canMergeLoad(v, l, x) && clobber(l)
|
||||
// result: (XORLmem x [off] {sym} ptr mem)
|
||||
// result: (XORLload x [off] {sym} ptr mem)
|
||||
for {
|
||||
_ = v.Args[1]
|
||||
l := v.Args[0]
|
||||
@ -16237,7 +16237,7 @@ func rewriteValue386_Op386XORL_0(v *Value) bool {
|
||||
if !(canMergeLoad(v, l, x) && clobber(l)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386XORLmem)
|
||||
v.reset(Op386XORLload)
|
||||
v.AuxInt = off
|
||||
v.Aux = sym
|
||||
v.AddArg(x)
|
||||
@ -16310,14 +16310,14 @@ func rewriteValue386_Op386XORLconst_0(v *Value) bool {
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValue386_Op386XORLmem_0(v *Value) bool {
|
||||
func rewriteValue386_Op386XORLload_0(v *Value) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
config := b.Func.Config
|
||||
_ = config
|
||||
// match: (XORLmem [off1] {sym} val (ADDLconst [off2] base) mem)
|
||||
// match: (XORLload [off1] {sym} val (ADDLconst [off2] base) mem)
|
||||
// cond: is32Bit(off1+off2)
|
||||
// result: (XORLmem [off1+off2] {sym} val base mem)
|
||||
// result: (XORLload [off1+off2] {sym} val base mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym := v.Aux
|
||||
@ -16333,7 +16333,7 @@ func rewriteValue386_Op386XORLmem_0(v *Value) bool {
|
||||
if !(is32Bit(off1 + off2)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386XORLmem)
|
||||
v.reset(Op386XORLload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = sym
|
||||
v.AddArg(val)
|
||||
@ -16341,9 +16341,9 @@ func rewriteValue386_Op386XORLmem_0(v *Value) bool {
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
// match: (XORLmem [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
|
||||
// match: (XORLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
|
||||
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
|
||||
// result: (XORLmem [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
// result: (XORLload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym1 := v.Aux
|
||||
@ -16360,7 +16360,7 @@ func rewriteValue386_Op386XORLmem_0(v *Value) bool {
|
||||
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386XORLmem)
|
||||
v.reset(Op386XORLload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = mergeSym(sym1, sym2)
|
||||
v.AddArg(val)
|
||||
|
File diff suppressed because it is too large
Load Diff
@ -510,8 +510,8 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
|
||||
gc.AddAux(&p.From, v)
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = v.Reg()
|
||||
case ssa.Op386ADDLmem, ssa.Op386SUBLmem, ssa.Op386ANDLmem, ssa.Op386ORLmem, ssa.Op386XORLmem,
|
||||
ssa.Op386ADDSDmem, ssa.Op386ADDSSmem, ssa.Op386SUBSDmem, ssa.Op386SUBSSmem, ssa.Op386MULSDmem, ssa.Op386MULSSmem:
|
||||
case ssa.Op386ADDLload, ssa.Op386SUBLload, ssa.Op386ANDLload, ssa.Op386ORLload, ssa.Op386XORLload,
|
||||
ssa.Op386ADDSDload, ssa.Op386ADDSSload, ssa.Op386SUBSDload, ssa.Op386SUBSSload, ssa.Op386MULSDload, ssa.Op386MULSSload:
|
||||
p := s.Prog(v.Op.Asm())
|
||||
p.From.Type = obj.TYPE_MEM
|
||||
p.From.Reg = v.Args[1].Reg()
|
||||
|
Loading…
Reference in New Issue
Block a user