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https://github.com/golang/go
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[dev.ssa] cmd/compile: mark LEA and MOV instructions as not clobbering flags
This further reduces the number of flags spills during make.bash by about 50%. Note that GetG is implemented by one or two MOVs, which is why it does not clobber flags. Change-Id: I6fede8c027b7dc340e00d1e15df1b87bf2b2d9ec Reviewed-on: https://go-review.googlesource.com/13843 Reviewed-by: Keith Randall <khr@golang.org>
This commit is contained in:
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@ -93,11 +93,12 @@ func init() {
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// Common regInfo
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// Common regInfo
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var (
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var (
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gp01 = regInfo{inputs: []regMask{}, outputs: gponly, clobbers: flags}
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gp01 = regInfo{inputs: []regMask{}, outputs: gponly}
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gp11 = regInfo{inputs: []regMask{gpsp}, outputs: gponly, clobbers: flags}
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gp11 = regInfo{inputs: []regMask{gpsp}, outputs: gponly, clobbers: flags}
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gp11sb = regInfo{inputs: []regMask{gpspsb}, outputs: gponly, clobbers: flags}
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gp11nf = regInfo{inputs: []regMask{gpsp}, outputs: gponly} // nf: no flags clobbered
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gp11sb = regInfo{inputs: []regMask{gpspsb}, outputs: gponly}
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gp21 = regInfo{inputs: []regMask{gpsp, gpsp}, outputs: gponly, clobbers: flags}
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gp21 = regInfo{inputs: []regMask{gpsp, gpsp}, outputs: gponly, clobbers: flags}
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gp21sb = regInfo{inputs: []regMask{gpspsb, gpsp}, outputs: gponly, clobbers: flags}
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gp21sb = regInfo{inputs: []regMask{gpspsb, gpsp}, outputs: gponly}
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gp21shift = regInfo{inputs: []regMask{gpsp, cx}, outputs: []regMask{gp &^ cx}, clobbers: flags}
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gp21shift = regInfo{inputs: []regMask{gpsp, cx}, outputs: []regMask{gp &^ cx}, clobbers: flags}
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gp11div = regInfo{inputs: []regMask{ax, gpsp &^ dx}, outputs: []regMask{ax},
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gp11div = regInfo{inputs: []regMask{ax, gpsp &^ dx}, outputs: []regMask{ax},
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clobbers: dx | flags}
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clobbers: dx | flags}
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@ -315,12 +316,12 @@ func init() {
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{name: "SETA", reg: readflags, asm: "SETHI"}, // extract unsigned > condition from arg0
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{name: "SETA", reg: readflags, asm: "SETHI"}, // extract unsigned > condition from arg0
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{name: "SETAE", reg: readflags, asm: "SETCC"}, // extract unsigned >= condition from arg0
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{name: "SETAE", reg: readflags, asm: "SETCC"}, // extract unsigned >= condition from arg0
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{name: "MOVBQSX", reg: gp11, asm: "MOVBQSX"}, // sign extend arg0 from int8 to int64
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{name: "MOVBQSX", reg: gp11nf, asm: "MOVBQSX"}, // sign extend arg0 from int8 to int64
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{name: "MOVBQZX", reg: gp11, asm: "MOVBQZX"}, // zero extend arg0 from int8 to int64
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{name: "MOVBQZX", reg: gp11nf, asm: "MOVBQZX"}, // zero extend arg0 from int8 to int64
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{name: "MOVWQSX", reg: gp11, asm: "MOVWQSX"}, // sign extend arg0 from int16 to int64
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{name: "MOVWQSX", reg: gp11nf, asm: "MOVWQSX"}, // sign extend arg0 from int16 to int64
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{name: "MOVWQZX", reg: gp11, asm: "MOVWQZX"}, // zero extend arg0 from int16 to int64
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{name: "MOVWQZX", reg: gp11nf, asm: "MOVWQZX"}, // zero extend arg0 from int16 to int64
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{name: "MOVLQSX", reg: gp11, asm: "MOVLQSX"}, // sign extend arg0 from int32 to int64
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{name: "MOVLQSX", reg: gp11nf, asm: "MOVLQSX"}, // sign extend arg0 from int32 to int64
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{name: "MOVLQZX", reg: gp11, asm: "MOVLQZX"}, // zero extend arg0 from int32 to int64
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{name: "MOVLQZX", reg: gp11nf, asm: "MOVLQZX"}, // zero extend arg0 from int32 to int64
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{name: "MOVBconst", reg: gp01, asm: "MOVB"}, // 8 low bits of auxint
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{name: "MOVBconst", reg: gp01, asm: "MOVB"}, // 8 low bits of auxint
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{name: "MOVWconst", reg: gp01, asm: "MOVW"}, // 16 low bits of auxint
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{name: "MOVWconst", reg: gp01, asm: "MOVW"}, // 16 low bits of auxint
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@ -2261,7 +2261,6 @@ var opcodeTable = [...]opInfo{
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inputs: []inputInfo{
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inputs: []inputInfo{
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{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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clobbers: 8589934592, // .FLAGS
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outputs: []regMask{
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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@ -2420,7 +2419,6 @@ var opcodeTable = [...]opInfo{
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inputs: []inputInfo{
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inputs: []inputInfo{
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{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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clobbers: 8589934592, // .FLAGS
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outputs: []regMask{
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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@ -2433,7 +2431,6 @@ var opcodeTable = [...]opInfo{
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inputs: []inputInfo{
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inputs: []inputInfo{
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{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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clobbers: 8589934592, // .FLAGS
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outputs: []regMask{
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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@ -2446,7 +2443,6 @@ var opcodeTable = [...]opInfo{
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inputs: []inputInfo{
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inputs: []inputInfo{
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{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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clobbers: 8589934592, // .FLAGS
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outputs: []regMask{
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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@ -2459,7 +2455,6 @@ var opcodeTable = [...]opInfo{
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inputs: []inputInfo{
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inputs: []inputInfo{
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{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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clobbers: 8589934592, // .FLAGS
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outputs: []regMask{
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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@ -2472,7 +2467,6 @@ var opcodeTable = [...]opInfo{
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inputs: []inputInfo{
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inputs: []inputInfo{
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{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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clobbers: 8589934592, // .FLAGS
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outputs: []regMask{
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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@ -2495,7 +2489,6 @@ var opcodeTable = [...]opInfo{
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name: "MOVBconst",
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name: "MOVBconst",
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asm: x86.AMOVB,
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asm: x86.AMOVB,
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reg: regInfo{
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reg: regInfo{
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clobbers: 8589934592, // .FLAGS
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outputs: []regMask{
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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@ -2505,7 +2498,6 @@ var opcodeTable = [...]opInfo{
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name: "MOVWconst",
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name: "MOVWconst",
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asm: x86.AMOVW,
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asm: x86.AMOVW,
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reg: regInfo{
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reg: regInfo{
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clobbers: 8589934592, // .FLAGS
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outputs: []regMask{
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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@ -2515,7 +2507,6 @@ var opcodeTable = [...]opInfo{
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name: "MOVLconst",
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name: "MOVLconst",
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asm: x86.AMOVL,
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asm: x86.AMOVL,
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reg: regInfo{
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reg: regInfo{
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clobbers: 8589934592, // .FLAGS
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outputs: []regMask{
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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@ -2525,7 +2516,6 @@ var opcodeTable = [...]opInfo{
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name: "MOVQconst",
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name: "MOVQconst",
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asm: x86.AMOVQ,
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asm: x86.AMOVQ,
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reg: regInfo{
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reg: regInfo{
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clobbers: 8589934592, // .FLAGS
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outputs: []regMask{
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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@ -2537,7 +2527,6 @@ var opcodeTable = [...]opInfo{
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inputs: []inputInfo{
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inputs: []inputInfo{
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{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
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{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
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},
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},
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clobbers: 8589934592, // .FLAGS
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outputs: []regMask{
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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@ -2550,7 +2539,6 @@ var opcodeTable = [...]opInfo{
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{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
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{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
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},
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},
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clobbers: 8589934592, // .FLAGS
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outputs: []regMask{
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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@ -2563,7 +2551,6 @@ var opcodeTable = [...]opInfo{
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{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
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{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
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},
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},
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clobbers: 8589934592, // .FLAGS
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outputs: []regMask{
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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@ -2576,7 +2563,6 @@ var opcodeTable = [...]opInfo{
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{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
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{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
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},
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},
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clobbers: 8589934592, // .FLAGS
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outputs: []regMask{
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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@ -2589,7 +2575,6 @@ var opcodeTable = [...]opInfo{
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{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
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{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
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},
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},
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clobbers: 8589934592, // .FLAGS
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outputs: []regMask{
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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@ -2799,7 +2784,6 @@ var opcodeTable = [...]opInfo{
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{
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{
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name: "LoweredGetG",
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name: "LoweredGetG",
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reg: regInfo{
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reg: regInfo{
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clobbers: 8589934592, // .FLAGS
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outputs: []regMask{
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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