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obj/riscv: fix link to risc-v dwarf register numbers

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The repository name and structure in the RISC-V GitHub org has been
modified, rendering the existing link invalid. This updates to point at
the new location of the RISC-V DWARF specification.

Change occured in https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/208

Change-Id: I8ca4c390bee2d7ce20418cdd00e4945a426cf5f7
Reviewed-on: https://go-review.googlesource.com/c/go/+/363355
Reviewed-by: Brad Fitzpatrick <bradfitz@golang.org>
Trust: Brad Fitzpatrick <bradfitz@golang.org>
Trust: Than McIntosh <thanm@google.com>
This commit is contained in:
hasheddan 2021-11-11 10:02:13 -05:00 committed by Ian Lance Taylor
parent 8ce1a953fb
commit f1935c5270
1 changed files with 1 additions and 1 deletions
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2
src/cmd/internal/obj/riscv/cpu.go
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@ -183,7 +183,7 @@ const (
REGG = REG_G
)
// https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#dwarf-register-numbers
// https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-dwarf.adoc#dwarf-register-numbers
var RISCV64DWARFRegisters = map[int16]int16{
// Integer Registers.
REG_X0: 0,