1
0
mirror of https://github.com/golang/go synced 2024-11-24 00:20:14 -07:00

cmd/compile/internal/arm: merge cases in ssaGenValue

Merge case statement for OpARMSLL, OpARMSRL and OpARMSRA into an
existing one using the same logic.

Change-Id: Ic4224668228902e5188fb0559b5f1949cfea1381
Reviewed-on: https://go-review.googlesource.com/c/go/+/171724
Run-TryBot: Tobias Klauser <tobias.klauser@gmail.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
This commit is contained in:
Tobias Klauser 2019-04-12 14:03:39 +02:00 committed by Tobias Klauser
parent 7cd39de2d9
commit f125b32d19

View File

@ -206,6 +206,9 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
ssa.OpARMADDD,
ssa.OpARMSUBF,
ssa.OpARMSUBD,
ssa.OpARMSLL,
ssa.OpARMSRL,
ssa.OpARMSRA,
ssa.OpARMMULF,
ssa.OpARMMULD,
ssa.OpARMNMULF,
@ -247,18 +250,6 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
p.Reg = r1
p.To.Type = obj.TYPE_REG
p.To.Reg = r
case ssa.OpARMSLL,
ssa.OpARMSRL,
ssa.OpARMSRA:
r := v.Reg()
r1 := v.Args[0].Reg()
r2 := v.Args[1].Reg()
p := s.Prog(v.Op.Asm())
p.From.Type = obj.TYPE_REG
p.From.Reg = r2
p.Reg = r1
p.To.Type = obj.TYPE_REG
p.To.Reg = r
case ssa.OpARMSRAcond:
// ARM shift instructions uses only the low-order byte of the shift amount
// generate conditional instructions to deal with large shifts