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cmd/internal/obj/loong64: reclassify three-register operation instructions and two-register operation instructions

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The instructions belonging to case 32 have the same structure as the
instructions in case 2.

The instructions in case 33 are actually two-register operation
instructions. We move their definitions from function oprrr to oprr and
merge their implementation into case 9.

Change-Id: Id04aaa497e78d8198a58f8d406876d16b3f393a7
Reviewed-on: https://go-review.googlesource.com/c/go/+/565616
Reviewed-by: Qiqi Huang <huangqiqi@loongson.cn>
Reviewed-by: abner chenc <chenguoqi@loongson.cn>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Dmitri Shuralyov <dmitshur@google.com>
Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn>
Reviewed-by: Michael Knyszek <mknyszek@google.com>
This commit is contained in:
limeidan 2024-01-05 10:33:42 +08:00 committed by abner chenc
parent ecadbe9faa
commit ee3da50617
1 changed files with 52 additions and 78 deletions
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130
src/cmd/internal/obj/loong64/asm.go
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@ -74,21 +74,23 @@ var optab = []Optab{
{ANEGW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, {ANEGW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
{ANEGV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, {ANEGV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
{AMASKEQZ, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0}, {AMASKEQZ, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
{ASLL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
{ASLL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
{ASLLV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
{ASLLV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
{AMUL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
{AMUL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
{AMULV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
{AMULV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
{AADDF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 2, 4, 0, 0},
{AADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 2, 4, 0, 0},
{ACMPEQF, C_FREG, C_FREG, C_NONE, C_FCCREG, C_NONE, 2, 4, 0, 0},
{ASLL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 9, 4, 0, 0},
{ASLL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 9, 4, 0, 0},
{ASLLV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 9, 4, 0, 0},
{ASLLV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 9, 4, 0, 0},
{ACLO, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 9, 4, 0, 0}, {ACLO, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 9, 4, 0, 0},
{AABSF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
{AADDF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 32, 4, 0, 0}, {AMOVVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
{AADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 32, 4, 0, 0}, {AMOVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
{AABSF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 33, 4, 0, 0}, {AMOVD, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
{AMOVVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 33, 4, 0, 0},
{AMOVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 33, 4, 0, 0},
{AMOVD, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 33, 4, 0, 0},
{ACMPEQF, C_FREG, C_FREG, C_NONE, C_FCCREG, C_NONE, 29, 4, 0, 0},
{AMOVW, C_REG, C_NONE, C_NONE, C_SEXT, C_NONE, 7, 4, 0, 0}, {AMOVW, C_REG, C_NONE, C_NONE, C_SEXT, C_NONE, 7, 4, 0, 0},
{AMOVWU, C_REG, C_NONE, C_NONE, C_SEXT, C_NONE, 7, 4, 0, 0}, {AMOVWU, C_REG, C_NONE, C_NONE, C_SEXT, C_NONE, 7, 4, 0, 0},
@ -197,11 +199,6 @@ var optab = []Optab{
{AMOVV, C_LCON, C_NONE, C_NONE, C_REG, C_NONE, 19, 8, 0, NOTUSETMP}, {AMOVV, C_LCON, C_NONE, C_NONE, C_REG, C_NONE, 19, 8, 0, NOTUSETMP},
{AMOVV, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 59, 16, 0, NOTUSETMP}, {AMOVV, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 59, 16, 0, NOTUSETMP},
{AMUL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
{AMUL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
{AMULV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
{AMULV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
{AADD, C_ADD0CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0}, {AADD, C_ADD0CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
{AADD, C_ADD0CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0}, {AADD, C_ADD0CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
{AADD, C_ANDCON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0}, {AADD, C_ANDCON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
@ -1388,16 +1385,7 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
o1 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(r), uint32(p.To.Reg)) o1 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(r), uint32(p.To.Reg))
case 9: // sll r1,[r2],r3 case 9: // sll r1,[r2],r3
switch p.As { o1 = OP_RR(c.oprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg))
case ACLO, ACLZ, ACPUCFG:
o1 = OP_RR(c.oprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg))
default:
r := int(p.Reg)
if r == 0 {
r = int(p.To.Reg)
}
o1 = OP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(r), uint32(p.To.Reg))
}
case 10: // add $con,[r1],r2 ==> mov $con, t; add t,[r1],r2 case 10: // add $con,[r1],r2 ==> mov $con, t; add t,[r1],r2
v := c.regoff(&p.From) v := c.regoff(&p.From)
@ -1576,9 +1564,6 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.From.Reg)) o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.From.Reg))
} }
case 29: // fcmp.cond.x fj, fk, fcc
o1 = OP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg))
case 30: // movw r,fr case 30: // movw r,fr
a := OP_TEN(8, 1321) // movgr2fr.w a := OP_TEN(8, 1321) // movgr2fr.w
o1 = OP_RR(a, uint32(p.From.Reg), uint32(p.To.Reg)) o1 = OP_RR(a, uint32(p.From.Reg), uint32(p.To.Reg))
@ -1587,16 +1572,6 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
a := OP_TEN(8, 1325) // movfr2gr.s a := OP_TEN(8, 1325) // movfr2gr.s
o1 = OP_RR(a, uint32(p.From.Reg), uint32(p.To.Reg)) o1 = OP_RR(a, uint32(p.From.Reg), uint32(p.To.Reg))
case 32: // fadd fr1,[fr2],fr3
r := int(p.Reg)
if r == 0 {
r = int(p.To.Reg)
}
o1 = OP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(r), uint32(p.To.Reg))
case 33: // fabs fr1, fr3
o1 = OP_RRR(c.oprrr(p.As), uint32(0), uint32(p.From.Reg), uint32(p.To.Reg))
case 34: // mov $con,fr case 34: // mov $con,fr
v := c.regoff(&p.From) v := c.regoff(&p.From)
a := AADDU a := AADDU
@ -1960,6 +1935,42 @@ func (c *ctxt0) oprrr(a obj.As) uint32 {
return 0x201 << 15 return 0x201 << 15
case AADDD: case AADDD:
return 0x202 << 15 return 0x202 << 15
case ACMPEQF:
return 0x0c1<<20 | 0x4<<15 // FCMP.CEQ.S
case ACMPEQD:
return 0x0c2<<20 | 0x4<<15 // FCMP.CEQ.D
case ACMPGED:
return 0x0c2<<20 | 0x7<<15 // FCMP.SLE.D
case ACMPGEF:
return 0x0c1<<20 | 0x7<<15 // FCMP.SLE.S
case ACMPGTD:
return 0x0c2<<20 | 0x3<<15 // FCMP.SLT.D
case ACMPGTF:
return 0x0c1<<20 | 0x3<<15 // FCMP.SLT.S
}
if a < 0 {
c.ctxt.Diag("bad rrr opcode -%v", -a)
} else {
c.ctxt.Diag("bad rrr opcode %v", a)
}
return 0
}
func (c *ctxt0) oprr(a obj.As) uint32 {
switch a {
case ACLO:
return 0x4 << 10
case ACLZ:
return 0x5 << 10
case ACPUCFG:
return 0x1b << 10
case ARDTIMELW:
return 0x18 << 10
case ARDTIMEHW:
return 0x19 << 10
case ARDTIMED:
return 0x1a << 10
case ATRUNCFV: case ATRUNCFV:
return 0x46a9 << 10 return 0x46a9 << 10
case ATRUNCDV: case ATRUNCDV:
@ -2000,49 +2011,12 @@ func (c *ctxt0) oprrr(a obj.As) uint32 {
return 0x4505 << 10 return 0x4505 << 10
case ANEGD: case ANEGD:
return 0x4506 << 10 return 0x4506 << 10
case ACMPEQF:
return 0x0c1<<20 | 0x4<<15 // FCMP.CEQ.S
case ACMPEQD:
return 0x0c2<<20 | 0x4<<15 // FCMP.CEQ.D
case ACMPGED:
return 0x0c2<<20 | 0x7<<15 // FCMP.SLE.D
case ACMPGEF:
return 0x0c1<<20 | 0x7<<15 // FCMP.SLE.S
case ACMPGTD:
return 0x0c2<<20 | 0x3<<15 // FCMP.SLT.D
case ACMPGTF:
return 0x0c1<<20 | 0x3<<15 // FCMP.SLT.S
case ASQRTF: case ASQRTF:
return 0x4511 << 10 return 0x4511 << 10
case ASQRTD: case ASQRTD:
return 0x4512 << 10 return 0x4512 << 10
} }
if a < 0 {
c.ctxt.Diag("bad rrr opcode -%v", -a)
} else {
c.ctxt.Diag("bad rrr opcode %v", a)
}
return 0
}
func (c *ctxt0) oprr(a obj.As) uint32 {
switch a {
case ACLO:
return 0x4 << 10
case ACLZ:
return 0x5 << 10
case ACPUCFG:
return 0x1b << 10
case ARDTIMELW:
return 0x18 << 10
case ARDTIMEHW:
return 0x19 << 10
case ARDTIMED:
return 0x1a << 10
}
c.ctxt.Diag("bad rr opcode %v", a) c.ctxt.Diag("bad rr opcode %v", a)
return 0 return 0
} }