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cmd/internal/obj/loong64: reclassify three-register operation instructions and two-register operation instructions
The instructions belonging to case 32 have the same structure as the instructions in case 2. The instructions in case 33 are actually two-register operation instructions. We move their definitions from function oprrr to oprr and merge their implementation into case 9. Change-Id: Id04aaa497e78d8198a58f8d406876d16b3f393a7 Reviewed-on: https://go-review.googlesource.com/c/go/+/565616 Reviewed-by: Qiqi Huang <huangqiqi@loongson.cn> Reviewed-by: abner chenc <chenguoqi@loongson.cn> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Dmitri Shuralyov <dmitshur@google.com> Reviewed-by: sophie zhao <zhaoxiaolin@loongson.cn> Reviewed-by: Michael Knyszek <mknyszek@google.com>
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limeidan
abner chenc
parent
ecadbe9faa
commit
ee3da50617
@ -74,21 +74,23 @@ var optab = []Optab{
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{ANEGW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
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{ANEGV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
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{AMASKEQZ, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
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{ASLL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
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{ASLL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
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{ASLLV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
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{ASLLV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
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{AMUL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
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{AMUL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
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{AMULV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
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{AMULV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
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{AADDF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 2, 4, 0, 0},
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{AADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 2, 4, 0, 0},
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{ACMPEQF, C_FREG, C_FREG, C_NONE, C_FCCREG, C_NONE, 2, 4, 0, 0},
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{ASLL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 9, 4, 0, 0},
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{ASLL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 9, 4, 0, 0},
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{ASLLV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 9, 4, 0, 0},
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{ASLLV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 9, 4, 0, 0},
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{ACLO, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 9, 4, 0, 0},
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{AADDF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 32, 4, 0, 0},
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{AADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 32, 4, 0, 0},
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{AABSF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 33, 4, 0, 0},
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{AMOVVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 33, 4, 0, 0},
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{AMOVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 33, 4, 0, 0},
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{AMOVD, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 33, 4, 0, 0},
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{ACMPEQF, C_FREG, C_FREG, C_NONE, C_FCCREG, C_NONE, 29, 4, 0, 0},
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{AABSF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
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{AMOVVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
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{AMOVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
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{AMOVD, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
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{AMOVW, C_REG, C_NONE, C_NONE, C_SEXT, C_NONE, 7, 4, 0, 0},
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{AMOVWU, C_REG, C_NONE, C_NONE, C_SEXT, C_NONE, 7, 4, 0, 0},
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@ -197,11 +199,6 @@ var optab = []Optab{
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{AMOVV, C_LCON, C_NONE, C_NONE, C_REG, C_NONE, 19, 8, 0, NOTUSETMP},
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{AMOVV, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 59, 16, 0, NOTUSETMP},
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{AMUL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
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{AMUL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
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{AMULV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
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{AMULV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
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{AADD, C_ADD0CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
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{AADD, C_ADD0CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
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{AADD, C_ANDCON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
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@ -1388,16 +1385,7 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
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o1 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(r), uint32(p.To.Reg))
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case 9: // sll r1,[r2],r3
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switch p.As {
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case ACLO, ACLZ, ACPUCFG:
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o1 = OP_RR(c.oprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg))
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default:
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r := int(p.Reg)
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if r == 0 {
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r = int(p.To.Reg)
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}
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o1 = OP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(r), uint32(p.To.Reg))
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}
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o1 = OP_RR(c.oprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg))
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case 10: // add $con,[r1],r2 ==> mov $con, t; add t,[r1],r2
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v := c.regoff(&p.From)
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@ -1576,9 +1564,6 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
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o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.From.Reg))
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}
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case 29: // fcmp.cond.x fj, fk, fcc
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o1 = OP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg))
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case 30: // movw r,fr
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a := OP_TEN(8, 1321) // movgr2fr.w
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o1 = OP_RR(a, uint32(p.From.Reg), uint32(p.To.Reg))
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@ -1587,16 +1572,6 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
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a := OP_TEN(8, 1325) // movfr2gr.s
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o1 = OP_RR(a, uint32(p.From.Reg), uint32(p.To.Reg))
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case 32: // fadd fr1,[fr2],fr3
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r := int(p.Reg)
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if r == 0 {
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r = int(p.To.Reg)
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}
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o1 = OP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(r), uint32(p.To.Reg))
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case 33: // fabs fr1, fr3
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o1 = OP_RRR(c.oprrr(p.As), uint32(0), uint32(p.From.Reg), uint32(p.To.Reg))
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case 34: // mov $con,fr
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v := c.regoff(&p.From)
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a := AADDU
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@ -1960,6 +1935,42 @@ func (c *ctxt0) oprrr(a obj.As) uint32 {
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return 0x201 << 15
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case AADDD:
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return 0x202 << 15
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case ACMPEQF:
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return 0x0c1<<20 | 0x4<<15 // FCMP.CEQ.S
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case ACMPEQD:
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return 0x0c2<<20 | 0x4<<15 // FCMP.CEQ.D
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case ACMPGED:
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return 0x0c2<<20 | 0x7<<15 // FCMP.SLE.D
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case ACMPGEF:
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return 0x0c1<<20 | 0x7<<15 // FCMP.SLE.S
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case ACMPGTD:
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return 0x0c2<<20 | 0x3<<15 // FCMP.SLT.D
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case ACMPGTF:
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return 0x0c1<<20 | 0x3<<15 // FCMP.SLT.S
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}
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if a < 0 {
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c.ctxt.Diag("bad rrr opcode -%v", -a)
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} else {
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c.ctxt.Diag("bad rrr opcode %v", a)
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}
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return 0
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}
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func (c *ctxt0) oprr(a obj.As) uint32 {
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switch a {
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case ACLO:
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return 0x4 << 10
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case ACLZ:
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return 0x5 << 10
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case ACPUCFG:
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return 0x1b << 10
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case ARDTIMELW:
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return 0x18 << 10
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case ARDTIMEHW:
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return 0x19 << 10
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case ARDTIMED:
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return 0x1a << 10
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case ATRUNCFV:
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return 0x46a9 << 10
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case ATRUNCDV:
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@ -2000,49 +2011,12 @@ func (c *ctxt0) oprrr(a obj.As) uint32 {
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return 0x4505 << 10
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case ANEGD:
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return 0x4506 << 10
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case ACMPEQF:
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return 0x0c1<<20 | 0x4<<15 // FCMP.CEQ.S
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case ACMPEQD:
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return 0x0c2<<20 | 0x4<<15 // FCMP.CEQ.D
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case ACMPGED:
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return 0x0c2<<20 | 0x7<<15 // FCMP.SLE.D
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case ACMPGEF:
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return 0x0c1<<20 | 0x7<<15 // FCMP.SLE.S
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case ACMPGTD:
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return 0x0c2<<20 | 0x3<<15 // FCMP.SLT.D
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case ACMPGTF:
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return 0x0c1<<20 | 0x3<<15 // FCMP.SLT.S
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case ASQRTF:
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return 0x4511 << 10
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case ASQRTD:
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return 0x4512 << 10
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}
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if a < 0 {
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c.ctxt.Diag("bad rrr opcode -%v", -a)
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} else {
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c.ctxt.Diag("bad rrr opcode %v", a)
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}
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return 0
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}
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func (c *ctxt0) oprr(a obj.As) uint32 {
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switch a {
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case ACLO:
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return 0x4 << 10
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case ACLZ:
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return 0x5 << 10
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case ACPUCFG:
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return 0x1b << 10
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case ARDTIMELW:
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return 0x18 << 10
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case ARDTIMEHW:
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return 0x19 << 10
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case ARDTIMED:
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return 0x1a << 10
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}
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c.ctxt.Diag("bad rr opcode %v", a)
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return 0
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}
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