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https://github.com/golang/go
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all: simplify code using "gofmt -s -w"
Most changes are removing redundant declaration of type when direct
instantiating value of map or slice, e.g. []T{T{}} become []T{{}}.
Small changes are removing the high order of subslice if its value
is the length of slice itself, e.g. T[:len(T)] become T[:].
The following file is excluded due to incompatibility with go1.4,
- src/cmd/compile/internal/gc/ssa.go
Change-Id: Id3abb09401795ce1e6da591a89749cba8502fb26
Reviewed-on: https://go-review.googlesource.com/c/go/+/166437
Run-TryBot: Dave Cheney <dave@cheney.net>
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Ian Lance Taylor <iant@golang.org>
This commit is contained in:
Shulhan
Ian Lance Taylor
parent
04845fe78a
commit
ed7f323c8f
@ -25,16 +25,16 @@ type iselOp struct {
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var iselRegs = [2]int16{ppc64.REG_R0, ppc64.REGTMP}
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var iselOps = map[ssa.Op]iselOp{
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ssa.OpPPC64Equal: iselOp{cond: ppc64.C_COND_EQ, valueIfCond: 1},
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ssa.OpPPC64NotEqual: iselOp{cond: ppc64.C_COND_EQ, valueIfCond: 0},
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ssa.OpPPC64LessThan: iselOp{cond: ppc64.C_COND_LT, valueIfCond: 1},
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ssa.OpPPC64GreaterEqual: iselOp{cond: ppc64.C_COND_LT, valueIfCond: 0},
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ssa.OpPPC64GreaterThan: iselOp{cond: ppc64.C_COND_GT, valueIfCond: 1},
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ssa.OpPPC64LessEqual: iselOp{cond: ppc64.C_COND_GT, valueIfCond: 0},
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ssa.OpPPC64FLessThan: iselOp{cond: ppc64.C_COND_LT, valueIfCond: 1},
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ssa.OpPPC64FGreaterThan: iselOp{cond: ppc64.C_COND_GT, valueIfCond: 1},
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ssa.OpPPC64FLessEqual: iselOp{cond: ppc64.C_COND_LT, valueIfCond: 1}, // 2 comparisons, 2nd is EQ
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ssa.OpPPC64FGreaterEqual: iselOp{cond: ppc64.C_COND_GT, valueIfCond: 1}, // 2 comparisons, 2nd is EQ
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ssa.OpPPC64Equal: {cond: ppc64.C_COND_EQ, valueIfCond: 1},
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ssa.OpPPC64NotEqual: {cond: ppc64.C_COND_EQ, valueIfCond: 0},
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ssa.OpPPC64LessThan: {cond: ppc64.C_COND_LT, valueIfCond: 1},
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ssa.OpPPC64GreaterEqual: {cond: ppc64.C_COND_LT, valueIfCond: 0},
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ssa.OpPPC64GreaterThan: {cond: ppc64.C_COND_GT, valueIfCond: 1},
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ssa.OpPPC64LessEqual: {cond: ppc64.C_COND_GT, valueIfCond: 0},
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ssa.OpPPC64FLessThan: {cond: ppc64.C_COND_LT, valueIfCond: 1},
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ssa.OpPPC64FGreaterThan: {cond: ppc64.C_COND_GT, valueIfCond: 1},
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ssa.OpPPC64FLessEqual: {cond: ppc64.C_COND_LT, valueIfCond: 1}, // 2 comparisons, 2nd is EQ
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ssa.OpPPC64FGreaterEqual: {cond: ppc64.C_COND_GT, valueIfCond: 1}, // 2 comparisons, 2nd is EQ
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}
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// markMoves marks any MOVXconst ops that need to avoid clobbering flags.
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@ -62,7 +62,7 @@ func PseudoVersion(major, older string, t time.Time, rev string) string {
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// Form (2), (3).
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// Extract patch from vMAJOR.MINOR.PATCH
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v := older[:len(older)]
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v := older[:]
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i := strings.LastIndex(v, ".") + 1
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v, patch := v[:i], v[i:]
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@ -68,351 +68,351 @@ type Optab struct {
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var optab = []Optab{
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// zero-length instructions
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Optab{i: 0, as: obj.ATEXT, a1: C_ADDR, a6: C_TEXTSIZE},
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Optab{i: 0, as: obj.ATEXT, a1: C_ADDR, a3: C_LCON, a6: C_TEXTSIZE},
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Optab{i: 0, as: obj.APCDATA, a1: C_LCON, a6: C_LCON},
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Optab{i: 0, as: obj.AFUNCDATA, a1: C_SCON, a6: C_ADDR},
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Optab{i: 0, as: obj.ANOP},
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Optab{i: 0, as: obj.ANOP, a1: C_SAUTO},
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{i: 0, as: obj.ATEXT, a1: C_ADDR, a6: C_TEXTSIZE},
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{i: 0, as: obj.ATEXT, a1: C_ADDR, a3: C_LCON, a6: C_TEXTSIZE},
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{i: 0, as: obj.APCDATA, a1: C_LCON, a6: C_LCON},
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{i: 0, as: obj.AFUNCDATA, a1: C_SCON, a6: C_ADDR},
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{i: 0, as: obj.ANOP},
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{i: 0, as: obj.ANOP, a1: C_SAUTO},
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// move register
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Optab{i: 1, as: AMOVD, a1: C_REG, a6: C_REG},
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Optab{i: 1, as: AMOVB, a1: C_REG, a6: C_REG},
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Optab{i: 1, as: AMOVBZ, a1: C_REG, a6: C_REG},
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Optab{i: 1, as: AMOVW, a1: C_REG, a6: C_REG},
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Optab{i: 1, as: AMOVWZ, a1: C_REG, a6: C_REG},
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Optab{i: 1, as: AFMOVD, a1: C_FREG, a6: C_FREG},
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Optab{i: 1, as: AMOVDBR, a1: C_REG, a6: C_REG},
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{i: 1, as: AMOVD, a1: C_REG, a6: C_REG},
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{i: 1, as: AMOVB, a1: C_REG, a6: C_REG},
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{i: 1, as: AMOVBZ, a1: C_REG, a6: C_REG},
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{i: 1, as: AMOVW, a1: C_REG, a6: C_REG},
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{i: 1, as: AMOVWZ, a1: C_REG, a6: C_REG},
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{i: 1, as: AFMOVD, a1: C_FREG, a6: C_FREG},
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{i: 1, as: AMOVDBR, a1: C_REG, a6: C_REG},
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// load constant
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Optab{i: 26, as: AMOVD, a1: C_LACON, a6: C_REG},
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Optab{i: 26, as: AMOVW, a1: C_LACON, a6: C_REG},
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Optab{i: 26, as: AMOVWZ, a1: C_LACON, a6: C_REG},
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Optab{i: 3, as: AMOVD, a1: C_DCON, a6: C_REG},
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Optab{i: 3, as: AMOVW, a1: C_DCON, a6: C_REG},
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Optab{i: 3, as: AMOVWZ, a1: C_DCON, a6: C_REG},
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Optab{i: 3, as: AMOVB, a1: C_DCON, a6: C_REG},
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Optab{i: 3, as: AMOVBZ, a1: C_DCON, a6: C_REG},
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{i: 26, as: AMOVD, a1: C_LACON, a6: C_REG},
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{i: 26, as: AMOVW, a1: C_LACON, a6: C_REG},
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{i: 26, as: AMOVWZ, a1: C_LACON, a6: C_REG},
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{i: 3, as: AMOVD, a1: C_DCON, a6: C_REG},
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{i: 3, as: AMOVW, a1: C_DCON, a6: C_REG},
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{i: 3, as: AMOVWZ, a1: C_DCON, a6: C_REG},
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{i: 3, as: AMOVB, a1: C_DCON, a6: C_REG},
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{i: 3, as: AMOVBZ, a1: C_DCON, a6: C_REG},
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// store constant
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Optab{i: 72, as: AMOVD, a1: C_SCON, a6: C_LAUTO},
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Optab{i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LAUTO},
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Optab{i: 72, as: AMOVW, a1: C_SCON, a6: C_LAUTO},
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Optab{i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LAUTO},
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Optab{i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LAUTO},
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Optab{i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LAUTO},
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Optab{i: 72, as: AMOVB, a1: C_SCON, a6: C_LAUTO},
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Optab{i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LAUTO},
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Optab{i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LAUTO},
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Optab{i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LAUTO},
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Optab{i: 72, as: AMOVD, a1: C_SCON, a6: C_LOREG},
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Optab{i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LOREG},
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Optab{i: 72, as: AMOVW, a1: C_SCON, a6: C_LOREG},
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Optab{i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LOREG},
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Optab{i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LOREG},
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Optab{i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LOREG},
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Optab{i: 72, as: AMOVB, a1: C_SCON, a6: C_LOREG},
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Optab{i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LOREG},
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Optab{i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LOREG},
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Optab{i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LOREG},
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{i: 72, as: AMOVD, a1: C_SCON, a6: C_LAUTO},
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{i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LAUTO},
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{i: 72, as: AMOVW, a1: C_SCON, a6: C_LAUTO},
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{i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LAUTO},
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{i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LAUTO},
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{i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LAUTO},
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{i: 72, as: AMOVB, a1: C_SCON, a6: C_LAUTO},
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{i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LAUTO},
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{i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LAUTO},
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{i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LAUTO},
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{i: 72, as: AMOVD, a1: C_SCON, a6: C_LOREG},
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{i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LOREG},
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{i: 72, as: AMOVW, a1: C_SCON, a6: C_LOREG},
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{i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LOREG},
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{i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LOREG},
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{i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LOREG},
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{i: 72, as: AMOVB, a1: C_SCON, a6: C_LOREG},
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{i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LOREG},
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{i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LOREG},
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{i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LOREG},
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// store
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Optab{i: 35, as: AMOVD, a1: C_REG, a6: C_LAUTO},
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Optab{i: 35, as: AMOVW, a1: C_REG, a6: C_LAUTO},
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Optab{i: 35, as: AMOVWZ, a1: C_REG, a6: C_LAUTO},
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Optab{i: 35, as: AMOVBZ, a1: C_REG, a6: C_LAUTO},
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Optab{i: 35, as: AMOVB, a1: C_REG, a6: C_LAUTO},
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Optab{i: 35, as: AMOVDBR, a1: C_REG, a6: C_LAUTO},
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Optab{i: 35, as: AMOVHBR, a1: C_REG, a6: C_LAUTO},
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Optab{i: 35, as: AMOVD, a1: C_REG, a6: C_LOREG},
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Optab{i: 35, as: AMOVW, a1: C_REG, a6: C_LOREG},
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Optab{i: 35, as: AMOVWZ, a1: C_REG, a6: C_LOREG},
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Optab{i: 35, as: AMOVBZ, a1: C_REG, a6: C_LOREG},
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Optab{i: 35, as: AMOVB, a1: C_REG, a6: C_LOREG},
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Optab{i: 35, as: AMOVDBR, a1: C_REG, a6: C_LOREG},
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Optab{i: 35, as: AMOVHBR, a1: C_REG, a6: C_LOREG},
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Optab{i: 74, as: AMOVD, a1: C_REG, a6: C_ADDR},
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Optab{i: 74, as: AMOVW, a1: C_REG, a6: C_ADDR},
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Optab{i: 74, as: AMOVWZ, a1: C_REG, a6: C_ADDR},
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Optab{i: 74, as: AMOVBZ, a1: C_REG, a6: C_ADDR},
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Optab{i: 74, as: AMOVB, a1: C_REG, a6: C_ADDR},
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{i: 35, as: AMOVD, a1: C_REG, a6: C_LAUTO},
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{i: 35, as: AMOVW, a1: C_REG, a6: C_LAUTO},
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{i: 35, as: AMOVWZ, a1: C_REG, a6: C_LAUTO},
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{i: 35, as: AMOVBZ, a1: C_REG, a6: C_LAUTO},
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{i: 35, as: AMOVB, a1: C_REG, a6: C_LAUTO},
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{i: 35, as: AMOVDBR, a1: C_REG, a6: C_LAUTO},
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{i: 35, as: AMOVHBR, a1: C_REG, a6: C_LAUTO},
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{i: 35, as: AMOVD, a1: C_REG, a6: C_LOREG},
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{i: 35, as: AMOVW, a1: C_REG, a6: C_LOREG},
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{i: 35, as: AMOVWZ, a1: C_REG, a6: C_LOREG},
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{i: 35, as: AMOVBZ, a1: C_REG, a6: C_LOREG},
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{i: 35, as: AMOVB, a1: C_REG, a6: C_LOREG},
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{i: 35, as: AMOVDBR, a1: C_REG, a6: C_LOREG},
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{i: 35, as: AMOVHBR, a1: C_REG, a6: C_LOREG},
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{i: 74, as: AMOVD, a1: C_REG, a6: C_ADDR},
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{i: 74, as: AMOVW, a1: C_REG, a6: C_ADDR},
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{i: 74, as: AMOVWZ, a1: C_REG, a6: C_ADDR},
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{i: 74, as: AMOVBZ, a1: C_REG, a6: C_ADDR},
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{i: 74, as: AMOVB, a1: C_REG, a6: C_ADDR},
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// load
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Optab{i: 36, as: AMOVD, a1: C_LAUTO, a6: C_REG},
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Optab{i: 36, as: AMOVW, a1: C_LAUTO, a6: C_REG},
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Optab{i: 36, as: AMOVWZ, a1: C_LAUTO, a6: C_REG},
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Optab{i: 36, as: AMOVBZ, a1: C_LAUTO, a6: C_REG},
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Optab{i: 36, as: AMOVB, a1: C_LAUTO, a6: C_REG},
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Optab{i: 36, as: AMOVDBR, a1: C_LAUTO, a6: C_REG},
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Optab{i: 36, as: AMOVHBR, a1: C_LAUTO, a6: C_REG},
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Optab{i: 36, as: AMOVD, a1: C_LOREG, a6: C_REG},
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Optab{i: 36, as: AMOVW, a1: C_LOREG, a6: C_REG},
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Optab{i: 36, as: AMOVWZ, a1: C_LOREG, a6: C_REG},
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Optab{i: 36, as: AMOVBZ, a1: C_LOREG, a6: C_REG},
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Optab{i: 36, as: AMOVB, a1: C_LOREG, a6: C_REG},
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Optab{i: 36, as: AMOVDBR, a1: C_LOREG, a6: C_REG},
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Optab{i: 36, as: AMOVHBR, a1: C_LOREG, a6: C_REG},
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Optab{i: 75, as: AMOVD, a1: C_ADDR, a6: C_REG},
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Optab{i: 75, as: AMOVW, a1: C_ADDR, a6: C_REG},
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Optab{i: 75, as: AMOVWZ, a1: C_ADDR, a6: C_REG},
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Optab{i: 75, as: AMOVBZ, a1: C_ADDR, a6: C_REG},
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Optab{i: 75, as: AMOVB, a1: C_ADDR, a6: C_REG},
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{i: 36, as: AMOVD, a1: C_LAUTO, a6: C_REG},
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{i: 36, as: AMOVW, a1: C_LAUTO, a6: C_REG},
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{i: 36, as: AMOVWZ, a1: C_LAUTO, a6: C_REG},
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{i: 36, as: AMOVBZ, a1: C_LAUTO, a6: C_REG},
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{i: 36, as: AMOVB, a1: C_LAUTO, a6: C_REG},
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{i: 36, as: AMOVDBR, a1: C_LAUTO, a6: C_REG},
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{i: 36, as: AMOVHBR, a1: C_LAUTO, a6: C_REG},
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{i: 36, as: AMOVD, a1: C_LOREG, a6: C_REG},
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{i: 36, as: AMOVW, a1: C_LOREG, a6: C_REG},
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{i: 36, as: AMOVWZ, a1: C_LOREG, a6: C_REG},
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{i: 36, as: AMOVBZ, a1: C_LOREG, a6: C_REG},
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{i: 36, as: AMOVB, a1: C_LOREG, a6: C_REG},
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{i: 36, as: AMOVDBR, a1: C_LOREG, a6: C_REG},
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{i: 36, as: AMOVHBR, a1: C_LOREG, a6: C_REG},
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{i: 75, as: AMOVD, a1: C_ADDR, a6: C_REG},
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{i: 75, as: AMOVW, a1: C_ADDR, a6: C_REG},
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{i: 75, as: AMOVWZ, a1: C_ADDR, a6: C_REG},
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{i: 75, as: AMOVBZ, a1: C_ADDR, a6: C_REG},
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{i: 75, as: AMOVB, a1: C_ADDR, a6: C_REG},
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// interlocked load and op
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Optab{i: 99, as: ALAAG, a1: C_REG, a2: C_REG, a6: C_LOREG},
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{i: 99, as: ALAAG, a1: C_REG, a2: C_REG, a6: C_LOREG},
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// integer arithmetic
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Optab{i: 2, as: AADD, a1: C_REG, a2: C_REG, a6: C_REG},
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Optab{i: 2, as: AADD, a1: C_REG, a6: C_REG},
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Optab{i: 22, as: AADD, a1: C_LCON, a2: C_REG, a6: C_REG},
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Optab{i: 22, as: AADD, a1: C_LCON, a6: C_REG},
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Optab{i: 12, as: AADD, a1: C_LOREG, a6: C_REG},
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Optab{i: 12, as: AADD, a1: C_LAUTO, a6: C_REG},
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Optab{i: 21, as: ASUB, a1: C_LCON, a2: C_REG, a6: C_REG},
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Optab{i: 21, as: ASUB, a1: C_LCON, a6: C_REG},
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Optab{i: 12, as: ASUB, a1: C_LOREG, a6: C_REG},
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Optab{i: 12, as: ASUB, a1: C_LAUTO, a6: C_REG},
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Optab{i: 4, as: AMULHD, a1: C_REG, a6: C_REG},
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Optab{i: 4, as: AMULHD, a1: C_REG, a2: C_REG, a6: C_REG},
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Optab{i: 2, as: ADIVW, a1: C_REG, a2: C_REG, a6: C_REG},
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Optab{i: 2, as: ADIVW, a1: C_REG, a6: C_REG},
|
||||
Optab{i: 10, as: ASUB, a1: C_REG, a2: C_REG, a6: C_REG},
|
||||
Optab{i: 10, as: ASUB, a1: C_REG, a6: C_REG},
|
||||
Optab{i: 47, as: ANEG, a1: C_REG, a6: C_REG},
|
||||
Optab{i: 47, as: ANEG, a6: C_REG},
|
||||
{i: 2, as: AADD, a1: C_REG, a2: C_REG, a6: C_REG},
|
||||
{i: 2, as: AADD, a1: C_REG, a6: C_REG},
|
||||
{i: 22, as: AADD, a1: C_LCON, a2: C_REG, a6: C_REG},
|
||||
{i: 22, as: AADD, a1: C_LCON, a6: C_REG},
|
||||
{i: 12, as: AADD, a1: C_LOREG, a6: C_REG},
|
||||
{i: 12, as: AADD, a1: C_LAUTO, a6: C_REG},
|
||||
{i: 21, as: ASUB, a1: C_LCON, a2: C_REG, a6: C_REG},
|
||||
{i: 21, as: ASUB, a1: C_LCON, a6: C_REG},
|
||||
{i: 12, as: ASUB, a1: C_LOREG, a6: C_REG},
|
||||
{i: 12, as: ASUB, a1: C_LAUTO, a6: C_REG},
|
||||
{i: 4, as: AMULHD, a1: C_REG, a6: C_REG},
|
||||
{i: 4, as: AMULHD, a1: C_REG, a2: C_REG, a6: C_REG},
|
||||
{i: 2, as: ADIVW, a1: C_REG, a2: C_REG, a6: C_REG},
|
||||
{i: 2, as: ADIVW, a1: C_REG, a6: C_REG},
|
||||
{i: 10, as: ASUB, a1: C_REG, a2: C_REG, a6: C_REG},
|
||||
{i: 10, as: ASUB, a1: C_REG, a6: C_REG},
|
||||
{i: 47, as: ANEG, a1: C_REG, a6: C_REG},
|
||||
{i: 47, as: ANEG, a6: C_REG},
|
||||
|
||||
// integer logical
|
||||
Optab{i: 6, as: AAND, a1: C_REG, a2: C_REG, a6: C_REG},
|
||||
Optab{i: 6, as: AAND, a1: C_REG, a6: C_REG},
|
||||
Optab{i: 23, as: AAND, a1: C_LCON, a6: C_REG},
|
||||
Optab{i: 12, as: AAND, a1: C_LOREG, a6: C_REG},
|
||||
Optab{i: 12, as: AAND, a1: C_LAUTO, a6: C_REG},
|
||||
Optab{i: 6, as: AANDW, a1: C_REG, a2: C_REG, a6: C_REG},
|
||||
Optab{i: 6, as: AANDW, a1: C_REG, a6: C_REG},
|
||||
Optab{i: 24, as: AANDW, a1: C_LCON, a6: C_REG},
|
||||
Optab{i: 12, as: AANDW, a1: C_LOREG, a6: C_REG},
|
||||
Optab{i: 12, as: AANDW, a1: C_LAUTO, a6: C_REG},
|
||||
Optab{i: 7, as: ASLD, a1: C_REG, a6: C_REG},
|
||||
Optab{i: 7, as: ASLD, a1: C_REG, a2: C_REG, a6: C_REG},
|
||||
Optab{i: 7, as: ASLD, a1: C_SCON, a2: C_REG, a6: C_REG},
|
||||
Optab{i: 7, as: ASLD, a1: C_SCON, a6: C_REG},
|
||||
Optab{i: 13, as: ARNSBG, a1: C_SCON, a3: C_SCON, a4: C_SCON, a5: C_REG, a6: C_REG},
|
||||
{i: 6, as: AAND, a1: C_REG, a2: C_REG, a6: C_REG},
|
||||
{i: 6, as: AAND, a1: C_REG, a6: C_REG},
|
||||
{i: 23, as: AAND, a1: C_LCON, a6: C_REG},
|
||||
{i: 12, as: AAND, a1: C_LOREG, a6: C_REG},
|
||||
{i: 12, as: AAND, a1: C_LAUTO, a6: C_REG},
|
||||
{i: 6, as: AANDW, a1: C_REG, a2: C_REG, a6: C_REG},
|
||||
{i: 6, as: AANDW, a1: C_REG, a6: C_REG},
|
||||
{i: 24, as: AANDW, a1: C_LCON, a6: C_REG},
|
||||
{i: 12, as: AANDW, a1: C_LOREG, a6: C_REG},
|
||||
{i: 12, as: AANDW, a1: C_LAUTO, a6: C_REG},
|
||||
{i: 7, as: ASLD, a1: C_REG, a6: C_REG},
|
||||
{i: 7, as: ASLD, a1: C_REG, a2: C_REG, a6: C_REG},
|
||||
{i: 7, as: ASLD, a1: C_SCON, a2: C_REG, a6: C_REG},
|
||||
{i: 7, as: ASLD, a1: C_SCON, a6: C_REG},
|
||||
{i: 13, as: ARNSBG, a1: C_SCON, a3: C_SCON, a4: C_SCON, a5: C_REG, a6: C_REG},
|
||||
|
||||
// compare and swap
|
||||
Optab{i: 79, as: ACSG, a1: C_REG, a2: C_REG, a6: C_SOREG},
|
||||
{i: 79, as: ACSG, a1: C_REG, a2: C_REG, a6: C_SOREG},
|
||||
|
||||
// floating point
|
||||
Optab{i: 32, as: AFADD, a1: C_FREG, a6: C_FREG},
|
||||
Optab{i: 33, as: AFABS, a1: C_FREG, a6: C_FREG},
|
||||
Optab{i: 33, as: AFABS, a6: C_FREG},
|
||||
Optab{i: 34, as: AFMADD, a1: C_FREG, a2: C_FREG, a6: C_FREG},
|
||||
Optab{i: 32, as: AFMUL, a1: C_FREG, a6: C_FREG},
|
||||
Optab{i: 36, as: AFMOVD, a1: C_LAUTO, a6: C_FREG},
|
||||
Optab{i: 36, as: AFMOVD, a1: C_LOREG, a6: C_FREG},
|
||||
Optab{i: 75, as: AFMOVD, a1: C_ADDR, a6: C_FREG},
|
||||
Optab{i: 35, as: AFMOVD, a1: C_FREG, a6: C_LAUTO},
|
||||
Optab{i: 35, as: AFMOVD, a1: C_FREG, a6: C_LOREG},
|
||||
Optab{i: 74, as: AFMOVD, a1: C_FREG, a6: C_ADDR},
|
||||
Optab{i: 67, as: AFMOVD, a1: C_ZCON, a6: C_FREG},
|
||||
Optab{i: 81, as: ALDGR, a1: C_REG, a6: C_FREG},
|
||||
Optab{i: 81, as: ALGDR, a1: C_FREG, a6: C_REG},
|
||||
Optab{i: 82, as: ACEFBRA, a1: C_REG, a6: C_FREG},
|
||||
Optab{i: 83, as: ACFEBRA, a1: C_FREG, a6: C_REG},
|
||||
Optab{i: 48, as: AFIEBR, a1: C_SCON, a2: C_FREG, a6: C_FREG},
|
||||
Optab{i: 49, as: ACPSDR, a1: C_FREG, a2: C_FREG, a6: C_FREG},
|
||||
Optab{i: 50, as: ALTDBR, a1: C_FREG, a6: C_FREG},
|
||||
Optab{i: 51, as: ATCDB, a1: C_FREG, a6: C_SCON},
|
||||
{i: 32, as: AFADD, a1: C_FREG, a6: C_FREG},
|
||||
{i: 33, as: AFABS, a1: C_FREG, a6: C_FREG},
|
||||
{i: 33, as: AFABS, a6: C_FREG},
|
||||
{i: 34, as: AFMADD, a1: C_FREG, a2: C_FREG, a6: C_FREG},
|
||||
{i: 32, as: AFMUL, a1: C_FREG, a6: C_FREG},
|
||||
{i: 36, as: AFMOVD, a1: C_LAUTO, a6: C_FREG},
|
||||
{i: 36, as: AFMOVD, a1: C_LOREG, a6: C_FREG},
|
||||
{i: 75, as: AFMOVD, a1: C_ADDR, a6: C_FREG},
|
||||
{i: 35, as: AFMOVD, a1: C_FREG, a6: C_LAUTO},
|
||||
{i: 35, as: AFMOVD, a1: C_FREG, a6: C_LOREG},
|
||||
{i: 74, as: AFMOVD, a1: C_FREG, a6: C_ADDR},
|
||||
{i: 67, as: AFMOVD, a1: C_ZCON, a6: C_FREG},
|
||||
{i: 81, as: ALDGR, a1: C_REG, a6: C_FREG},
|
||||
{i: 81, as: ALGDR, a1: C_FREG, a6: C_REG},
|
||||
{i: 82, as: ACEFBRA, a1: C_REG, a6: C_FREG},
|
||||
{i: 83, as: ACFEBRA, a1: C_FREG, a6: C_REG},
|
||||
{i: 48, as: AFIEBR, a1: C_SCON, a2: C_FREG, a6: C_FREG},
|
||||
{i: 49, as: ACPSDR, a1: C_FREG, a2: C_FREG, a6: C_FREG},
|
||||
{i: 50, as: ALTDBR, a1: C_FREG, a6: C_FREG},
|
||||
{i: 51, as: ATCDB, a1: C_FREG, a6: C_SCON},
|
||||
|
||||
// load symbol address (plus offset)
|
||||
Optab{i: 19, as: AMOVD, a1: C_SYMADDR, a6: C_REG},
|
||||
Optab{i: 93, as: AMOVD, a1: C_GOTADDR, a6: C_REG},
|
||||
Optab{i: 94, as: AMOVD, a1: C_TLS_LE, a6: C_REG},
|
||||
Optab{i: 95, as: AMOVD, a1: C_TLS_IE, a6: C_REG},
|
||||
{i: 19, as: AMOVD, a1: C_SYMADDR, a6: C_REG},
|
||||
{i: 93, as: AMOVD, a1: C_GOTADDR, a6: C_REG},
|
||||
{i: 94, as: AMOVD, a1: C_TLS_LE, a6: C_REG},
|
||||
{i: 95, as: AMOVD, a1: C_TLS_IE, a6: C_REG},
|
||||
|
||||
// system call
|
||||
Optab{i: 5, as: ASYSCALL},
|
||||
Optab{i: 77, as: ASYSCALL, a1: C_SCON},
|
||||
{i: 5, as: ASYSCALL},
|
||||
{i: 77, as: ASYSCALL, a1: C_SCON},
|
||||
|
||||
// branch
|
||||
Optab{i: 16, as: ABEQ, a6: C_SBRA},
|
||||
Optab{i: 11, as: ABR, a6: C_LBRA},
|
||||
Optab{i: 16, as: ABC, a1: C_SCON, a2: C_REG, a6: C_LBRA},
|
||||
Optab{i: 18, as: ABR, a6: C_REG},
|
||||
Optab{i: 18, as: ABR, a1: C_REG, a6: C_REG},
|
||||
Optab{i: 15, as: ABR, a6: C_ZOREG},
|
||||
Optab{i: 15, as: ABC, a6: C_ZOREG},
|
||||
Optab{i: 89, as: ACMPBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA},
|
||||
Optab{i: 90, as: ACMPBEQ, a1: C_REG, a3: C_ADDCON, a6: C_SBRA},
|
||||
Optab{i: 90, as: ACMPBEQ, a1: C_REG, a3: C_SCON, a6: C_SBRA},
|
||||
Optab{i: 89, as: ACMPUBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA},
|
||||
Optab{i: 90, as: ACMPUBEQ, a1: C_REG, a3: C_ANDCON, a6: C_SBRA},
|
||||
{i: 16, as: ABEQ, a6: C_SBRA},
|
||||
{i: 11, as: ABR, a6: C_LBRA},
|
||||
{i: 16, as: ABC, a1: C_SCON, a2: C_REG, a6: C_LBRA},
|
||||
{i: 18, as: ABR, a6: C_REG},
|
||||
{i: 18, as: ABR, a1: C_REG, a6: C_REG},
|
||||
{i: 15, as: ABR, a6: C_ZOREG},
|
||||
{i: 15, as: ABC, a6: C_ZOREG},
|
||||
{i: 89, as: ACMPBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA},
|
||||
{i: 90, as: ACMPBEQ, a1: C_REG, a3: C_ADDCON, a6: C_SBRA},
|
||||
{i: 90, as: ACMPBEQ, a1: C_REG, a3: C_SCON, a6: C_SBRA},
|
||||
{i: 89, as: ACMPUBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA},
|
||||
{i: 90, as: ACMPUBEQ, a1: C_REG, a3: C_ANDCON, a6: C_SBRA},
|
||||
|
||||
// move on condition
|
||||
Optab{i: 17, as: AMOVDEQ, a1: C_REG, a6: C_REG},
|
||||
{i: 17, as: AMOVDEQ, a1: C_REG, a6: C_REG},
|
||||
|
||||
// find leftmost one
|
||||
Optab{i: 8, as: AFLOGR, a1: C_REG, a6: C_REG},
|
||||
{i: 8, as: AFLOGR, a1: C_REG, a6: C_REG},
|
||||
|
||||
// population count
|
||||
Optab{i: 9, as: APOPCNT, a1: C_REG, a6: C_REG},
|
||||
{i: 9, as: APOPCNT, a1: C_REG, a6: C_REG},
|
||||
|
||||
// compare
|
||||
Optab{i: 70, as: ACMP, a1: C_REG, a6: C_REG},
|
||||
Optab{i: 71, as: ACMP, a1: C_REG, a6: C_LCON},
|
||||
Optab{i: 70, as: ACMPU, a1: C_REG, a6: C_REG},
|
||||
Optab{i: 71, as: ACMPU, a1: C_REG, a6: C_LCON},
|
||||
Optab{i: 70, as: AFCMPO, a1: C_FREG, a6: C_FREG},
|
||||
Optab{i: 70, as: AFCMPO, a1: C_FREG, a2: C_REG, a6: C_FREG},
|
||||
{i: 70, as: ACMP, a1: C_REG, a6: C_REG},
|
||||
{i: 71, as: ACMP, a1: C_REG, a6: C_LCON},
|
||||
{i: 70, as: ACMPU, a1: C_REG, a6: C_REG},
|
||||
{i: 71, as: ACMPU, a1: C_REG, a6: C_LCON},
|
||||
{i: 70, as: AFCMPO, a1: C_FREG, a6: C_FREG},
|
||||
{i: 70, as: AFCMPO, a1: C_FREG, a2: C_REG, a6: C_FREG},
|
||||
|
||||
// test under mask
|
||||
Optab{i: 91, as: ATMHH, a1: C_REG, a6: C_ANDCON},
|
||||
{i: 91, as: ATMHH, a1: C_REG, a6: C_ANDCON},
|
||||
|
||||
// insert program mask
|
||||
Optab{i: 92, as: AIPM, a1: C_REG},
|
||||
{i: 92, as: AIPM, a1: C_REG},
|
||||
|
||||
// 32-bit access registers
|
||||
Optab{i: 68, as: AMOVW, a1: C_AREG, a6: C_REG},
|
||||
Optab{i: 68, as: AMOVWZ, a1: C_AREG, a6: C_REG},
|
||||
Optab{i: 69, as: AMOVW, a1: C_REG, a6: C_AREG},
|
||||
Optab{i: 69, as: AMOVWZ, a1: C_REG, a6: C_AREG},
|
||||
{i: 68, as: AMOVW, a1: C_AREG, a6: C_REG},
|
||||
{i: 68, as: AMOVWZ, a1: C_AREG, a6: C_REG},
|
||||
{i: 69, as: AMOVW, a1: C_REG, a6: C_AREG},
|
||||
{i: 69, as: AMOVWZ, a1: C_REG, a6: C_AREG},
|
||||
|
||||
// macros
|
||||
Optab{i: 96, as: ACLEAR, a1: C_LCON, a6: C_LOREG},
|
||||
Optab{i: 96, as: ACLEAR, a1: C_LCON, a6: C_LAUTO},
|
||||
{i: 96, as: ACLEAR, a1: C_LCON, a6: C_LOREG},
|
||||
{i: 96, as: ACLEAR, a1: C_LCON, a6: C_LAUTO},
|
||||
|
||||
// load/store multiple
|
||||
Optab{i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LOREG},
|
||||
Optab{i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LAUTO},
|
||||
Optab{i: 98, as: ALMG, a1: C_LOREG, a2: C_REG, a6: C_REG},
|
||||
Optab{i: 98, as: ALMG, a1: C_LAUTO, a2: C_REG, a6: C_REG},
|
||||
{i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LOREG},
|
||||
{i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LAUTO},
|
||||
{i: 98, as: ALMG, a1: C_LOREG, a2: C_REG, a6: C_REG},
|
||||
{i: 98, as: ALMG, a1: C_LAUTO, a2: C_REG, a6: C_REG},
|
||||
|
||||
// bytes
|
||||
Optab{i: 40, as: ABYTE, a1: C_SCON},
|
||||
Optab{i: 40, as: AWORD, a1: C_LCON},
|
||||
Optab{i: 31, as: ADWORD, a1: C_LCON},
|
||||
Optab{i: 31, as: ADWORD, a1: C_DCON},
|
||||
{i: 40, as: ABYTE, a1: C_SCON},
|
||||
{i: 40, as: AWORD, a1: C_LCON},
|
||||
{i: 31, as: ADWORD, a1: C_LCON},
|
||||
{i: 31, as: ADWORD, a1: C_DCON},
|
||||
|
||||
// fast synchronization
|
||||
Optab{i: 80, as: ASYNC},
|
||||
{i: 80, as: ASYNC},
|
||||
|
||||
// store clock
|
||||
Optab{i: 88, as: ASTCK, a6: C_SAUTO},
|
||||
Optab{i: 88, as: ASTCK, a6: C_SOREG},
|
||||
{i: 88, as: ASTCK, a6: C_SAUTO},
|
||||
{i: 88, as: ASTCK, a6: C_SOREG},
|
||||
|
||||
// storage and storage
|
||||
Optab{i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LOREG},
|
||||
Optab{i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LAUTO},
|
||||
Optab{i: 84, as: AMVC, a1: C_SCON, a3: C_LAUTO, a6: C_LAUTO},
|
||||
{i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LOREG},
|
||||
{i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LAUTO},
|
||||
{i: 84, as: AMVC, a1: C_SCON, a3: C_LAUTO, a6: C_LAUTO},
|
||||
|
||||
// address
|
||||
Optab{i: 85, as: ALARL, a1: C_LCON, a6: C_REG},
|
||||
Optab{i: 85, as: ALARL, a1: C_SYMADDR, a6: C_REG},
|
||||
Optab{i: 86, as: ALA, a1: C_SOREG, a6: C_REG},
|
||||
Optab{i: 86, as: ALA, a1: C_SAUTO, a6: C_REG},
|
||||
Optab{i: 87, as: AEXRL, a1: C_SYMADDR, a6: C_REG},
|
||||
{i: 85, as: ALARL, a1: C_LCON, a6: C_REG},
|
||||
{i: 85, as: ALARL, a1: C_SYMADDR, a6: C_REG},
|
||||
{i: 86, as: ALA, a1: C_SOREG, a6: C_REG},
|
||||
{i: 86, as: ALA, a1: C_SAUTO, a6: C_REG},
|
||||
{i: 87, as: AEXRL, a1: C_SYMADDR, a6: C_REG},
|
||||
|
||||
// undefined (deliberate illegal instruction)
|
||||
Optab{i: 78, as: obj.AUNDEF},
|
||||
{i: 78, as: obj.AUNDEF},
|
||||
|
||||
// vector instructions
|
||||
|
||||
// VRX store
|
||||
Optab{i: 100, as: AVST, a1: C_VREG, a6: C_SOREG},
|
||||
Optab{i: 100, as: AVST, a1: C_VREG, a6: C_SAUTO},
|
||||
Optab{i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG},
|
||||
Optab{i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO},
|
||||
{i: 100, as: AVST, a1: C_VREG, a6: C_SOREG},
|
||||
{i: 100, as: AVST, a1: C_VREG, a6: C_SAUTO},
|
||||
{i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG},
|
||||
{i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO},
|
||||
|
||||
// VRX load
|
||||
Optab{i: 101, as: AVL, a1: C_SOREG, a6: C_VREG},
|
||||
Optab{i: 101, as: AVL, a1: C_SAUTO, a6: C_VREG},
|
||||
Optab{i: 101, as: AVLEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG},
|
||||
Optab{i: 101, as: AVLEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG},
|
||||
{i: 101, as: AVL, a1: C_SOREG, a6: C_VREG},
|
||||
{i: 101, as: AVL, a1: C_SAUTO, a6: C_VREG},
|
||||
{i: 101, as: AVLEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG},
|
||||
{i: 101, as: AVLEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG},
|
||||
|
||||
// VRV scatter
|
||||
Optab{i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG},
|
||||
Optab{i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO},
|
||||
{i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG},
|
||||
{i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO},
|
||||
|
||||
// VRV gather
|
||||
Optab{i: 103, as: AVGEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG},
|
||||
Optab{i: 103, as: AVGEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG},
|
||||
{i: 103, as: AVGEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG},
|
||||
{i: 103, as: AVGEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG},
|
||||
|
||||
// VRS element shift/rotate and load gr to/from vr element
|
||||
Optab{i: 104, as: AVESLG, a1: C_SCON, a2: C_VREG, a6: C_VREG},
|
||||
Optab{i: 104, as: AVESLG, a1: C_REG, a2: C_VREG, a6: C_VREG},
|
||||
Optab{i: 104, as: AVESLG, a1: C_SCON, a6: C_VREG},
|
||||
Optab{i: 104, as: AVESLG, a1: C_REG, a6: C_VREG},
|
||||
Optab{i: 104, as: AVLGVG, a1: C_SCON, a2: C_VREG, a6: C_REG},
|
||||
Optab{i: 104, as: AVLGVG, a1: C_REG, a2: C_VREG, a6: C_REG},
|
||||
Optab{i: 104, as: AVLVGG, a1: C_SCON, a2: C_REG, a6: C_VREG},
|
||||
Optab{i: 104, as: AVLVGG, a1: C_REG, a2: C_REG, a6: C_VREG},
|
||||
{i: 104, as: AVESLG, a1: C_SCON, a2: C_VREG, a6: C_VREG},
|
||||
{i: 104, as: AVESLG, a1: C_REG, a2: C_VREG, a6: C_VREG},
|
||||
{i: 104, as: AVESLG, a1: C_SCON, a6: C_VREG},
|
||||
{i: 104, as: AVESLG, a1: C_REG, a6: C_VREG},
|
||||
{i: 104, as: AVLGVG, a1: C_SCON, a2: C_VREG, a6: C_REG},
|
||||
{i: 104, as: AVLGVG, a1: C_REG, a2: C_VREG, a6: C_REG},
|
||||
{i: 104, as: AVLVGG, a1: C_SCON, a2: C_REG, a6: C_VREG},
|
||||
{i: 104, as: AVLVGG, a1: C_REG, a2: C_REG, a6: C_VREG},
|
||||
|
||||
// VRS store multiple
|
||||
Optab{i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SOREG},
|
||||
Optab{i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SAUTO},
|
||||
{i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SOREG},
|
||||
{i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SAUTO},
|
||||
|
||||
// VRS load multiple
|
||||
Optab{i: 106, as: AVLM, a1: C_SOREG, a2: C_VREG, a6: C_VREG},
|
||||
Optab{i: 106, as: AVLM, a1: C_SAUTO, a2: C_VREG, a6: C_VREG},
|
||||
{i: 106, as: AVLM, a1: C_SOREG, a2: C_VREG, a6: C_VREG},
|
||||
{i: 106, as: AVLM, a1: C_SAUTO, a2: C_VREG, a6: C_VREG},
|
||||
|
||||
// VRS store with length
|
||||
Optab{i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SOREG},
|
||||
Optab{i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SAUTO},
|
||||
{i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SOREG},
|
||||
{i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SAUTO},
|
||||
|
||||
// VRS load with length
|
||||
Optab{i: 108, as: AVLL, a1: C_REG, a3: C_SOREG, a6: C_VREG},
|
||||
Optab{i: 108, as: AVLL, a1: C_REG, a3: C_SAUTO, a6: C_VREG},
|
||||
{i: 108, as: AVLL, a1: C_REG, a3: C_SOREG, a6: C_VREG},
|
||||
{i: 108, as: AVLL, a1: C_REG, a3: C_SAUTO, a6: C_VREG},
|
||||
|
||||
// VRI-a
|
||||
Optab{i: 109, as: AVGBM, a1: C_ANDCON, a6: C_VREG},
|
||||
Optab{i: 109, as: AVZERO, a6: C_VREG},
|
||||
Optab{i: 109, as: AVREPIG, a1: C_ADDCON, a6: C_VREG},
|
||||
Optab{i: 109, as: AVREPIG, a1: C_SCON, a6: C_VREG},
|
||||
Optab{i: 109, as: AVLEIG, a1: C_SCON, a3: C_ADDCON, a6: C_VREG},
|
||||
Optab{i: 109, as: AVLEIG, a1: C_SCON, a3: C_SCON, a6: C_VREG},
|
||||
{i: 109, as: AVGBM, a1: C_ANDCON, a6: C_VREG},
|
||||
{i: 109, as: AVZERO, a6: C_VREG},
|
||||
{i: 109, as: AVREPIG, a1: C_ADDCON, a6: C_VREG},
|
||||
{i: 109, as: AVREPIG, a1: C_SCON, a6: C_VREG},
|
||||
{i: 109, as: AVLEIG, a1: C_SCON, a3: C_ADDCON, a6: C_VREG},
|
||||
{i: 109, as: AVLEIG, a1: C_SCON, a3: C_SCON, a6: C_VREG},
|
||||
|
||||
// VRI-b generate mask
|
||||
Optab{i: 110, as: AVGMG, a1: C_SCON, a3: C_SCON, a6: C_VREG},
|
||||
{i: 110, as: AVGMG, a1: C_SCON, a3: C_SCON, a6: C_VREG},
|
||||
|
||||
// VRI-c replicate
|
||||
Optab{i: 111, as: AVREPG, a1: C_UCON, a2: C_VREG, a6: C_VREG},
|
||||
{i: 111, as: AVREPG, a1: C_UCON, a2: C_VREG, a6: C_VREG},
|
||||
|
||||
// VRI-d element rotate and insert under mask and
|
||||
// shift left double by byte
|
||||
Optab{i: 112, as: AVERIMG, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
|
||||
Optab{i: 112, as: AVSLDB, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
|
||||
{i: 112, as: AVERIMG, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
|
||||
{i: 112, as: AVSLDB, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
|
||||
|
||||
// VRI-d fp test data class immediate
|
||||
Optab{i: 113, as: AVFTCIDB, a1: C_SCON, a2: C_VREG, a6: C_VREG},
|
||||
{i: 113, as: AVFTCIDB, a1: C_SCON, a2: C_VREG, a6: C_VREG},
|
||||
|
||||
// VRR-a load reg
|
||||
Optab{i: 114, as: AVLR, a1: C_VREG, a6: C_VREG},
|
||||
{i: 114, as: AVLR, a1: C_VREG, a6: C_VREG},
|
||||
|
||||
// VRR-a compare
|
||||
Optab{i: 115, as: AVECG, a1: C_VREG, a6: C_VREG},
|
||||
{i: 115, as: AVECG, a1: C_VREG, a6: C_VREG},
|
||||
|
||||
// VRR-b
|
||||
Optab{i: 117, as: AVCEQG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
|
||||
Optab{i: 117, as: AVFAEF, a1: C_VREG, a2: C_VREG, a6: C_VREG},
|
||||
Optab{i: 117, as: AVPKSG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
|
||||
{i: 117, as: AVCEQG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
|
||||
{i: 117, as: AVFAEF, a1: C_VREG, a2: C_VREG, a6: C_VREG},
|
||||
{i: 117, as: AVPKSG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
|
||||
|
||||
// VRR-c
|
||||
Optab{i: 118, as: AVAQ, a1: C_VREG, a2: C_VREG, a6: C_VREG},
|
||||
Optab{i: 118, as: AVAQ, a1: C_VREG, a6: C_VREG},
|
||||
Optab{i: 118, as: AVNOT, a1: C_VREG, a6: C_VREG},
|
||||
Optab{i: 123, as: AVPDI, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
|
||||
{i: 118, as: AVAQ, a1: C_VREG, a2: C_VREG, a6: C_VREG},
|
||||
{i: 118, as: AVAQ, a1: C_VREG, a6: C_VREG},
|
||||
{i: 118, as: AVNOT, a1: C_VREG, a6: C_VREG},
|
||||
{i: 123, as: AVPDI, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
|
||||
|
||||
// VRR-c shifts
|
||||
Optab{i: 119, as: AVERLLVG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
|
||||
Optab{i: 119, as: AVERLLVG, a1: C_VREG, a6: C_VREG},
|
||||
{i: 119, as: AVERLLVG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
|
||||
{i: 119, as: AVERLLVG, a1: C_VREG, a6: C_VREG},
|
||||
|
||||
// VRR-d
|
||||
Optab{i: 120, as: AVACQ, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG},
|
||||
{i: 120, as: AVACQ, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG},
|
||||
|
||||
// VRR-e
|
||||
Optab{i: 121, as: AVSEL, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG},
|
||||
{i: 121, as: AVSEL, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG},
|
||||
|
||||
// VRR-f
|
||||
Optab{i: 122, as: AVLVGP, a1: C_REG, a2: C_REG, a6: C_VREG},
|
||||
{i: 122, as: AVLVGP, a1: C_REG, a2: C_REG, a6: C_VREG},
|
||||
}
|
||||
|
||||
var oprange [ALAST & obj.AMask][]Optab
|
||||
|
||||
@ -164,9 +164,9 @@ func main() {
|
||||
}`
|
||||
|
||||
want := map[string]map[string]bool{
|
||||
"main.Foo": map[string]bool{"v": false},
|
||||
"main.Bar": map[string]bool{"Foo": true, "name": false},
|
||||
"main.Baz": map[string]bool{"Foo": true, "name": false},
|
||||
"main.Foo": {"v": false},
|
||||
"main.Bar": {"Foo": true, "name": false},
|
||||
"main.Baz": {"Foo": true, "name": false},
|
||||
}
|
||||
|
||||
dir, err := ioutil.TempDir("", "TestEmbeddedStructMarker")
|
||||
|
||||
@ -54,21 +54,21 @@ type wasmFuncType struct {
|
||||
}
|
||||
|
||||
var wasmFuncTypes = map[string]*wasmFuncType{
|
||||
"_rt0_wasm_js": &wasmFuncType{Params: []byte{}}, //
|
||||
"wasm_export_run": &wasmFuncType{Params: []byte{I32, I32}}, // argc, argv
|
||||
"wasm_export_resume": &wasmFuncType{Params: []byte{}}, //
|
||||
"wasm_export_getsp": &wasmFuncType{Results: []byte{I32}}, // sp
|
||||
"wasm_pc_f_loop": &wasmFuncType{Params: []byte{}}, //
|
||||
"runtime.wasmMove": &wasmFuncType{Params: []byte{I32, I32, I32}}, // dst, src, len
|
||||
"runtime.wasmZero": &wasmFuncType{Params: []byte{I32, I32}}, // ptr, len
|
||||
"runtime.wasmDiv": &wasmFuncType{Params: []byte{I64, I64}, Results: []byte{I64}}, // x, y -> x/y
|
||||
"runtime.wasmTruncS": &wasmFuncType{Params: []byte{F64}, Results: []byte{I64}}, // x -> int(x)
|
||||
"runtime.wasmTruncU": &wasmFuncType{Params: []byte{F64}, Results: []byte{I64}}, // x -> uint(x)
|
||||
"runtime.gcWriteBarrier": &wasmFuncType{Params: []byte{I64, I64}}, // ptr, val
|
||||
"cmpbody": &wasmFuncType{Params: []byte{I64, I64, I64, I64}, Results: []byte{I64}}, // a, alen, b, blen -> -1/0/1
|
||||
"memeqbody": &wasmFuncType{Params: []byte{I64, I64, I64}, Results: []byte{I64}}, // a, b, len -> 0/1
|
||||
"memcmp": &wasmFuncType{Params: []byte{I32, I32, I32}, Results: []byte{I32}}, // a, b, len -> <0/0/>0
|
||||
"memchr": &wasmFuncType{Params: []byte{I32, I32, I32}, Results: []byte{I32}}, // s, c, len -> index
|
||||
"_rt0_wasm_js": {Params: []byte{}}, //
|
||||
"wasm_export_run": {Params: []byte{I32, I32}}, // argc, argv
|
||||
"wasm_export_resume": {Params: []byte{}}, //
|
||||
"wasm_export_getsp": {Results: []byte{I32}}, // sp
|
||||
"wasm_pc_f_loop": {Params: []byte{}}, //
|
||||
"runtime.wasmMove": {Params: []byte{I32, I32, I32}}, // dst, src, len
|
||||
"runtime.wasmZero": {Params: []byte{I32, I32}}, // ptr, len
|
||||
"runtime.wasmDiv": {Params: []byte{I64, I64}, Results: []byte{I64}}, // x, y -> x/y
|
||||
"runtime.wasmTruncS": {Params: []byte{F64}, Results: []byte{I64}}, // x -> int(x)
|
||||
"runtime.wasmTruncU": {Params: []byte{F64}, Results: []byte{I64}}, // x -> uint(x)
|
||||
"runtime.gcWriteBarrier": {Params: []byte{I64, I64}}, // ptr, val
|
||||
"cmpbody": {Params: []byte{I64, I64, I64, I64}, Results: []byte{I64}}, // a, alen, b, blen -> -1/0/1
|
||||
"memeqbody": {Params: []byte{I64, I64, I64}, Results: []byte{I64}}, // a, b, len -> 0/1
|
||||
"memcmp": {Params: []byte{I32, I32, I32}, Results: []byte{I32}}, // a, b, len -> <0/0/>0
|
||||
"memchr": {Params: []byte{I32, I32, I32}, Results: []byte{I32}}, // s, c, len -> index
|
||||
}
|
||||
|
||||
func assignAddress(ctxt *ld.Link, sect *sym.Section, n int, s *sym.Symbol, va uint64, isTramp bool) (*sym.Section, int, uint64) {
|
||||
@ -105,12 +105,12 @@ func asmb2(ctxt *ld.Link) {
|
||||
// For normal Go functions the return value is
|
||||
// 0 if the function returned normally or
|
||||
// 1 if the stack needs to be unwound.
|
||||
&wasmFuncType{Results: []byte{I32}},
|
||||
{Results: []byte{I32}},
|
||||
}
|
||||
|
||||
// collect host imports (functions that get imported from the WebAssembly host, usually JavaScript)
|
||||
hostImports := []*wasmFunc{
|
||||
&wasmFunc{
|
||||
{
|
||||
Name: "debug",
|
||||
Type: lookupType(&wasmFuncType{Params: []byte{I32}}, &types),
|
||||
},
|
||||
|
||||
@ -358,7 +358,7 @@ func buildProfile(prof map[uint64]Record) *profile.Profile {
|
||||
ID: uint64(len(p.Location) + 1),
|
||||
Address: frame.PC,
|
||||
Line: []profile.Line{
|
||||
profile.Line{
|
||||
{
|
||||
Function: fn,
|
||||
Line: int64(frame.Line),
|
||||
},
|
||||
|
||||
@ -169,12 +169,12 @@ type unmarshalTest struct {
|
||||
|
||||
var largeUnmarshalTests = []unmarshalTest{
|
||||
// Data length: 7_102_415_735
|
||||
unmarshalTest{
|
||||
{
|
||||
state: "md5\x01\xa5\xf7\xf0=\xd6S\x85\xd9M\n}\xc3\u0601\x89\xe7@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_`abcdefghijklmnopqrstuv\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x01\xa7VCw",
|
||||
sum: "cddefcf74ffec709a0b45a6a987564d5",
|
||||
},
|
||||
// Data length: 6_565_544_823
|
||||
unmarshalTest{
|
||||
{
|
||||
state: "md5\x01{\xda\x1a\xc7\xc9'?\x83EX\xe0\x88q\xfeG\x18@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_`abcdefghijklmnopqrstuv\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x01\x87VCw",
|
||||
sum: "fd9f41874ab240698e7bc9c3ae70c8e4",
|
||||
},
|
||||
|
||||
@ -168,12 +168,12 @@ type unmarshalTest struct {
|
||||
|
||||
var largeUnmarshalTests = []unmarshalTest{
|
||||
// Data length: 7_102_415_735
|
||||
unmarshalTest{
|
||||
{
|
||||
state: "sha\x01\x13\xbc\xfe\x83\x8c\xbd\xdfP\x1f\xd8ڿ<\x9eji8t\xe1\xa5@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_`abcdefghijklmnopqrstuv\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x01\xa7VCw",
|
||||
sum: "bc6245c9959cc33e1c2592e5c9ea9b5d0431246c",
|
||||
},
|
||||
// Data length: 6_565_544_823
|
||||
unmarshalTest{
|
||||
{
|
||||
state: "sha\x01m;\x16\xa6R\xbe@\xa9nĈ\xf9S\x03\x00B\xc2\xdcv\xcf@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_`abcdefghijklmnopqrstuv\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x01\x87VCw",
|
||||
sum: "8f2d1c0e4271768f35feb918bfe21ea1387a2072",
|
||||
},
|
||||
|
||||
@ -241,19 +241,19 @@ type unmarshalTest struct {
|
||||
|
||||
var largeUnmarshalTests = []unmarshalTest{
|
||||
// Data length: 7_115_087_207
|
||||
unmarshalTest{
|
||||
{
|
||||
state: "sha\x03yX\xaf\xb7\x04*\x8f\xaa\x9bx\xc5#\x1f\xeb\x94\xfdz1\xaf\xfbk֗\n\xc93\xcf\x02\v.\xa5\xe4\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x01\xa8\x17\x9dg",
|
||||
sum: "f5e06371f0c115e9968455c8e48a318aba548b9f15676fa41de123f7d1c99c55",
|
||||
},
|
||||
|
||||
// Data length: 7_070_038_086
|
||||
unmarshalTest{
|
||||
{
|
||||
state: "sha\x03$\x933u\nV\v\xe2\xf7:0!ʳ\xa4\x13\xd3 6\xdcBB\xb5\x19\xcd=\xc1h\xee=\xb4\x9c@ABCDE\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x01\xa5h8F",
|
||||
sum: "a280b08df5eba060fcd0eb3d29320bbc038afb95781661f91bbfd0a6fc9fdd6e",
|
||||
},
|
||||
|
||||
// Data length: 6_464_878_887
|
||||
unmarshalTest{
|
||||
{
|
||||
state: "sha\x03\x9f\x12\x87G\xf2\xdf<\x82\xa0\x11/*W\x02&IKWlh\x03\x95\xb1\xab\f\n\xf6Ze\xf9\x1d\x1b\x00\x01\x02\x03\x04\x05\x06\a\b\t\n\v\f\r\x0e\x0f\x10\x11\x12\x13\x14\x15\x16\x17\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f !\"#$%&\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x01\x81V9'",
|
||||
sum: "d2fffb762f105ab71e2d70069346c44c38c4fe183aad8cfcf5a76397c0457806",
|
||||
},
|
||||
|
||||
@ -847,11 +847,11 @@ type unmarshalTest struct {
|
||||
|
||||
var largeUnmarshalTests = []unmarshalTest{
|
||||
// Data length: 6_565_544_823
|
||||
unmarshalTest{
|
||||
{
|
||||
state: "sha\aηe\x0f\x0f\xe1r]#\aoJ!.{5B\xe4\x140\x91\xdd\x00a\xe1\xb3E&\xb9\xbb\aJ\x9f^\x9f\x03ͺD\x96H\x80\xb0X\x9d\xdeʸ\f\xf7:\xd5\xe6'\xb9\x93f\xddA\xf0~\xe1\x02\x14\x00\x01\x02\x03\x04\x05\x06\a\b\t\n\v\f\r\x0e\x0f\x10\x11\x12\x13\x14\x15\x16\x17\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f !\"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_`abcdefghijklmnopqrstuv\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x01\x87VCw",
|
||||
sum: "12d612357a1dbc74a28883dff79b83e7d2b881ae40d7a67fd7305490bc8a641cd1ce9ece598192080d6e9ac7e75d5988567a58a9812991299eb99a04ecb69523",
|
||||
},
|
||||
unmarshalTest{
|
||||
{
|
||||
state: "sha\a2\xd2\xdc\xf5\xd7\xe2\xf9\x97\xaa\xe7}Fϱ\xbc\x8e\xbf\x12h\x83Z\xa1\xc7\xf5p>bfS T\xea\xee\x1e\xa6Z\x9c\xa4ڶ\u0086\bn\xe47\x8fsGs3\xe0\xda\\\x9dqZ\xa5\xf6\xd0kM\xa1\xf2\x00\x01\x02\x03\x04\x05\x06\a\b\t\n\v\f\r\x0e\x0f\x10\x11\x12\x13\x14\x15\x16\x17\x18\x19\x1a\x1b\x1c\x1d\x1e\x1f !\"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\\]^_`abcdefghijklmnopqrstuv\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x01\xa7VCw",
|
||||
sum: "94a04b9a901254cd94ca0313557e4be3ab1ca86e920c1f3efdc22d361e9ae12be66bc6d6dc5db79a0a4aa6eca6f293c1e9095bbae127ae405f6c325478343299",
|
||||
},
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -369,7 +369,7 @@ func domainToReverseLabels(domain string) (reverseLabels []string, ok bool) {
|
||||
reverseLabels = append(reverseLabels, domain)
|
||||
domain = ""
|
||||
} else {
|
||||
reverseLabels = append(reverseLabels, domain[i+1:len(domain)])
|
||||
reverseLabels = append(reverseLabels, domain[i+1:])
|
||||
domain = domain[:i]
|
||||
}
|
||||
}
|
||||
|
||||
@ -439,7 +439,7 @@ func TestDriverArgs(t *testing.T) {
|
||||
0: {
|
||||
args: []interface{}{Valuer_V("foo")},
|
||||
want: []driver.NamedValue{
|
||||
driver.NamedValue{
|
||||
{
|
||||
Ordinal: 1,
|
||||
Value: "FOO",
|
||||
},
|
||||
@ -448,7 +448,7 @@ func TestDriverArgs(t *testing.T) {
|
||||
1: {
|
||||
args: []interface{}{nilValuerVPtr},
|
||||
want: []driver.NamedValue{
|
||||
driver.NamedValue{
|
||||
{
|
||||
Ordinal: 1,
|
||||
Value: nil,
|
||||
},
|
||||
@ -457,7 +457,7 @@ func TestDriverArgs(t *testing.T) {
|
||||
2: {
|
||||
args: []interface{}{nilValuerPPtr},
|
||||
want: []driver.NamedValue{
|
||||
driver.NamedValue{
|
||||
{
|
||||
Ordinal: 1,
|
||||
Value: "nil-to-str",
|
||||
},
|
||||
@ -466,7 +466,7 @@ func TestDriverArgs(t *testing.T) {
|
||||
3: {
|
||||
args: []interface{}{"plain-str"},
|
||||
want: []driver.NamedValue{
|
||||
driver.NamedValue{
|
||||
{
|
||||
Ordinal: 1,
|
||||
Value: "plain-str",
|
||||
},
|
||||
@ -475,7 +475,7 @@ func TestDriverArgs(t *testing.T) {
|
||||
4: {
|
||||
args: []interface{}{nilStrPtr},
|
||||
want: []driver.NamedValue{
|
||||
driver.NamedValue{
|
||||
{
|
||||
Ordinal: 1,
|
||||
Value: nil,
|
||||
},
|
||||
|
||||
@ -154,7 +154,7 @@ var fileTests = []fileTest{
|
||||
nil,
|
||||
nil,
|
||||
map[string][]Reloc{
|
||||
"__text": []Reloc{
|
||||
"__text": {
|
||||
{
|
||||
Addr: 0x1d,
|
||||
Type: uint8(GENERIC_RELOC_VANILLA),
|
||||
@ -189,7 +189,7 @@ var fileTests = []fileTest{
|
||||
nil,
|
||||
nil,
|
||||
map[string][]Reloc{
|
||||
"__text": []Reloc{
|
||||
"__text": {
|
||||
{
|
||||
Addr: 0x19,
|
||||
Type: uint8(X86_64_RELOC_BRANCH),
|
||||
@ -207,7 +207,7 @@ var fileTests = []fileTest{
|
||||
Value: 2,
|
||||
},
|
||||
},
|
||||
"__compact_unwind": []Reloc{
|
||||
"__compact_unwind": {
|
||||
{
|
||||
Addr: 0x0,
|
||||
Type: uint8(X86_64_RELOC_UNSIGNED),
|
||||
|
||||
@ -539,52 +539,52 @@ func TestBufferedDecodingSameError(t *testing.T) {
|
||||
// NBSWY3DPO5XXE3DE == helloworld
|
||||
// Test with "ZZ" as extra input
|
||||
{"helloworld", [][]string{
|
||||
[]string{"NBSW", "Y3DP", "O5XX", "E3DE", "ZZ"},
|
||||
[]string{"NBSWY3DPO5XXE3DE", "ZZ"},
|
||||
[]string{"NBSWY3DPO5XXE3DEZZ"},
|
||||
[]string{"NBS", "WY3", "DPO", "5XX", "E3D", "EZZ"},
|
||||
[]string{"NBSWY3DPO5XXE3", "DEZZ"},
|
||||
{"NBSW", "Y3DP", "O5XX", "E3DE", "ZZ"},
|
||||
{"NBSWY3DPO5XXE3DE", "ZZ"},
|
||||
{"NBSWY3DPO5XXE3DEZZ"},
|
||||
{"NBS", "WY3", "DPO", "5XX", "E3D", "EZZ"},
|
||||
{"NBSWY3DPO5XXE3", "DEZZ"},
|
||||
}, io.ErrUnexpectedEOF},
|
||||
|
||||
// Test with "ZZY" as extra input
|
||||
{"helloworld", [][]string{
|
||||
[]string{"NBSW", "Y3DP", "O5XX", "E3DE", "ZZY"},
|
||||
[]string{"NBSWY3DPO5XXE3DE", "ZZY"},
|
||||
[]string{"NBSWY3DPO5XXE3DEZZY"},
|
||||
[]string{"NBS", "WY3", "DPO", "5XX", "E3D", "EZZY"},
|
||||
[]string{"NBSWY3DPO5XXE3", "DEZZY"},
|
||||
{"NBSW", "Y3DP", "O5XX", "E3DE", "ZZY"},
|
||||
{"NBSWY3DPO5XXE3DE", "ZZY"},
|
||||
{"NBSWY3DPO5XXE3DEZZY"},
|
||||
{"NBS", "WY3", "DPO", "5XX", "E3D", "EZZY"},
|
||||
{"NBSWY3DPO5XXE3", "DEZZY"},
|
||||
}, io.ErrUnexpectedEOF},
|
||||
|
||||
// Normal case, this is valid input
|
||||
{"helloworld", [][]string{
|
||||
[]string{"NBSW", "Y3DP", "O5XX", "E3DE"},
|
||||
[]string{"NBSWY3DPO5XXE3DE"},
|
||||
[]string{"NBS", "WY3", "DPO", "5XX", "E3D", "E"},
|
||||
[]string{"NBSWY3DPO5XXE3", "DE"},
|
||||
{"NBSW", "Y3DP", "O5XX", "E3DE"},
|
||||
{"NBSWY3DPO5XXE3DE"},
|
||||
{"NBS", "WY3", "DPO", "5XX", "E3D", "E"},
|
||||
{"NBSWY3DPO5XXE3", "DE"},
|
||||
}, nil},
|
||||
|
||||
// MZXW6YTB = fooba
|
||||
{"fooba", [][]string{
|
||||
[]string{"MZXW6YTBZZ"},
|
||||
[]string{"MZXW6YTBZ", "Z"},
|
||||
[]string{"MZXW6YTB", "ZZ"},
|
||||
[]string{"MZXW6YT", "BZZ"},
|
||||
[]string{"MZXW6Y", "TBZZ"},
|
||||
[]string{"MZXW6Y", "TB", "ZZ"},
|
||||
[]string{"MZXW6", "YTBZZ"},
|
||||
[]string{"MZXW6", "YTB", "ZZ"},
|
||||
[]string{"MZXW6", "YT", "BZZ"},
|
||||
{"MZXW6YTBZZ"},
|
||||
{"MZXW6YTBZ", "Z"},
|
||||
{"MZXW6YTB", "ZZ"},
|
||||
{"MZXW6YT", "BZZ"},
|
||||
{"MZXW6Y", "TBZZ"},
|
||||
{"MZXW6Y", "TB", "ZZ"},
|
||||
{"MZXW6", "YTBZZ"},
|
||||
{"MZXW6", "YTB", "ZZ"},
|
||||
{"MZXW6", "YT", "BZZ"},
|
||||
}, io.ErrUnexpectedEOF},
|
||||
|
||||
// Normal case, this is valid input
|
||||
{"fooba", [][]string{
|
||||
[]string{"MZXW6YTB"},
|
||||
[]string{"MZXW6YT", "B"},
|
||||
[]string{"MZXW6Y", "TB"},
|
||||
[]string{"MZXW6", "YTB"},
|
||||
[]string{"MZXW6", "YT", "B"},
|
||||
[]string{"MZXW", "6YTB"},
|
||||
[]string{"MZXW", "6Y", "TB"},
|
||||
{"MZXW6YTB"},
|
||||
{"MZXW6YT", "B"},
|
||||
{"MZXW6Y", "TB"},
|
||||
{"MZXW6", "YTB"},
|
||||
{"MZXW6", "YT", "B"},
|
||||
{"MZXW", "6YTB"},
|
||||
{"MZXW", "6Y", "TB"},
|
||||
}, nil},
|
||||
}
|
||||
|
||||
|
||||
@ -132,12 +132,12 @@ func ExamplePutVarint() {
|
||||
|
||||
func ExampleUvarint() {
|
||||
inputs := [][]byte{
|
||||
[]byte{0x01},
|
||||
[]byte{0x02},
|
||||
[]byte{0x7f},
|
||||
[]byte{0x80, 0x01},
|
||||
[]byte{0xff, 0x01},
|
||||
[]byte{0x80, 0x02},
|
||||
{0x01},
|
||||
{0x02},
|
||||
{0x7f},
|
||||
{0x80, 0x01},
|
||||
{0xff, 0x01},
|
||||
{0x80, 0x02},
|
||||
}
|
||||
for _, b := range inputs {
|
||||
x, n := binary.Uvarint(b)
|
||||
@ -157,15 +157,15 @@ func ExampleUvarint() {
|
||||
|
||||
func ExampleVarint() {
|
||||
inputs := [][]byte{
|
||||
[]byte{0x81, 0x01},
|
||||
[]byte{0x7f},
|
||||
[]byte{0x03},
|
||||
[]byte{0x01},
|
||||
[]byte{0x00},
|
||||
[]byte{0x02},
|
||||
[]byte{0x04},
|
||||
[]byte{0x7e},
|
||||
[]byte{0x80, 0x01},
|
||||
{0x81, 0x01},
|
||||
{0x7f},
|
||||
{0x03},
|
||||
{0x01},
|
||||
{0x00},
|
||||
{0x02},
|
||||
{0x04},
|
||||
{0x7e},
|
||||
{0x80, 0x01},
|
||||
}
|
||||
for _, b := range inputs {
|
||||
x, n := binary.Varint(b)
|
||||
|
||||
@ -25,8 +25,8 @@ var archTest = []archiveTest{
|
||||
{"printhello.o", 860},
|
||||
},
|
||||
[]FileHeader{
|
||||
FileHeader{U64_TOCMAGIC},
|
||||
FileHeader{U64_TOCMAGIC},
|
||||
{U64_TOCMAGIC},
|
||||
{U64_TOCMAGIC},
|
||||
},
|
||||
},
|
||||
{
|
||||
|
||||
@ -4430,37 +4430,37 @@ func TestStructOfFieldName(t *testing.T) {
|
||||
// invalid field name "1nvalid"
|
||||
shouldPanic(func() {
|
||||
StructOf([]StructField{
|
||||
StructField{Name: "valid", Type: TypeOf("")},
|
||||
StructField{Name: "1nvalid", Type: TypeOf("")},
|
||||
{Name: "valid", Type: TypeOf("")},
|
||||
{Name: "1nvalid", Type: TypeOf("")},
|
||||
})
|
||||
})
|
||||
|
||||
// invalid field name "+"
|
||||
shouldPanic(func() {
|
||||
StructOf([]StructField{
|
||||
StructField{Name: "val1d", Type: TypeOf("")},
|
||||
StructField{Name: "+", Type: TypeOf("")},
|
||||
{Name: "val1d", Type: TypeOf("")},
|
||||
{Name: "+", Type: TypeOf("")},
|
||||
})
|
||||
})
|
||||
|
||||
// no field name
|
||||
shouldPanic(func() {
|
||||
StructOf([]StructField{
|
||||
StructField{Name: "", Type: TypeOf("")},
|
||||
{Name: "", Type: TypeOf("")},
|
||||
})
|
||||
})
|
||||
|
||||
// verify creation of a struct with valid struct fields
|
||||
validFields := []StructField{
|
||||
StructField{
|
||||
{
|
||||
Name: "φ",
|
||||
Type: TypeOf(""),
|
||||
},
|
||||
StructField{
|
||||
{
|
||||
Name: "ValidName",
|
||||
Type: TypeOf(""),
|
||||
},
|
||||
StructField{
|
||||
{
|
||||
Name: "Val1dNam5",
|
||||
Type: TypeOf(""),
|
||||
},
|
||||
@ -4477,21 +4477,21 @@ func TestStructOfFieldName(t *testing.T) {
|
||||
func TestStructOf(t *testing.T) {
|
||||
// check construction and use of type not in binary
|
||||
fields := []StructField{
|
||||
StructField{
|
||||
{
|
||||
Name: "S",
|
||||
Tag: "s",
|
||||
Type: TypeOf(""),
|
||||
},
|
||||
StructField{
|
||||
{
|
||||
Name: "X",
|
||||
Tag: "x",
|
||||
Type: TypeOf(byte(0)),
|
||||
},
|
||||
StructField{
|
||||
{
|
||||
Name: "Y",
|
||||
Type: TypeOf(uint64(0)),
|
||||
},
|
||||
StructField{
|
||||
{
|
||||
Name: "Z",
|
||||
Type: TypeOf([3]uint16{}),
|
||||
},
|
||||
@ -4573,20 +4573,20 @@ func TestStructOf(t *testing.T) {
|
||||
// check duplicate names
|
||||
shouldPanic(func() {
|
||||
StructOf([]StructField{
|
||||
StructField{Name: "string", Type: TypeOf("")},
|
||||
StructField{Name: "string", Type: TypeOf("")},
|
||||
{Name: "string", Type: TypeOf("")},
|
||||
{Name: "string", Type: TypeOf("")},
|
||||
})
|
||||
})
|
||||
shouldPanic(func() {
|
||||
StructOf([]StructField{
|
||||
StructField{Type: TypeOf("")},
|
||||
StructField{Name: "string", Type: TypeOf("")},
|
||||
{Type: TypeOf("")},
|
||||
{Name: "string", Type: TypeOf("")},
|
||||
})
|
||||
})
|
||||
shouldPanic(func() {
|
||||
StructOf([]StructField{
|
||||
StructField{Type: TypeOf("")},
|
||||
StructField{Type: TypeOf("")},
|
||||
{Type: TypeOf("")},
|
||||
{Type: TypeOf("")},
|
||||
})
|
||||
})
|
||||
// check that type already in binary is found
|
||||
@ -4596,7 +4596,7 @@ func TestStructOf(t *testing.T) {
|
||||
type structFieldType interface{}
|
||||
checkSameType(t,
|
||||
StructOf([]StructField{
|
||||
StructField{
|
||||
{
|
||||
Name: "F",
|
||||
Type: TypeOf((*structFieldType)(nil)).Elem(),
|
||||
},
|
||||
|
||||
Loading…
Reference in New Issue
Block a user