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internal/cpu: fix cpu cacheLineSize for loong64

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We choose 64 because the L1 Dcache of Loongson 3A5000 CPU is
4-way 256-line 64-byte-per-line.

Change-Id: Ifb9a9f993dd6f75b5adb4ff6e4d93e945b1b2a98
Reviewed-on: https://go-review.googlesource.com/c/go/+/408854
Run-TryBot: Ian Lance Taylor <iant@google.com>
TryBot-Result: Gopher Robot <gobot@golang.org>
Auto-Submit: Ian Lance Taylor <iant@google.com>
Reviewed-by: Alex Rakoczy <alex@golang.org>
Reviewed-by: Ian Lance Taylor <iant@google.com>
This commit is contained in:
Guoqi Chen 2022-05-26 19:38:02 +08:00 committed by Gopher Robot
parent f8c26a59a4
commit ec9258029e
1 changed files with 3 additions and 1 deletions
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4
src/internal/cpu/cpu_loong64.go
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@ -6,6 +6,8 @@
package cpu
const CacheLinePadSize = 32
// CacheLinePadSize is used to prevent false sharing of cache lines.
// We choose 64 because Loongson 3A5000 the L1 Dcache is 4-way 256-line 64-byte-per-line.
const CacheLinePadSize = 64
func doinit() {}