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cmd/compile/internal/ssa{,/gen}: define rules and operation on loong64
The rules and operation definition is used to generate rewrite functions and OpKind type constant. Contributors to the loong64 port are: Weining Lu <luweining@loongson.cn> Lei Wang <wanglei@loongson.cn> Lingqin Gong <gonglingqin@loongson.cn> Xiaolin Zhao <zhaoxiaolin@loongson.cn> Meidan Li <limeidan@loongson.cn> Xiaojuan Zhai <zhaixiaojuan@loongson.cn> Qiyuan Pu <puqiyuan@loongson.cn> Guoqi Chen <chenguoqi@loongson.cn> This port has been updated to Go 1.15.6: https://github.com/loongson/go Updates #46229 Change-Id: Ia362ed7ba5d84046697aadbc8d6d4cbe495f6076 Reviewed-on: https://go-review.googlesource.com/c/go/+/367039 Run-TryBot: Ian Lance Taylor <iant@google.com> TryBot-Result: Gopher Robot <gobot@golang.org> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Ian Lance Taylor <iant@google.com> Auto-Submit: Ian Lance Taylor <iant@google.com>
This commit is contained in:
Xiaodong Liu
Gopher Robot
parent
f2cd6d60ae
commit
ec5bdefd0a
675
src/cmd/compile/internal/ssa/gen/LOONG64.rules
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src/cmd/compile/internal/ssa/gen/LOONG64.rules
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// Copyright 2022 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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(Add(Ptr|64|32|16|8) ...) => (ADDV ...)
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(Add(32|64)F ...) => (ADD(F|D) ...)
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(Sub(Ptr|64|32|16|8) ...) => (SUBV ...)
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(Sub(32|64)F ...) => (SUB(F|D) ...)
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(Mul(64|32|16|8) x y) => (Select1 (MULVU x y))
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(Mul(32|64)F ...) => (MUL(F|D) ...)
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(Mul64uhilo ...) => (MULVU ...)
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(Select0 (Mul64uover x y)) => (Select1 <typ.UInt64> (MULVU x y))
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(Select1 (Mul64uover x y)) => (SGTU <typ.Bool> (Select0 <typ.UInt64> (MULVU x y)) (MOVVconst <typ.UInt64> [0]))
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(Hmul64 x y) => (Select0 (MULV x y))
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(Hmul64u x y) => (Select0 (MULVU x y))
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(Hmul32 x y) => (SRAVconst (Select1 <typ.Int64> (MULV (SignExt32to64 x) (SignExt32to64 y))) [32])
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(Hmul32u x y) => (SRLVconst (Select1 <typ.UInt64> (MULVU (ZeroExt32to64 x) (ZeroExt32to64 y))) [32])
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(Div64 x y) => (Select1 (DIVV x y))
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(Div64u x y) => (Select1 (DIVVU x y))
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(Div32 x y) => (Select1 (DIVV (SignExt32to64 x) (SignExt32to64 y)))
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(Div32u x y) => (Select1 (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y)))
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(Div16 x y) => (Select1 (DIVV (SignExt16to64 x) (SignExt16to64 y)))
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(Div16u x y) => (Select1 (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y)))
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(Div8 x y) => (Select1 (DIVV (SignExt8to64 x) (SignExt8to64 y)))
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(Div8u x y) => (Select1 (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y)))
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(Div(32|64)F ...) => (DIV(F|D) ...)
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(Mod64 x y) => (Select0 (DIVV x y))
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(Mod64u x y) => (Select0 (DIVVU x y))
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(Mod32 x y) => (Select0 (DIVV (SignExt32to64 x) (SignExt32to64 y)))
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(Mod32u x y) => (Select0 (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y)))
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(Mod16 x y) => (Select0 (DIVV (SignExt16to64 x) (SignExt16to64 y)))
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(Mod16u x y) => (Select0 (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y)))
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(Mod8 x y) => (Select0 (DIVV (SignExt8to64 x) (SignExt8to64 y)))
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(Mod8u x y) => (Select0 (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y)))
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// (x + y) / 2 with x>=y => (x - y) / 2 + y
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(Avg64u <t> x y) => (ADDV (SRLVconst <t> (SUBV <t> x y) [1]) y)
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(And(64|32|16|8) ...) => (AND ...)
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(Or(64|32|16|8) ...) => (OR ...)
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(Xor(64|32|16|8) ...) => (XOR ...)
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// shifts
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// hardware instruction uses only the low 6 bits of the shift
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// we compare to 64 to ensure Go semantics for large shifts
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(Lsh64x64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y))
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(Lsh64x32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y)))
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(Lsh64x16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y)))
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(Lsh64x8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y)))
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(Lsh32x64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y))
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(Lsh32x32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y)))
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(Lsh32x16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y)))
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(Lsh32x8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y)))
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(Lsh16x64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y))
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(Lsh16x32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y)))
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(Lsh16x16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y)))
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(Lsh16x8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y)))
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(Lsh8x64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SLLV <t> x y))
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(Lsh8x32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y)))
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(Lsh8x16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y)))
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(Lsh8x8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SLLV <t> x (ZeroExt8to64 y)))
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(Rsh64Ux64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> x y))
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(Rsh64Ux32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> x (ZeroExt32to64 y)))
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(Rsh64Ux16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> x (ZeroExt16to64 y)))
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(Rsh64Ux8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> x (ZeroExt8to64 y)))
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(Rsh32Ux64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> (ZeroExt32to64 x) y))
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(Rsh32Ux32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> (ZeroExt32to64 x) (ZeroExt32to64 y)))
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(Rsh32Ux16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> (ZeroExt32to64 x) (ZeroExt16to64 y)))
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(Rsh32Ux8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> (ZeroExt32to64 x) (ZeroExt8to64 y)))
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(Rsh16Ux64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> (ZeroExt16to64 x) y))
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(Rsh16Ux32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> (ZeroExt16to64 x) (ZeroExt32to64 y)))
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(Rsh16Ux16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> (ZeroExt16to64 x) (ZeroExt16to64 y)))
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(Rsh16Ux8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> (ZeroExt16to64 x) (ZeroExt8to64 y)))
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(Rsh8Ux64 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) y)) (SRLV <t> (ZeroExt8to64 x) y))
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(Rsh8Ux32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SRLV <t> (ZeroExt8to64 x) (ZeroExt32to64 y)))
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(Rsh8Ux16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SRLV <t> (ZeroExt8to64 x) (ZeroExt16to64 y)))
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(Rsh8Ux8 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64 y))) (SRLV <t> (ZeroExt8to64 x) (ZeroExt8to64 y)))
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(Rsh64x64 <t> x y) => (SRAV x (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y))
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(Rsh64x32 <t> x y) => (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y)))
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(Rsh64x16 <t> x y) => (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y)))
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(Rsh64x8 <t> x y) => (SRAV x (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y)))
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(Rsh32x64 <t> x y) => (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y))
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(Rsh32x32 <t> x y) => (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y)))
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(Rsh32x16 <t> x y) => (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y)))
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(Rsh32x8 <t> x y) => (SRAV (SignExt32to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y)))
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(Rsh16x64 <t> x y) => (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y))
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(Rsh16x32 <t> x y) => (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y)))
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(Rsh16x16 <t> x y) => (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y)))
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(Rsh16x8 <t> x y) => (SRAV (SignExt16to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y)))
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(Rsh8x64 <t> x y) => (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU y (MOVVconst <typ.UInt64> [63]))) y))
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(Rsh8x32 <t> x y) => (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt32to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt32to64 y)))
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(Rsh8x16 <t> x y) => (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt16to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt16to64 y)))
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(Rsh8x8 <t> x y) => (SRAV (SignExt8to64 x) (OR <t> (NEGV <t> (SGTU (ZeroExt8to64 y) (MOVVconst <typ.UInt64> [63]))) (ZeroExt8to64 y)))
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// rotates
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(RotateLeft8 <t> x (MOVVconst [c])) => (Or8 (Lsh8x64 <t> x (MOVVconst [c&7])) (Rsh8Ux64 <t> x (MOVVconst [-c&7])))
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(RotateLeft16 <t> x (MOVVconst [c])) => (Or16 (Lsh16x64 <t> x (MOVVconst [c&15])) (Rsh16Ux64 <t> x (MOVVconst [-c&15])))
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(RotateLeft32 <t> x (MOVVconst [c])) => (Or32 (Lsh32x64 <t> x (MOVVconst [c&31])) (Rsh32Ux64 <t> x (MOVVconst [-c&31])))
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(RotateLeft64 <t> x (MOVVconst [c])) => (Or64 (Lsh64x64 <t> x (MOVVconst [c&63])) (Rsh64Ux64 <t> x (MOVVconst [-c&63])))
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// unary ops
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(Neg(64|32|16|8) ...) => (NEGV ...)
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(Neg(32|64)F ...) => (NEG(F|D) ...)
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(Com(64|32|16|8) x) => (NOR (MOVVconst [0]) x)
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(Sqrt ...) => (SQRTD ...)
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(Sqrt32 ...) => (SQRTF ...)
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// boolean ops -- booleans are represented with 0=false, 1=true
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(AndB ...) => (AND ...)
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(OrB ...) => (OR ...)
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(EqB x y) => (XOR (MOVVconst [1]) (XOR <typ.Bool> x y))
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(NeqB ...) => (XOR ...)
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(Not x) => (XORconst [1] x)
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// constants
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(Const(64|32|16|8) [val]) => (MOVVconst [int64(val)])
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(Const(32|64)F [val]) => (MOV(F|D)const [float64(val)])
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(ConstNil) => (MOVVconst [0])
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(ConstBool [t]) => (MOVVconst [int64(b2i(t))])
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(Slicemask <t> x) => (SRAVconst (NEGV <t> x) [63])
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// truncations
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// Because we ignore high parts of registers, truncates are just copies.
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(Trunc16to8 ...) => (Copy ...)
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(Trunc32to8 ...) => (Copy ...)
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(Trunc32to16 ...) => (Copy ...)
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(Trunc64to8 ...) => (Copy ...)
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(Trunc64to16 ...) => (Copy ...)
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(Trunc64to32 ...) => (Copy ...)
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// Zero-/Sign-extensions
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(ZeroExt8to16 ...) => (MOVBUreg ...)
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(ZeroExt8to32 ...) => (MOVBUreg ...)
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(ZeroExt16to32 ...) => (MOVHUreg ...)
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(ZeroExt8to64 ...) => (MOVBUreg ...)
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(ZeroExt16to64 ...) => (MOVHUreg ...)
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(ZeroExt32to64 ...) => (MOVWUreg ...)
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(SignExt8to16 ...) => (MOVBreg ...)
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(SignExt8to32 ...) => (MOVBreg ...)
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(SignExt16to32 ...) => (MOVHreg ...)
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(SignExt8to64 ...) => (MOVBreg ...)
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(SignExt16to64 ...) => (MOVHreg ...)
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(SignExt32to64 ...) => (MOVWreg ...)
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// float <=> int conversion
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(Cvt32to32F ...) => (MOVWF ...)
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(Cvt32to64F ...) => (MOVWD ...)
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(Cvt64to32F ...) => (MOVVF ...)
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(Cvt64to64F ...) => (MOVVD ...)
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(Cvt32Fto32 ...) => (TRUNCFW ...)
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(Cvt64Fto32 ...) => (TRUNCDW ...)
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(Cvt32Fto64 ...) => (TRUNCFV ...)
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(Cvt64Fto64 ...) => (TRUNCDV ...)
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(Cvt32Fto64F ...) => (MOVFD ...)
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(Cvt64Fto32F ...) => (MOVDF ...)
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(CvtBoolToUint8 ...) => (Copy ...)
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(Round(32|64)F ...) => (Copy ...)
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// comparisons
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(Eq8 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt8to64 x) (ZeroExt8to64 y)))
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(Eq16 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt16to64 x) (ZeroExt16to64 y)))
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(Eq32 x y) => (SGTU (MOVVconst [1]) (XOR (ZeroExt32to64 x) (ZeroExt32to64 y)))
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(Eq64 x y) => (SGTU (MOVVconst [1]) (XOR x y))
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(EqPtr x y) => (SGTU (MOVVconst [1]) (XOR x y))
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(Eq(32|64)F x y) => (FPFlagTrue (CMPEQ(F|D) x y))
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(Neq8 x y) => (SGTU (XOR (ZeroExt8to64 x) (ZeroExt8to64 y)) (MOVVconst [0]))
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(Neq16 x y) => (SGTU (XOR (ZeroExt16to32 x) (ZeroExt16to64 y)) (MOVVconst [0]))
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(Neq32 x y) => (SGTU (XOR (ZeroExt32to64 x) (ZeroExt32to64 y)) (MOVVconst [0]))
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(Neq64 x y) => (SGTU (XOR x y) (MOVVconst [0]))
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(NeqPtr x y) => (SGTU (XOR x y) (MOVVconst [0]))
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(Neq(32|64)F x y) => (FPFlagFalse (CMPEQ(F|D) x y))
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(Less8 x y) => (SGT (SignExt8to64 y) (SignExt8to64 x))
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(Less16 x y) => (SGT (SignExt16to64 y) (SignExt16to64 x))
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(Less32 x y) => (SGT (SignExt32to64 y) (SignExt32to64 x))
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(Less64 x y) => (SGT y x)
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(Less(32|64)F x y) => (FPFlagTrue (CMPGT(F|D) y x)) // reverse operands to work around NaN
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(Less8U x y) => (SGTU (ZeroExt8to64 y) (ZeroExt8to64 x))
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(Less16U x y) => (SGTU (ZeroExt16to64 y) (ZeroExt16to64 x))
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(Less32U x y) => (SGTU (ZeroExt32to64 y) (ZeroExt32to64 x))
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(Less64U x y) => (SGTU y x)
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(Leq8 x y) => (XOR (MOVVconst [1]) (SGT (SignExt8to64 x) (SignExt8to64 y)))
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(Leq16 x y) => (XOR (MOVVconst [1]) (SGT (SignExt16to64 x) (SignExt16to64 y)))
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(Leq32 x y) => (XOR (MOVVconst [1]) (SGT (SignExt32to64 x) (SignExt32to64 y)))
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(Leq64 x y) => (XOR (MOVVconst [1]) (SGT x y))
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(Leq(32|64)F x y) => (FPFlagTrue (CMPGE(F|D) y x)) // reverse operands to work around NaN
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(Leq8U x y) => (XOR (MOVVconst [1]) (SGTU (ZeroExt8to64 x) (ZeroExt8to64 y)))
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(Leq16U x y) => (XOR (MOVVconst [1]) (SGTU (ZeroExt16to64 x) (ZeroExt16to64 y)))
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(Leq32U x y) => (XOR (MOVVconst [1]) (SGTU (ZeroExt32to64 x) (ZeroExt32to64 y)))
|
||||
(Leq64U x y) => (XOR (MOVVconst [1]) (SGTU x y))
|
||||
|
||||
(OffPtr [off] ptr:(SP)) => (MOVVaddr [int32(off)] ptr)
|
||||
(OffPtr [off] ptr) => (ADDVconst [off] ptr)
|
||||
|
||||
(Addr {sym} base) => (MOVVaddr {sym} base)
|
||||
(LocalAddr {sym} base _) => (MOVVaddr {sym} base)
|
||||
|
||||
// loads
|
||||
(Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem)
|
||||
(Load <t> ptr mem) && (is8BitInt(t) && isSigned(t)) => (MOVBload ptr mem)
|
||||
(Load <t> ptr mem) && (is8BitInt(t) && !isSigned(t)) => (MOVBUload ptr mem)
|
||||
(Load <t> ptr mem) && (is16BitInt(t) && isSigned(t)) => (MOVHload ptr mem)
|
||||
(Load <t> ptr mem) && (is16BitInt(t) && !isSigned(t)) => (MOVHUload ptr mem)
|
||||
(Load <t> ptr mem) && (is32BitInt(t) && isSigned(t)) => (MOVWload ptr mem)
|
||||
(Load <t> ptr mem) && (is32BitInt(t) && !isSigned(t)) => (MOVWUload ptr mem)
|
||||
(Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVVload ptr mem)
|
||||
(Load <t> ptr mem) && is32BitFloat(t) => (MOVFload ptr mem)
|
||||
(Load <t> ptr mem) && is64BitFloat(t) => (MOVDload ptr mem)
|
||||
|
||||
// stores
|
||||
(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
|
||||
(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
|
||||
(Store {t} ptr val mem) && t.Size() == 4 && !is32BitFloat(val.Type) => (MOVWstore ptr val mem)
|
||||
(Store {t} ptr val mem) && t.Size() == 8 && !is64BitFloat(val.Type) => (MOVVstore ptr val mem)
|
||||
(Store {t} ptr val mem) && t.Size() == 4 && is32BitFloat(val.Type) => (MOVFstore ptr val mem)
|
||||
(Store {t} ptr val mem) && t.Size() == 8 && is64BitFloat(val.Type) => (MOVDstore ptr val mem)
|
||||
|
||||
// zeroing
|
||||
(Zero [0] _ mem) => mem
|
||||
(Zero [1] ptr mem) => (MOVBstore ptr (MOVVconst [0]) mem)
|
||||
(Zero [2] {t} ptr mem) && t.Alignment()%2 == 0 =>
|
||||
(MOVHstore ptr (MOVVconst [0]) mem)
|
||||
(Zero [2] ptr mem) =>
|
||||
(MOVBstore [1] ptr (MOVVconst [0])
|
||||
(MOVBstore [0] ptr (MOVVconst [0]) mem))
|
||||
(Zero [4] {t} ptr mem) && t.Alignment()%4 == 0 =>
|
||||
(MOVWstore ptr (MOVVconst [0]) mem)
|
||||
(Zero [4] {t} ptr mem) && t.Alignment()%2 == 0 =>
|
||||
(MOVHstore [2] ptr (MOVVconst [0])
|
||||
(MOVHstore [0] ptr (MOVVconst [0]) mem))
|
||||
(Zero [4] ptr mem) =>
|
||||
(MOVBstore [3] ptr (MOVVconst [0])
|
||||
(MOVBstore [2] ptr (MOVVconst [0])
|
||||
(MOVBstore [1] ptr (MOVVconst [0])
|
||||
(MOVBstore [0] ptr (MOVVconst [0]) mem))))
|
||||
(Zero [8] {t} ptr mem) && t.Alignment()%8 == 0 =>
|
||||
(MOVVstore ptr (MOVVconst [0]) mem)
|
||||
(Zero [8] {t} ptr mem) && t.Alignment()%4 == 0 =>
|
||||
(MOVWstore [4] ptr (MOVVconst [0])
|
||||
(MOVWstore [0] ptr (MOVVconst [0]) mem))
|
||||
(Zero [8] {t} ptr mem) && t.Alignment()%2 == 0 =>
|
||||
(MOVHstore [6] ptr (MOVVconst [0])
|
||||
(MOVHstore [4] ptr (MOVVconst [0])
|
||||
(MOVHstore [2] ptr (MOVVconst [0])
|
||||
(MOVHstore [0] ptr (MOVVconst [0]) mem))))
|
||||
|
||||
(Zero [3] ptr mem) =>
|
||||
(MOVBstore [2] ptr (MOVVconst [0])
|
||||
(MOVBstore [1] ptr (MOVVconst [0])
|
||||
(MOVBstore [0] ptr (MOVVconst [0]) mem)))
|
||||
(Zero [6] {t} ptr mem) && t.Alignment()%2 == 0 =>
|
||||
(MOVHstore [4] ptr (MOVVconst [0])
|
||||
(MOVHstore [2] ptr (MOVVconst [0])
|
||||
(MOVHstore [0] ptr (MOVVconst [0]) mem)))
|
||||
(Zero [12] {t} ptr mem) && t.Alignment()%4 == 0 =>
|
||||
(MOVWstore [8] ptr (MOVVconst [0])
|
||||
(MOVWstore [4] ptr (MOVVconst [0])
|
||||
(MOVWstore [0] ptr (MOVVconst [0]) mem)))
|
||||
(Zero [16] {t} ptr mem) && t.Alignment()%8 == 0 =>
|
||||
(MOVVstore [8] ptr (MOVVconst [0])
|
||||
(MOVVstore [0] ptr (MOVVconst [0]) mem))
|
||||
(Zero [24] {t} ptr mem) && t.Alignment()%8 == 0 =>
|
||||
(MOVVstore [16] ptr (MOVVconst [0])
|
||||
(MOVVstore [8] ptr (MOVVconst [0])
|
||||
(MOVVstore [0] ptr (MOVVconst [0]) mem)))
|
||||
|
||||
// medium zeroing uses a duff device
|
||||
// 8, and 128 are magic constants, see runtime/mkduff.go
|
||||
(Zero [s] {t} ptr mem)
|
||||
&& s%8 == 0 && s > 24 && s <= 8*128
|
||||
&& t.Alignment()%8 == 0 && !config.noDuffDevice =>
|
||||
(DUFFZERO [8 * (128 - s/8)] ptr mem)
|
||||
|
||||
// large or unaligned zeroing uses a loop
|
||||
(Zero [s] {t} ptr mem)
|
||||
&& (s > 8*128 || config.noDuffDevice) || t.Alignment()%8 != 0 =>
|
||||
(LoweredZero [t.Alignment()]
|
||||
ptr
|
||||
(ADDVconst <ptr.Type> ptr [s-moveSize(t.Alignment(), config)])
|
||||
mem)
|
||||
|
||||
// moves
|
||||
(Move [0] _ _ mem) => mem
|
||||
(Move [1] dst src mem) => (MOVBstore dst (MOVBload src mem) mem)
|
||||
(Move [2] {t} dst src mem) && t.Alignment()%2 == 0 =>
|
||||
(MOVHstore dst (MOVHload src mem) mem)
|
||||
(Move [2] dst src mem) =>
|
||||
(MOVBstore [1] dst (MOVBload [1] src mem)
|
||||
(MOVBstore dst (MOVBload src mem) mem))
|
||||
(Move [4] {t} dst src mem) && t.Alignment()%4 == 0 =>
|
||||
(MOVWstore dst (MOVWload src mem) mem)
|
||||
(Move [4] {t} dst src mem) && t.Alignment()%2 == 0 =>
|
||||
(MOVHstore [2] dst (MOVHload [2] src mem)
|
||||
(MOVHstore dst (MOVHload src mem) mem))
|
||||
(Move [4] dst src mem) =>
|
||||
(MOVBstore [3] dst (MOVBload [3] src mem)
|
||||
(MOVBstore [2] dst (MOVBload [2] src mem)
|
||||
(MOVBstore [1] dst (MOVBload [1] src mem)
|
||||
(MOVBstore dst (MOVBload src mem) mem))))
|
||||
(Move [8] {t} dst src mem) && t.Alignment()%8 == 0 =>
|
||||
(MOVVstore dst (MOVVload src mem) mem)
|
||||
(Move [8] {t} dst src mem) && t.Alignment()%4 == 0 =>
|
||||
(MOVWstore [4] dst (MOVWload [4] src mem)
|
||||
(MOVWstore dst (MOVWload src mem) mem))
|
||||
(Move [8] {t} dst src mem) && t.Alignment()%2 == 0 =>
|
||||
(MOVHstore [6] dst (MOVHload [6] src mem)
|
||||
(MOVHstore [4] dst (MOVHload [4] src mem)
|
||||
(MOVHstore [2] dst (MOVHload [2] src mem)
|
||||
(MOVHstore dst (MOVHload src mem) mem))))
|
||||
|
||||
(Move [3] dst src mem) =>
|
||||
(MOVBstore [2] dst (MOVBload [2] src mem)
|
||||
(MOVBstore [1] dst (MOVBload [1] src mem)
|
||||
(MOVBstore dst (MOVBload src mem) mem)))
|
||||
(Move [6] {t} dst src mem) && t.Alignment()%2 == 0 =>
|
||||
(MOVHstore [4] dst (MOVHload [4] src mem)
|
||||
(MOVHstore [2] dst (MOVHload [2] src mem)
|
||||
(MOVHstore dst (MOVHload src mem) mem)))
|
||||
(Move [12] {t} dst src mem) && t.Alignment()%4 == 0 =>
|
||||
(MOVWstore [8] dst (MOVWload [8] src mem)
|
||||
(MOVWstore [4] dst (MOVWload [4] src mem)
|
||||
(MOVWstore dst (MOVWload src mem) mem)))
|
||||
(Move [16] {t} dst src mem) && t.Alignment()%8 == 0 =>
|
||||
(MOVVstore [8] dst (MOVVload [8] src mem)
|
||||
(MOVVstore dst (MOVVload src mem) mem))
|
||||
(Move [24] {t} dst src mem) && t.Alignment()%8 == 0 =>
|
||||
(MOVVstore [16] dst (MOVVload [16] src mem)
|
||||
(MOVVstore [8] dst (MOVVload [8] src mem)
|
||||
(MOVVstore dst (MOVVload src mem) mem)))
|
||||
|
||||
// medium move uses a duff device
|
||||
(Move [s] {t} dst src mem)
|
||||
&& s%8 == 0 && s >= 24 && s <= 8*128 && t.Alignment()%8 == 0
|
||||
&& !config.noDuffDevice && logLargeCopy(v, s) =>
|
||||
(DUFFCOPY [16 * (128 - s/8)] dst src mem)
|
||||
// 16 and 128 are magic constants. 16 is the number of bytes to encode:
|
||||
// MOVV (R1), R23
|
||||
// ADDV $8, R1
|
||||
// MOVV R23, (R2)
|
||||
// ADDV $8, R2
|
||||
// and 128 is the number of such blocks. See runtime/duff_mips64.s:duffcopy.
|
||||
|
||||
// large or unaligned move uses a loop
|
||||
(Move [s] {t} dst src mem)
|
||||
&& s > 24 && logLargeCopy(v, s) || t.Alignment()%8 != 0 =>
|
||||
(LoweredMove [t.Alignment()]
|
||||
dst
|
||||
src
|
||||
(ADDVconst <src.Type> src [s-moveSize(t.Alignment(), config)])
|
||||
mem)
|
||||
|
||||
// calls
|
||||
(StaticCall ...) => (CALLstatic ...)
|
||||
(ClosureCall ...) => (CALLclosure ...)
|
||||
(InterCall ...) => (CALLinter ...)
|
||||
(TailCall ...) => (CALLtail ...)
|
||||
|
||||
// atomic intrinsics
|
||||
(AtomicLoad(8|32|64) ...) => (LoweredAtomicLoad(8|32|64) ...)
|
||||
(AtomicLoadPtr ...) => (LoweredAtomicLoad64 ...)
|
||||
|
||||
(AtomicStore(8|32|64) ...) => (LoweredAtomicStore(8|32|64) ...)
|
||||
(AtomicStorePtrNoWB ...) => (LoweredAtomicStore64 ...)
|
||||
|
||||
(AtomicExchange(32|64) ...) => (LoweredAtomicExchange(32|64) ...)
|
||||
|
||||
(AtomicAdd(32|64) ...) => (LoweredAtomicAdd(32|64) ...)
|
||||
|
||||
(AtomicCompareAndSwap(32|64) ...) => (LoweredAtomicCas(32|64) ...)
|
||||
|
||||
// checks
|
||||
(NilCheck ...) => (LoweredNilCheck ...)
|
||||
(IsNonNil ptr) => (SGTU ptr (MOVVconst [0]))
|
||||
(IsInBounds idx len) => (SGTU len idx)
|
||||
(IsSliceInBounds idx len) => (XOR (MOVVconst [1]) (SGTU idx len))
|
||||
|
||||
// pseudo-ops
|
||||
(GetClosurePtr ...) => (LoweredGetClosurePtr ...)
|
||||
(GetCallerSP ...) => (LoweredGetCallerSP ...)
|
||||
(GetCallerPC ...) => (LoweredGetCallerPC ...)
|
||||
|
||||
(If cond yes no) => (NE cond yes no)
|
||||
|
||||
// Write barrier.
|
||||
(WB ...) => (LoweredWB ...)
|
||||
|
||||
(PanicBounds [kind] x y mem) && boundsABI(kind) == 0 => (LoweredPanicBoundsA [kind] x y mem)
|
||||
(PanicBounds [kind] x y mem) && boundsABI(kind) == 1 => (LoweredPanicBoundsB [kind] x y mem)
|
||||
(PanicBounds [kind] x y mem) && boundsABI(kind) == 2 => (LoweredPanicBoundsC [kind] x y mem)
|
||||
|
||||
// Optimizations
|
||||
|
||||
// Absorb boolean tests into block
|
||||
(NE (FPFlagTrue cmp) yes no) => (FPT cmp yes no)
|
||||
(NE (FPFlagFalse cmp) yes no) => (FPF cmp yes no)
|
||||
(EQ (FPFlagTrue cmp) yes no) => (FPF cmp yes no)
|
||||
(EQ (FPFlagFalse cmp) yes no) => (FPT cmp yes no)
|
||||
(NE (XORconst [1] cmp:(SGT _ _)) yes no) => (EQ cmp yes no)
|
||||
(NE (XORconst [1] cmp:(SGTU _ _)) yes no) => (EQ cmp yes no)
|
||||
(NE (XORconst [1] cmp:(SGTconst _)) yes no) => (EQ cmp yes no)
|
||||
(NE (XORconst [1] cmp:(SGTUconst _)) yes no) => (EQ cmp yes no)
|
||||
(EQ (XORconst [1] cmp:(SGT _ _)) yes no) => (NE cmp yes no)
|
||||
(EQ (XORconst [1] cmp:(SGTU _ _)) yes no) => (NE cmp yes no)
|
||||
(EQ (XORconst [1] cmp:(SGTconst _)) yes no) => (NE cmp yes no)
|
||||
(EQ (XORconst [1] cmp:(SGTUconst _)) yes no) => (NE cmp yes no)
|
||||
(NE (SGTUconst [1] x) yes no) => (EQ x yes no)
|
||||
(EQ (SGTUconst [1] x) yes no) => (NE x yes no)
|
||||
(NE (SGTU x (MOVVconst [0])) yes no) => (NE x yes no)
|
||||
(EQ (SGTU x (MOVVconst [0])) yes no) => (EQ x yes no)
|
||||
(NE (SGTconst [0] x) yes no) => (LTZ x yes no)
|
||||
(EQ (SGTconst [0] x) yes no) => (GEZ x yes no)
|
||||
(NE (SGT x (MOVVconst [0])) yes no) => (GTZ x yes no)
|
||||
(EQ (SGT x (MOVVconst [0])) yes no) => (LEZ x yes no)
|
||||
|
||||
// fold offset into address
|
||||
(ADDVconst [off1] (MOVVaddr [off2] {sym} ptr)) && is32Bit(off1+int64(off2)) => (MOVVaddr [int32(off1)+int32(off2)] {sym} ptr)
|
||||
|
||||
// fold address into load/store
|
||||
(MOVBload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVBload [off1+int32(off2)] {sym} ptr mem)
|
||||
(MOVBUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVBUload [off1+int32(off2)] {sym} ptr mem)
|
||||
(MOVHload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVHload [off1+int32(off2)] {sym} ptr mem)
|
||||
(MOVHUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVHUload [off1+int32(off2)] {sym} ptr mem)
|
||||
(MOVWload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVWload [off1+int32(off2)] {sym} ptr mem)
|
||||
(MOVWUload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVWUload [off1+int32(off2)] {sym} ptr mem)
|
||||
(MOVVload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVVload [off1+int32(off2)] {sym} ptr mem)
|
||||
(MOVFload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVFload [off1+int32(off2)] {sym} ptr mem)
|
||||
(MOVDload [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVDload [off1+int32(off2)] {sym} ptr mem)
|
||||
|
||||
(MOVBstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) => (MOVBstore [off1+int32(off2)] {sym} ptr val mem)
|
||||
(MOVHstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) => (MOVHstore [off1+int32(off2)] {sym} ptr val mem)
|
||||
(MOVWstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) => (MOVWstore [off1+int32(off2)] {sym} ptr val mem)
|
||||
(MOVVstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) => (MOVVstore [off1+int32(off2)] {sym} ptr val mem)
|
||||
(MOVFstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) => (MOVFstore [off1+int32(off2)] {sym} ptr val mem)
|
||||
(MOVDstore [off1] {sym} (ADDVconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2) => (MOVDstore [off1+int32(off2)] {sym} ptr val mem)
|
||||
(MOVBstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVBstorezero [off1+int32(off2)] {sym} ptr mem)
|
||||
(MOVHstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVHstorezero [off1+int32(off2)] {sym} ptr mem)
|
||||
(MOVWstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVWstorezero [off1+int32(off2)] {sym} ptr mem)
|
||||
(MOVVstorezero [off1] {sym} (ADDVconst [off2] ptr) mem) && is32Bit(int64(off1)+off2) => (MOVVstorezero [off1+int32(off2)] {sym} ptr mem)
|
||||
|
||||
(MOVBload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
|
||||
(MOVBload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
|
||||
(MOVBUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
|
||||
(MOVBUload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
|
||||
(MOVHload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
|
||||
(MOVHload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
|
||||
(MOVHUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
|
||||
(MOVHUload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
|
||||
(MOVWload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
|
||||
(MOVWload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
|
||||
(MOVWUload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
|
||||
(MOVWUload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
|
||||
(MOVVload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
|
||||
(MOVVload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
|
||||
(MOVFload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
|
||||
(MOVFload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
|
||||
(MOVDload [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
|
||||
(MOVDload [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
|
||||
|
||||
(MOVBstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
|
||||
(MOVBstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem)
|
||||
(MOVHstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
|
||||
(MOVHstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem)
|
||||
(MOVWstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
|
||||
(MOVWstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem)
|
||||
(MOVVstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
|
||||
(MOVVstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem)
|
||||
(MOVFstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
|
||||
(MOVFstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem)
|
||||
(MOVDstore [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
|
||||
(MOVDstore [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr val mem)
|
||||
(MOVBstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
|
||||
(MOVBstorezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
|
||||
(MOVHstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
|
||||
(MOVHstorezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
|
||||
(MOVWstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
|
||||
(MOVWstorezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
|
||||
(MOVVstorezero [off1] {sym1} (MOVVaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2)) =>
|
||||
(MOVVstorezero [off1+int32(off2)] {mergeSym(sym1,sym2)} ptr mem)
|
||||
|
||||
(LoweredAtomicStore(32|64) ptr (MOVVconst [0]) mem) => (LoweredAtomicStorezero(32|64) ptr mem)
|
||||
(LoweredAtomicAdd32 ptr (MOVVconst [c]) mem) && is32Bit(c) => (LoweredAtomicAddconst32 [int32(c)] ptr mem)
|
||||
(LoweredAtomicAdd64 ptr (MOVVconst [c]) mem) && is32Bit(c) => (LoweredAtomicAddconst64 [c] ptr mem)
|
||||
|
||||
// don't extend after proper load
|
||||
(MOVBreg x:(MOVBload _ _)) => (MOVVreg x)
|
||||
(MOVBUreg x:(MOVBUload _ _)) => (MOVVreg x)
|
||||
(MOVHreg x:(MOVBload _ _)) => (MOVVreg x)
|
||||
(MOVHreg x:(MOVBUload _ _)) => (MOVVreg x)
|
||||
(MOVHreg x:(MOVHload _ _)) => (MOVVreg x)
|
||||
(MOVHUreg x:(MOVBUload _ _)) => (MOVVreg x)
|
||||
(MOVHUreg x:(MOVHUload _ _)) => (MOVVreg x)
|
||||
(MOVWreg x:(MOVBload _ _)) => (MOVVreg x)
|
||||
(MOVWreg x:(MOVBUload _ _)) => (MOVVreg x)
|
||||
(MOVWreg x:(MOVHload _ _)) => (MOVVreg x)
|
||||
(MOVWreg x:(MOVHUload _ _)) => (MOVVreg x)
|
||||
(MOVWreg x:(MOVWload _ _)) => (MOVVreg x)
|
||||
(MOVWUreg x:(MOVBUload _ _)) => (MOVVreg x)
|
||||
(MOVWUreg x:(MOVHUload _ _)) => (MOVVreg x)
|
||||
(MOVWUreg x:(MOVWUload _ _)) => (MOVVreg x)
|
||||
|
||||
// fold double extensions
|
||||
(MOVBreg x:(MOVBreg _)) => (MOVVreg x)
|
||||
(MOVBUreg x:(MOVBUreg _)) => (MOVVreg x)
|
||||
(MOVHreg x:(MOVBreg _)) => (MOVVreg x)
|
||||
(MOVHreg x:(MOVBUreg _)) => (MOVVreg x)
|
||||
(MOVHreg x:(MOVHreg _)) => (MOVVreg x)
|
||||
(MOVHUreg x:(MOVBUreg _)) => (MOVVreg x)
|
||||
(MOVHUreg x:(MOVHUreg _)) => (MOVVreg x)
|
||||
(MOVWreg x:(MOVBreg _)) => (MOVVreg x)
|
||||
(MOVWreg x:(MOVBUreg _)) => (MOVVreg x)
|
||||
(MOVWreg x:(MOVHreg _)) => (MOVVreg x)
|
||||
(MOVWreg x:(MOVWreg _)) => (MOVVreg x)
|
||||
(MOVWUreg x:(MOVBUreg _)) => (MOVVreg x)
|
||||
(MOVWUreg x:(MOVHUreg _)) => (MOVVreg x)
|
||||
(MOVWUreg x:(MOVWUreg _)) => (MOVVreg x)
|
||||
|
||||
// don't extend before store
|
||||
(MOVBstore [off] {sym} ptr (MOVBreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr (MOVBUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr (MOVHreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr (MOVWreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
|
||||
(MOVBstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
|
||||
(MOVHstore [off] {sym} ptr (MOVHreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
|
||||
(MOVHstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
|
||||
(MOVHstore [off] {sym} ptr (MOVWreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
|
||||
(MOVHstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
|
||||
(MOVWstore [off] {sym} ptr (MOVWreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
|
||||
(MOVWstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
|
||||
|
||||
// if a register move has only 1 use, just use the same register without emitting instruction
|
||||
// MOVVnop doesn't emit instruction, only for ensuring the type.
|
||||
(MOVVreg x) && x.Uses == 1 => (MOVVnop x)
|
||||
|
||||
// fold constant into arithmatic ops
|
||||
(ADDV x (MOVVconst [c])) && is32Bit(c) => (ADDVconst [c] x)
|
||||
(SUBV x (MOVVconst [c])) && is32Bit(c) => (SUBVconst [c] x)
|
||||
(AND x (MOVVconst [c])) && is32Bit(c) => (ANDconst [c] x)
|
||||
(OR x (MOVVconst [c])) && is32Bit(c) => (ORconst [c] x)
|
||||
(XOR x (MOVVconst [c])) && is32Bit(c) => (XORconst [c] x)
|
||||
(NOR x (MOVVconst [c])) && is32Bit(c) => (NORconst [c] x)
|
||||
|
||||
(SLLV _ (MOVVconst [c])) && uint64(c)>=64 => (MOVVconst [0])
|
||||
(SRLV _ (MOVVconst [c])) && uint64(c)>=64 => (MOVVconst [0])
|
||||
(SRAV x (MOVVconst [c])) && uint64(c)>=64 => (SRAVconst x [63])
|
||||
(SLLV x (MOVVconst [c])) => (SLLVconst x [c])
|
||||
(SRLV x (MOVVconst [c])) => (SRLVconst x [c])
|
||||
(SRAV x (MOVVconst [c])) => (SRAVconst x [c])
|
||||
|
||||
(SGT (MOVVconst [c]) x) && is32Bit(c) => (SGTconst [c] x)
|
||||
(SGTU (MOVVconst [c]) x) && is32Bit(c) => (SGTUconst [c] x)
|
||||
|
||||
// mul by constant
|
||||
(Select1 (MULVU x (MOVVconst [-1]))) => (NEGV x)
|
||||
(Select1 (MULVU _ (MOVVconst [0]))) => (MOVVconst [0])
|
||||
(Select1 (MULVU x (MOVVconst [1]))) => x
|
||||
(Select1 (MULVU x (MOVVconst [c]))) && isPowerOfTwo64(c) => (SLLVconst [log64(c)] x)
|
||||
|
||||
// div by constant
|
||||
(Select1 (DIVVU x (MOVVconst [1]))) => x
|
||||
(Select1 (DIVVU x (MOVVconst [c]))) && isPowerOfTwo64(c) => (SRLVconst [log64(c)] x)
|
||||
(Select0 (DIVVU _ (MOVVconst [1]))) => (MOVVconst [0]) // mod
|
||||
(Select0 (DIVVU x (MOVVconst [c]))) && isPowerOfTwo64(c) => (ANDconst [c-1] x) // mod
|
||||
|
||||
// generic simplifications
|
||||
(ADDV x (NEGV y)) => (SUBV x y)
|
||||
(SUBV x x) => (MOVVconst [0])
|
||||
(SUBV (MOVVconst [0]) x) => (NEGV x)
|
||||
(AND x x) => x
|
||||
(OR x x) => x
|
||||
(XOR x x) => (MOVVconst [0])
|
||||
|
||||
// remove redundant *const ops
|
||||
(ADDVconst [0] x) => x
|
||||
(SUBVconst [0] x) => x
|
||||
(ANDconst [0] _) => (MOVVconst [0])
|
||||
(ANDconst [-1] x) => x
|
||||
(ORconst [0] x) => x
|
||||
(ORconst [-1] _) => (MOVVconst [-1])
|
||||
(XORconst [0] x) => x
|
||||
(XORconst [-1] x) => (NORconst [0] x)
|
||||
|
||||
// generic constant folding
|
||||
(ADDVconst [c] (MOVVconst [d])) => (MOVVconst [c+d])
|
||||
(ADDVconst [c] (ADDVconst [d] x)) && is32Bit(c+d) => (ADDVconst [c+d] x)
|
||||
(ADDVconst [c] (SUBVconst [d] x)) && is32Bit(c-d) => (ADDVconst [c-d] x)
|
||||
(SUBVconst [c] (MOVVconst [d])) => (MOVVconst [d-c])
|
||||
(SUBVconst [c] (SUBVconst [d] x)) && is32Bit(-c-d) => (ADDVconst [-c-d] x)
|
||||
(SUBVconst [c] (ADDVconst [d] x)) && is32Bit(-c+d) => (ADDVconst [-c+d] x)
|
||||
(SLLVconst [c] (MOVVconst [d])) => (MOVVconst [d<<uint64(c)])
|
||||
(SRLVconst [c] (MOVVconst [d])) => (MOVVconst [int64(uint64(d)>>uint64(c))])
|
||||
(SRAVconst [c] (MOVVconst [d])) => (MOVVconst [d>>uint64(c)])
|
||||
(Select1 (MULVU (MOVVconst [c]) (MOVVconst [d]))) => (MOVVconst [c*d])
|
||||
(Select1 (DIVV (MOVVconst [c]) (MOVVconst [d]))) => (MOVVconst [c/d])
|
||||
(Select1 (DIVVU (MOVVconst [c]) (MOVVconst [d]))) => (MOVVconst [int64(uint64(c)/uint64(d))])
|
||||
(Select0 (DIVV (MOVVconst [c]) (MOVVconst [d]))) => (MOVVconst [c%d]) // mod
|
||||
(Select0 (DIVVU (MOVVconst [c]) (MOVVconst [d]))) => (MOVVconst [int64(uint64(c)%uint64(d))]) // mod
|
||||
(ANDconst [c] (MOVVconst [d])) => (MOVVconst [c&d])
|
||||
(ANDconst [c] (ANDconst [d] x)) => (ANDconst [c&d] x)
|
||||
(ORconst [c] (MOVVconst [d])) => (MOVVconst [c|d])
|
||||
(ORconst [c] (ORconst [d] x)) && is32Bit(c|d) => (ORconst [c|d] x)
|
||||
(XORconst [c] (MOVVconst [d])) => (MOVVconst [c^d])
|
||||
(XORconst [c] (XORconst [d] x)) && is32Bit(c^d) => (XORconst [c^d] x)
|
||||
(NORconst [c] (MOVVconst [d])) => (MOVVconst [^(c|d)])
|
||||
(NEGV (MOVVconst [c])) => (MOVVconst [-c])
|
||||
(MOVBreg (MOVVconst [c])) => (MOVVconst [int64(int8(c))])
|
||||
(MOVBUreg (MOVVconst [c])) => (MOVVconst [int64(uint8(c))])
|
||||
(MOVHreg (MOVVconst [c])) => (MOVVconst [int64(int16(c))])
|
||||
(MOVHUreg (MOVVconst [c])) => (MOVVconst [int64(uint16(c))])
|
||||
(MOVWreg (MOVVconst [c])) => (MOVVconst [int64(int32(c))])
|
||||
(MOVWUreg (MOVVconst [c])) => (MOVVconst [int64(uint32(c))])
|
||||
(MOVVreg (MOVVconst [c])) => (MOVVconst [c])
|
||||
|
||||
// constant comparisons
|
||||
(SGTconst [c] (MOVVconst [d])) && c>d => (MOVVconst [1])
|
||||
(SGTconst [c] (MOVVconst [d])) && c<=d => (MOVVconst [0])
|
||||
(SGTUconst [c] (MOVVconst [d])) && uint64(c)>uint64(d) => (MOVVconst [1])
|
||||
(SGTUconst [c] (MOVVconst [d])) && uint64(c)<=uint64(d) => (MOVVconst [0])
|
||||
|
||||
// other known comparisons
|
||||
(SGTconst [c] (MOVBreg _)) && 0x7f < c => (MOVVconst [1])
|
||||
(SGTconst [c] (MOVBreg _)) && c <= -0x80 => (MOVVconst [0])
|
||||
(SGTconst [c] (MOVBUreg _)) && 0xff < c => (MOVVconst [1])
|
||||
(SGTconst [c] (MOVBUreg _)) && c < 0 => (MOVVconst [0])
|
||||
(SGTUconst [c] (MOVBUreg _)) && 0xff < uint64(c) => (MOVVconst [1])
|
||||
(SGTconst [c] (MOVHreg _)) && 0x7fff < c => (MOVVconst [1])
|
||||
(SGTconst [c] (MOVHreg _)) && c <= -0x8000 => (MOVVconst [0])
|
||||
(SGTconst [c] (MOVHUreg _)) && 0xffff < c => (MOVVconst [1])
|
||||
(SGTconst [c] (MOVHUreg _)) && c < 0 => (MOVVconst [0])
|
||||
(SGTUconst [c] (MOVHUreg _)) && 0xffff < uint64(c) => (MOVVconst [1])
|
||||
(SGTconst [c] (MOVWUreg _)) && c < 0 => (MOVVconst [0])
|
||||
(SGTconst [c] (ANDconst [m] _)) && 0 <= m && m < c => (MOVVconst [1])
|
||||
(SGTUconst [c] (ANDconst [m] _)) && uint64(m) < uint64(c) => (MOVVconst [1])
|
||||
(SGTconst [c] (SRLVconst _ [d])) && 0 <= c && 0 < d && d <= 63 && 0xffffffffffffffff>>uint64(d) < uint64(c) => (MOVVconst [1])
|
||||
(SGTUconst [c] (SRLVconst _ [d])) && 0 < d && d <= 63 && 0xffffffffffffffff>>uint64(d) < uint64(c) => (MOVVconst [1])
|
||||
|
||||
// absorb constants into branches
|
||||
(EQ (MOVVconst [0]) yes no) => (First yes no)
|
||||
(EQ (MOVVconst [c]) yes no) && c != 0 => (First no yes)
|
||||
(NE (MOVVconst [0]) yes no) => (First no yes)
|
||||
(NE (MOVVconst [c]) yes no) && c != 0 => (First yes no)
|
||||
(LTZ (MOVVconst [c]) yes no) && c < 0 => (First yes no)
|
||||
(LTZ (MOVVconst [c]) yes no) && c >= 0 => (First no yes)
|
||||
(LEZ (MOVVconst [c]) yes no) && c <= 0 => (First yes no)
|
||||
(LEZ (MOVVconst [c]) yes no) && c > 0 => (First no yes)
|
||||
(GTZ (MOVVconst [c]) yes no) && c > 0 => (First yes no)
|
||||
(GTZ (MOVVconst [c]) yes no) && c <= 0 => (First no yes)
|
||||
(GEZ (MOVVconst [c]) yes no) && c >= 0 => (First yes no)
|
||||
(GEZ (MOVVconst [c]) yes no) && c < 0 => (First no yes)
|
||||
480
src/cmd/compile/internal/ssa/gen/LOONG64Ops.go
Normal file
480
src/cmd/compile/internal/ssa/gen/LOONG64Ops.go
Normal file
@ -0,0 +1,480 @@
|
||||
// Copyright 2022 The Go Authors. All rights reserved.
|
||||
// Use of this source code is governed by a BSD-style
|
||||
// license that can be found in the LICENSE file.
|
||||
|
||||
//go:build ignore
|
||||
// +build ignore
|
||||
|
||||
package main
|
||||
|
||||
import "strings"
|
||||
|
||||
// Notes:
|
||||
// - Integer types live in the low portion of registers. Upper portions are junk.
|
||||
// - Boolean types use the low-order byte of a register. 0=false, 1=true.
|
||||
// Upper bytes are junk.
|
||||
// - *const instructions may use a constant larger than the instruction can encode.
|
||||
// In this case the assembler expands to multiple instructions and uses tmp
|
||||
// register (R23).
|
||||
|
||||
// Suffixes encode the bit width of various instructions.
|
||||
// V (vlong) = 64 bit
|
||||
// WU (word) = 32 bit unsigned
|
||||
// W (word) = 32 bit
|
||||
// H (half word) = 16 bit
|
||||
// HU = 16 bit unsigned
|
||||
// B (byte) = 8 bit
|
||||
// BU = 8 bit unsigned
|
||||
// F (float) = 32 bit float
|
||||
// D (double) = 64 bit float
|
||||
|
||||
// Note: registers not used in regalloc are not included in this list,
|
||||
// so that regmask stays within int64
|
||||
// Be careful when hand coding regmasks.
|
||||
var regNamesLOONG64 = []string{
|
||||
"R0", // constant 0
|
||||
"R1",
|
||||
"SP", // aka R3
|
||||
"R4",
|
||||
"R5",
|
||||
"R6",
|
||||
"R7",
|
||||
"R8",
|
||||
"R9",
|
||||
"R10",
|
||||
"R11",
|
||||
"R12",
|
||||
"R13",
|
||||
"R14",
|
||||
"R15",
|
||||
"R16",
|
||||
"R17",
|
||||
"R18",
|
||||
"R19",
|
||||
"R20",
|
||||
"R21",
|
||||
"g", // aka R22
|
||||
"R23",
|
||||
"R24",
|
||||
"R25",
|
||||
"R26",
|
||||
"R27",
|
||||
"R28",
|
||||
"R29",
|
||||
// R30 is REGTMP not used in regalloc
|
||||
"R31",
|
||||
|
||||
"F0",
|
||||
"F1",
|
||||
"F2",
|
||||
"F3",
|
||||
"F4",
|
||||
"F5",
|
||||
"F6",
|
||||
"F7",
|
||||
"F8",
|
||||
"F9",
|
||||
"F10",
|
||||
"F11",
|
||||
"F12",
|
||||
"F13",
|
||||
"F14",
|
||||
"F15",
|
||||
"F16",
|
||||
"F17",
|
||||
"F18",
|
||||
"F19",
|
||||
"F20",
|
||||
"F21",
|
||||
"F22",
|
||||
"F23",
|
||||
"F24",
|
||||
"F25",
|
||||
"F26",
|
||||
"F27",
|
||||
"F28",
|
||||
"F29",
|
||||
"F30",
|
||||
"F31",
|
||||
|
||||
// If you add registers, update asyncPreempt in runtime.
|
||||
|
||||
// pseudo-registers
|
||||
"SB",
|
||||
}
|
||||
|
||||
func init() {
|
||||
// Make map from reg names to reg integers.
|
||||
if len(regNamesLOONG64) > 64 {
|
||||
panic("too many registers")
|
||||
}
|
||||
num := map[string]int{}
|
||||
for i, name := range regNamesLOONG64 {
|
||||
num[name] = i
|
||||
}
|
||||
buildReg := func(s string) regMask {
|
||||
m := regMask(0)
|
||||
for _, r := range strings.Split(s, " ") {
|
||||
if n, ok := num[r]; ok {
|
||||
m |= regMask(1) << uint(n)
|
||||
continue
|
||||
}
|
||||
panic("register " + r + " not found")
|
||||
}
|
||||
return m
|
||||
}
|
||||
|
||||
// Common individual register masks
|
||||
var (
|
||||
gp = buildReg("R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31") // R1 is LR, R2 is thread pointer, R3 is stack pointer, R21-unused, R22 is g, R30 is REGTMP
|
||||
gps = buildReg("R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R19 R20 R23 R24 R25 R26 R27 R28 R29 R31") | buildReg("g")
|
||||
gpg = gp | buildReg("g")
|
||||
gpsp = gp | buildReg("SP")
|
||||
gpspg = gpg | buildReg("SP")
|
||||
gpspsbg = gpspg | buildReg("SB")
|
||||
fp = buildReg("F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31")
|
||||
callerSave = gp | fp | buildReg("g") // runtime.setg (and anything calling it) may clobber g
|
||||
r1 = buildReg("R19")
|
||||
r2 = buildReg("R18")
|
||||
r3 = buildReg("R17")
|
||||
r4 = buildReg("R4")
|
||||
)
|
||||
// Common regInfo
|
||||
var (
|
||||
gp01 = regInfo{inputs: nil, outputs: []regMask{gp}}
|
||||
gp11 = regInfo{inputs: []regMask{gpg}, outputs: []regMask{gp}}
|
||||
gp11sp = regInfo{inputs: []regMask{gpspg}, outputs: []regMask{gp}}
|
||||
gp21 = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp}}
|
||||
gpmuldiv = regInfo{inputs: []regMask{gps, gps}, outputs: []regMask{buildReg("R17"), buildReg("R18")}}
|
||||
gpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gp}}
|
||||
gpstore = regInfo{inputs: []regMask{gpspsbg, gpg}}
|
||||
gpstore0 = regInfo{inputs: []regMask{gpspsbg}}
|
||||
gpxchg = regInfo{inputs: []regMask{gpspsbg, gpg}, outputs: []regMask{gp}}
|
||||
gpcas = regInfo{inputs: []regMask{gpspsbg, gpg, gpg}, outputs: []regMask{gp}}
|
||||
fp01 = regInfo{inputs: nil, outputs: []regMask{fp}}
|
||||
fp11 = regInfo{inputs: []regMask{fp}, outputs: []regMask{fp}}
|
||||
fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{fp}}
|
||||
fp2flags = regInfo{inputs: []regMask{fp, fp}}
|
||||
fpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{fp}}
|
||||
fpstore = regInfo{inputs: []regMask{gpspsbg, fp}}
|
||||
readflags = regInfo{inputs: nil, outputs: []regMask{gp}}
|
||||
)
|
||||
ops := []opData{
|
||||
// binary ops
|
||||
{name: "ADDV", argLength: 2, reg: gp21, asm: "ADDVU", commutative: true}, // arg0 + arg1
|
||||
{name: "ADDVconst", argLength: 1, reg: gp11sp, asm: "ADDVU", aux: "Int64"}, // arg0 + auxInt. auxInt is 32-bit, also in other *const ops.
|
||||
{name: "SUBV", argLength: 2, reg: gp21, asm: "SUBVU"}, // arg0 - arg1
|
||||
{name: "SUBVconst", argLength: 1, reg: gp11, asm: "SUBVU", aux: "Int64"}, // arg0 - auxInt
|
||||
|
||||
{name: "MULV", argLength: 2, reg: gpmuldiv, commutative: true, typ: "(Int64,Int64)"}, // arg0 * arg1, signed
|
||||
{name: "MULVU", argLength: 2, reg: gpmuldiv, commutative: true, typ: "(UInt64,UInt64)"}, // arg0 * arg1, unsigned
|
||||
{name: "DIVV", argLength: 2, reg: gpmuldiv, typ: "(Int64,Int64)"}, // arg0 / arg1, signed
|
||||
{name: "DIVVU", argLength: 2, reg: gpmuldiv, typ: "(UInt64,UInt64)"}, // arg0 / arg1, unsigned
|
||||
|
||||
{name: "ADDF", argLength: 2, reg: fp21, asm: "ADDF", commutative: true}, // arg0 + arg1
|
||||
{name: "ADDD", argLength: 2, reg: fp21, asm: "ADDD", commutative: true}, // arg0 + arg1
|
||||
{name: "SUBF", argLength: 2, reg: fp21, asm: "SUBF"}, // arg0 - arg1
|
||||
{name: "SUBD", argLength: 2, reg: fp21, asm: "SUBD"}, // arg0 - arg1
|
||||
{name: "MULF", argLength: 2, reg: fp21, asm: "MULF", commutative: true}, // arg0 * arg1
|
||||
{name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true}, // arg0 * arg1
|
||||
{name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"}, // arg0 / arg1
|
||||
{name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"}, // arg0 / arg1
|
||||
|
||||
{name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true}, // arg0 & arg1
|
||||
{name: "ANDconst", argLength: 1, reg: gp11, asm: "AND", aux: "Int64"}, // arg0 & auxInt
|
||||
{name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true}, // arg0 | arg1
|
||||
{name: "ORconst", argLength: 1, reg: gp11, asm: "OR", aux: "Int64"}, // arg0 | auxInt
|
||||
{name: "XOR", argLength: 2, reg: gp21, asm: "XOR", commutative: true, typ: "UInt64"}, // arg0 ^ arg1
|
||||
{name: "XORconst", argLength: 1, reg: gp11, asm: "XOR", aux: "Int64", typ: "UInt64"}, // arg0 ^ auxInt
|
||||
{name: "NOR", argLength: 2, reg: gp21, asm: "NOR", commutative: true}, // ^(arg0 | arg1)
|
||||
{name: "NORconst", argLength: 1, reg: gp11, asm: "NOR", aux: "Int64"}, // ^(arg0 | auxInt)
|
||||
|
||||
{name: "NEGV", argLength: 1, reg: gp11}, // -arg0
|
||||
{name: "NEGF", argLength: 1, reg: fp11, asm: "NEGF"}, // -arg0, float32
|
||||
{name: "NEGD", argLength: 1, reg: fp11, asm: "NEGD"}, // -arg0, float64
|
||||
{name: "SQRTD", argLength: 1, reg: fp11, asm: "SQRTD"}, // sqrt(arg0), float64
|
||||
{name: "SQRTF", argLength: 1, reg: fp11, asm: "SQRTF"}, // sqrt(arg0), float32
|
||||
|
||||
// shifts
|
||||
{name: "SLLV", argLength: 2, reg: gp21, asm: "SLLV"}, // arg0 << arg1, shift amount is mod 64
|
||||
{name: "SLLVconst", argLength: 1, reg: gp11, asm: "SLLV", aux: "Int64"}, // arg0 << auxInt
|
||||
{name: "SRLV", argLength: 2, reg: gp21, asm: "SRLV"}, // arg0 >> arg1, unsigned, shift amount is mod 64
|
||||
{name: "SRLVconst", argLength: 1, reg: gp11, asm: "SRLV", aux: "Int64"}, // arg0 >> auxInt, unsigned
|
||||
{name: "SRAV", argLength: 2, reg: gp21, asm: "SRAV"}, // arg0 >> arg1, signed, shift amount is mod 64
|
||||
{name: "SRAVconst", argLength: 1, reg: gp11, asm: "SRAV", aux: "Int64"}, // arg0 >> auxInt, signed
|
||||
|
||||
// comparisons
|
||||
{name: "SGT", argLength: 2, reg: gp21, asm: "SGT", typ: "Bool"}, // 1 if arg0 > arg1 (signed), 0 otherwise
|
||||
{name: "SGTconst", argLength: 1, reg: gp11, asm: "SGT", aux: "Int64", typ: "Bool"}, // 1 if auxInt > arg0 (signed), 0 otherwise
|
||||
{name: "SGTU", argLength: 2, reg: gp21, asm: "SGTU", typ: "Bool"}, // 1 if arg0 > arg1 (unsigned), 0 otherwise
|
||||
{name: "SGTUconst", argLength: 1, reg: gp11, asm: "SGTU", aux: "Int64", typ: "Bool"}, // 1 if auxInt > arg0 (unsigned), 0 otherwise
|
||||
|
||||
{name: "CMPEQF", argLength: 2, reg: fp2flags, asm: "CMPEQF", typ: "Flags"}, // flags=true if arg0 = arg1, float32
|
||||
{name: "CMPEQD", argLength: 2, reg: fp2flags, asm: "CMPEQD", typ: "Flags"}, // flags=true if arg0 = arg1, float64
|
||||
{name: "CMPGEF", argLength: 2, reg: fp2flags, asm: "CMPGEF", typ: "Flags"}, // flags=true if arg0 >= arg1, float32
|
||||
{name: "CMPGED", argLength: 2, reg: fp2flags, asm: "CMPGED", typ: "Flags"}, // flags=true if arg0 >= arg1, float64
|
||||
{name: "CMPGTF", argLength: 2, reg: fp2flags, asm: "CMPGTF", typ: "Flags"}, // flags=true if arg0 > arg1, float32
|
||||
{name: "CMPGTD", argLength: 2, reg: fp2flags, asm: "CMPGTD", typ: "Flags"}, // flags=true if arg0 > arg1, float64
|
||||
|
||||
// moves
|
||||
{name: "MOVVconst", argLength: 0, reg: gp01, aux: "Int64", asm: "MOVV", typ: "UInt64", rematerializeable: true}, // auxint
|
||||
{name: "MOVFconst", argLength: 0, reg: fp01, aux: "Float64", asm: "MOVF", typ: "Float32", rematerializeable: true}, // auxint as 64-bit float, convert to 32-bit float
|
||||
{name: "MOVDconst", argLength: 0, reg: fp01, aux: "Float64", asm: "MOVD", typ: "Float64", rematerializeable: true}, // auxint as 64-bit float
|
||||
|
||||
{name: "MOVVaddr", argLength: 1, reg: regInfo{inputs: []regMask{buildReg("SP") | buildReg("SB")}, outputs: []regMask{gp}}, aux: "SymOff", asm: "MOVV", rematerializeable: true, symEffect: "Addr"}, // arg0 + auxInt + aux.(*gc.Sym), arg0=SP/SB
|
||||
|
||||
{name: "MOVBload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVB", typ: "Int8", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem.
|
||||
{name: "MOVBUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVBU", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem.
|
||||
{name: "MOVHload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVH", typ: "Int16", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem.
|
||||
{name: "MOVHUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVHU", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem.
|
||||
{name: "MOVWload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVW", typ: "Int32", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem.
|
||||
{name: "MOVWUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVWU", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem.
|
||||
{name: "MOVVload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVV", typ: "UInt64", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem.
|
||||
{name: "MOVFload", argLength: 2, reg: fpload, aux: "SymOff", asm: "MOVF", typ: "Float32", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem.
|
||||
{name: "MOVDload", argLength: 2, reg: fpload, aux: "SymOff", asm: "MOVD", typ: "Float64", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0 + auxInt + aux. arg1=mem.
|
||||
|
||||
{name: "MOVBstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 1 byte of arg1 to arg0 + auxInt + aux. arg2=mem.
|
||||
{name: "MOVHstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 2 bytes of arg1 to arg0 + auxInt + aux. arg2=mem.
|
||||
{name: "MOVWstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem.
|
||||
{name: "MOVVstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVV", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 8 bytes of arg1 to arg0 + auxInt + aux. arg2=mem.
|
||||
{name: "MOVFstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVF", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes of arg1 to arg0 + auxInt + aux. arg2=mem.
|
||||
{name: "MOVDstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVD", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 8 bytes of arg1 to arg0 + auxInt + aux. arg2=mem.
|
||||
|
||||
{name: "MOVBstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 1 byte of zero to arg0 + auxInt + aux. arg1=mem.
|
||||
{name: "MOVHstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 2 bytes of zero to arg0 + auxInt + aux. arg1=mem.
|
||||
{name: "MOVWstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes of zero to arg0 + auxInt + aux. arg1=mem.
|
||||
{name: "MOVVstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVV", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 8 bytes of zero to arg0 + auxInt + aux. ar12=mem.
|
||||
|
||||
// conversions
|
||||
{name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVB"}, // move from arg0, sign-extended from byte
|
||||
{name: "MOVBUreg", argLength: 1, reg: gp11, asm: "MOVBU"}, // move from arg0, unsign-extended from byte
|
||||
{name: "MOVHreg", argLength: 1, reg: gp11, asm: "MOVH"}, // move from arg0, sign-extended from half
|
||||
{name: "MOVHUreg", argLength: 1, reg: gp11, asm: "MOVHU"}, // move from arg0, unsign-extended from half
|
||||
{name: "MOVWreg", argLength: 1, reg: gp11, asm: "MOVW"}, // move from arg0, sign-extended from word
|
||||
{name: "MOVWUreg", argLength: 1, reg: gp11, asm: "MOVWU"}, // move from arg0, unsign-extended from word
|
||||
{name: "MOVVreg", argLength: 1, reg: gp11, asm: "MOVV"}, // move from arg0
|
||||
|
||||
{name: "MOVVnop", argLength: 1, reg: regInfo{inputs: []regMask{gp}, outputs: []regMask{gp}}, resultInArg0: true}, // nop, return arg0 in same register
|
||||
|
||||
{name: "MOVWF", argLength: 1, reg: fp11, asm: "MOVWF"}, // int32 -> float32
|
||||
{name: "MOVWD", argLength: 1, reg: fp11, asm: "MOVWD"}, // int32 -> float64
|
||||
{name: "MOVVF", argLength: 1, reg: fp11, asm: "MOVVF"}, // int64 -> float32
|
||||
{name: "MOVVD", argLength: 1, reg: fp11, asm: "MOVVD"}, // int64 -> float64
|
||||
{name: "TRUNCFW", argLength: 1, reg: fp11, asm: "TRUNCFW"}, // float32 -> int32
|
||||
{name: "TRUNCDW", argLength: 1, reg: fp11, asm: "TRUNCDW"}, // float64 -> int32
|
||||
{name: "TRUNCFV", argLength: 1, reg: fp11, asm: "TRUNCFV"}, // float32 -> int64
|
||||
{name: "TRUNCDV", argLength: 1, reg: fp11, asm: "TRUNCDV"}, // float64 -> int64
|
||||
{name: "MOVFD", argLength: 1, reg: fp11, asm: "MOVFD"}, // float32 -> float64
|
||||
{name: "MOVDF", argLength: 1, reg: fp11, asm: "MOVDF"}, // float64 -> float32
|
||||
|
||||
// function calls
|
||||
{name: "CALLstatic", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem
|
||||
{name: "CALLtail", argLength: 1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // tail call static function aux.(*obj.LSym). arg0=mem, auxint=argsize, returns mem
|
||||
{name: "CALLclosure", argLength: 3, reg: regInfo{inputs: []regMask{gpsp, buildReg("R29"), 0}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call function via closure. arg0=codeptr, arg1=closure, arg2=mem, auxint=argsize, returns mem
|
||||
{name: "CALLinter", argLength: 2, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true}, // call fn by pointer. arg0=codeptr, arg1=mem, auxint=argsize, returns mem
|
||||
|
||||
// duffzero
|
||||
// arg0 = address of memory to zero
|
||||
// arg1 = mem
|
||||
// auxint = offset into duffzero code to start executing
|
||||
// returns mem
|
||||
// R19 aka loong64.REGRT1 changed as side effect
|
||||
{
|
||||
name: "DUFFZERO",
|
||||
aux: "Int64",
|
||||
argLength: 2,
|
||||
reg: regInfo{
|
||||
inputs: []regMask{gp},
|
||||
clobbers: buildReg("R19 R1"),
|
||||
},
|
||||
faultOnNilArg0: true,
|
||||
},
|
||||
|
||||
// duffcopy
|
||||
// arg0 = address of dst memory (in R20, changed as side effect) REGRT2
|
||||
// arg1 = address of src memory (in R19, changed as side effect) REGRT1
|
||||
// arg2 = mem
|
||||
// auxint = offset into duffcopy code to start executing
|
||||
// returns mem
|
||||
{
|
||||
name: "DUFFCOPY",
|
||||
aux: "Int64",
|
||||
argLength: 3,
|
||||
reg: regInfo{
|
||||
inputs: []regMask{buildReg("R20"), buildReg("R19")},
|
||||
clobbers: buildReg("R19 R20 R1"),
|
||||
},
|
||||
faultOnNilArg0: true,
|
||||
faultOnNilArg1: true,
|
||||
},
|
||||
|
||||
// large or unaligned zeroing
|
||||
// arg0 = address of memory to zero (in R19, changed as side effect)
|
||||
// arg1 = address of the last element to zero
|
||||
// arg2 = mem
|
||||
// auxint = alignment
|
||||
// returns mem
|
||||
// SUBV $8, R19
|
||||
// MOVV R0, 8(R19)
|
||||
// ADDV $8, R19
|
||||
// BNE Rarg1, R19, -2(PC)
|
||||
{
|
||||
name: "LoweredZero",
|
||||
aux: "Int64",
|
||||
argLength: 3,
|
||||
reg: regInfo{
|
||||
inputs: []regMask{buildReg("R19"), gp},
|
||||
clobbers: buildReg("R19"),
|
||||
},
|
||||
clobberFlags: true,
|
||||
faultOnNilArg0: true,
|
||||
},
|
||||
|
||||
// large or unaligned move
|
||||
// arg0 = address of dst memory (in R4, changed as side effect)
|
||||
// arg1 = address of src memory (in R19, changed as side effect)
|
||||
// arg2 = address of the last element of src
|
||||
// arg3 = mem
|
||||
// auxint = alignment
|
||||
// returns mem
|
||||
// SUBV $8, R19
|
||||
// MOVV 8(R19), Rtmp
|
||||
// MOVV Rtmp, (R4)
|
||||
// ADDV $8, R19
|
||||
// ADDV $8, R4
|
||||
// BNE Rarg2, R19, -4(PC)
|
||||
{
|
||||
name: "LoweredMove",
|
||||
aux: "Int64",
|
||||
argLength: 4,
|
||||
reg: regInfo{
|
||||
inputs: []regMask{buildReg("R4"), buildReg("R19"), gp},
|
||||
clobbers: buildReg("R19 R4"),
|
||||
},
|
||||
clobberFlags: true,
|
||||
faultOnNilArg0: true,
|
||||
faultOnNilArg1: true,
|
||||
},
|
||||
|
||||
// atomic loads.
|
||||
// load from arg0. arg1=mem.
|
||||
// returns <value,memory> so they can be properly ordered with other loads.
|
||||
{name: "LoweredAtomicLoad8", argLength: 2, reg: gpload, faultOnNilArg0: true},
|
||||
{name: "LoweredAtomicLoad32", argLength: 2, reg: gpload, faultOnNilArg0: true},
|
||||
{name: "LoweredAtomicLoad64", argLength: 2, reg: gpload, faultOnNilArg0: true},
|
||||
|
||||
// atomic stores.
|
||||
// store arg1 to arg0. arg2=mem. returns memory.
|
||||
{name: "LoweredAtomicStore8", argLength: 3, reg: gpstore, faultOnNilArg0: true, hasSideEffects: true},
|
||||
{name: "LoweredAtomicStore32", argLength: 3, reg: gpstore, faultOnNilArg0: true, hasSideEffects: true},
|
||||
{name: "LoweredAtomicStore64", argLength: 3, reg: gpstore, faultOnNilArg0: true, hasSideEffects: true},
|
||||
// store zero to arg0. arg1=mem. returns memory.
|
||||
{name: "LoweredAtomicStorezero32", argLength: 2, reg: gpstore0, faultOnNilArg0: true, hasSideEffects: true},
|
||||
{name: "LoweredAtomicStorezero64", argLength: 2, reg: gpstore0, faultOnNilArg0: true, hasSideEffects: true},
|
||||
|
||||
// atomic exchange.
|
||||
// store arg1 to arg0. arg2=mem. returns <old content of *arg0, memory>.
|
||||
// DBAR
|
||||
// LL (Rarg0), Rout
|
||||
// MOVV Rarg1, Rtmp
|
||||
// SC Rtmp, (Rarg0)
|
||||
// BEQ Rtmp, -3(PC)
|
||||
// DBAR
|
||||
{name: "LoweredAtomicExchange32", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
|
||||
{name: "LoweredAtomicExchange64", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
|
||||
|
||||
// atomic add.
|
||||
// *arg0 += arg1. arg2=mem. returns <new content of *arg0, memory>.
|
||||
// DBAR
|
||||
// LL (Rarg0), Rout
|
||||
// ADDV Rarg1, Rout, Rtmp
|
||||
// SC Rtmp, (Rarg0)
|
||||
// BEQ Rtmp, -3(PC)
|
||||
// DBAR
|
||||
// ADDV Rarg1, Rout
|
||||
{name: "LoweredAtomicAdd32", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
|
||||
{name: "LoweredAtomicAdd64", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
|
||||
// *arg0 += auxint. arg1=mem. returns <new content of *arg0, memory>. auxint is 32-bit.
|
||||
{name: "LoweredAtomicAddconst32", argLength: 2, reg: regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gp}}, aux: "Int32", resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
|
||||
{name: "LoweredAtomicAddconst64", argLength: 2, reg: regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gp}}, aux: "Int64", resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
|
||||
|
||||
// atomic compare and swap.
|
||||
// arg0 = pointer, arg1 = old value, arg2 = new value, arg3 = memory.
|
||||
// if *arg0 == arg1 {
|
||||
// *arg0 = arg2
|
||||
// return (true, memory)
|
||||
// } else {
|
||||
// return (false, memory)
|
||||
// }
|
||||
// DBAR
|
||||
// MOVV $0, Rout
|
||||
// LL (Rarg0), Rtmp
|
||||
// BNE Rtmp, Rarg1, 4(PC)
|
||||
// MOVV Rarg2, Rout
|
||||
// SC Rout, (Rarg0)
|
||||
// BEQ Rout, -4(PC)
|
||||
// DBAR
|
||||
{name: "LoweredAtomicCas32", argLength: 4, reg: gpcas, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
|
||||
{name: "LoweredAtomicCas64", argLength: 4, reg: gpcas, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
|
||||
|
||||
// pseudo-ops
|
||||
{name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gpg}}, nilCheck: true, faultOnNilArg0: true}, // panic if arg0 is nil. arg1=mem.
|
||||
|
||||
{name: "FPFlagTrue", argLength: 1, reg: readflags}, // bool, true if FP flag is true
|
||||
{name: "FPFlagFalse", argLength: 1, reg: readflags}, // bool, true if FP flag is false
|
||||
|
||||
// Scheduler ensures LoweredGetClosurePtr occurs only in entry block,
|
||||
// and sorts it to the very beginning of the block to prevent other
|
||||
// use of R22 (loong64.REGCTXT, the closure pointer)
|
||||
{name: "LoweredGetClosurePtr", reg: regInfo{outputs: []regMask{buildReg("R29")}}, zeroWidth: true},
|
||||
|
||||
// LoweredGetCallerSP returns the SP of the caller of the current function.
|
||||
{name: "LoweredGetCallerSP", reg: gp01, rematerializeable: true},
|
||||
|
||||
// LoweredGetCallerPC evaluates to the PC to which its "caller" will return.
|
||||
// I.e., if f calls g "calls" getcallerpc,
|
||||
// the result should be the PC within f that g will return to.
|
||||
// See runtime/stubs.go for a more detailed discussion.
|
||||
{name: "LoweredGetCallerPC", reg: gp01, rematerializeable: true},
|
||||
|
||||
// LoweredWB invokes runtime.gcWriteBarrier. arg0=destptr, arg1=srcptr, arg2=mem, aux=runtime.gcWriteBarrier
|
||||
// It saves all GP registers if necessary,
|
||||
// but clobbers R1 (LR) because it's a call
|
||||
// and R30 (REGTMP).
|
||||
{name: "LoweredWB", argLength: 3, reg: regInfo{inputs: []regMask{buildReg("R27"), buildReg("R28")}, clobbers: (callerSave &^ gpg) | buildReg("R1")}, clobberFlags: true, aux: "Sym", symEffect: "None"},
|
||||
|
||||
// There are three of these functions so that they can have three different register inputs.
|
||||
// When we check 0 <= c <= cap (A), then 0 <= b <= c (B), then 0 <= a <= b (C), we want the
|
||||
// default registers to match so we don't need to copy registers around unnecessarily.
|
||||
{name: "LoweredPanicBoundsA", argLength: 3, aux: "Int64", reg: regInfo{inputs: []regMask{r3, r4}}, typ: "Mem", call: true}, // arg0=idx, arg1=len, arg2=mem, returns memory. AuxInt contains report code (see PanicBounds in genericOps.go).
|
||||
{name: "LoweredPanicBoundsB", argLength: 3, aux: "Int64", reg: regInfo{inputs: []regMask{r2, r3}}, typ: "Mem", call: true}, // arg0=idx, arg1=len, arg2=mem, returns memory. AuxInt contains report code (see PanicBounds in genericOps.go).
|
||||
{name: "LoweredPanicBoundsC", argLength: 3, aux: "Int64", reg: regInfo{inputs: []regMask{r1, r2}}, typ: "Mem", call: true}, // arg0=idx, arg1=len, arg2=mem, returns memory. AuxInt contains report code (see PanicBounds in genericOps.go).
|
||||
}
|
||||
|
||||
blocks := []blockData{
|
||||
{name: "EQ", controls: 1},
|
||||
{name: "NE", controls: 1},
|
||||
{name: "LTZ", controls: 1}, // < 0
|
||||
{name: "LEZ", controls: 1}, // <= 0
|
||||
{name: "GTZ", controls: 1}, // > 0
|
||||
{name: "GEZ", controls: 1}, // >= 0
|
||||
{name: "FPT", controls: 1}, // FP flag is true
|
||||
{name: "FPF", controls: 1}, // FP flag is false
|
||||
}
|
||||
|
||||
archs = append(archs, arch{
|
||||
name: "LOONG64",
|
||||
pkg: "cmd/internal/obj/loong64",
|
||||
genfile: "../../loong64/ssa.go",
|
||||
ops: ops,
|
||||
blocks: blocks,
|
||||
regnames: regNamesLOONG64,
|
||||
// TODO: support register ABI on loong64
|
||||
ParamIntRegNames: "R4 R5 R6 R7 R8 R9 R10 R11",
|
||||
ParamFloatRegNames: "F0 F1 F2 F3 F4 F5 F6 F7",
|
||||
gpregmask: gp,
|
||||
fpregmask: fp,
|
||||
framepointerreg: -1, // not used
|
||||
linkreg: int8(num["R1"]),
|
||||
})
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
7946
src/cmd/compile/internal/ssa/rewriteLOONG64.go
Normal file
7946
src/cmd/compile/internal/ssa/rewriteLOONG64.go
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user