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cmd/objdump: add s390x plan9 disasm support

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This CL provides vendor support for s390x disassembler plan9 syntax.

cd $GOROOT/src/cmd
go get golang.org/x/arch@master
go mod tidy
go mod vendor

For #15255

Change-Id: I20c87510a1aee2d1cf2df58feb535974c4c0e3ef
Reviewed-on: https://go-review.googlesource.com/c/go/+/623075
Reviewed-by: David Chase <drchase@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Vishwanatha HD <vishwanatha.hd@ibm.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
This commit is contained in:
Srinivas Pokala 2024-10-29 07:33:44 +01:00 committed by Cherry Mui
parent 23493579ea
commit eb29beb0ad
10 changed files with 1437 additions and 123 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/cmd/go.mod
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@ -4,7 +4,7 @@ go 1.24
require (
github.com/google/pprof v0.0.0-20240722153945-304e4f0156b8
golang.org/x/arch v0.10.1-0.20240910142527-7874f23b9c06
golang.org/x/arch v0.11.1-0.20241106162200-f977c2e4e3f4
golang.org/x/build v0.0.0-20240722200705-b9910f320300
golang.org/x/mod v0.20.0
golang.org/x/sync v0.8.0

4
src/cmd/go.sum
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@ -6,8 +6,8 @@ github.com/ianlancetaylor/demangle v0.0.0-20240312041847-bd984b5ce465 h1:KwWnWVW
github.com/ianlancetaylor/demangle v0.0.0-20240312041847-bd984b5ce465/go.mod h1:gx7rwoVhcfuVKG5uya9Hs3Sxj7EIvldVofAWIUtGouw=
github.com/yuin/goldmark v1.6.0 h1:boZcn2GTjpsynOsC0iJHnBWa4Bi0qzfJjthwauItG68=
github.com/yuin/goldmark v1.6.0/go.mod h1:6yULJ656Px+3vBD8DxQVa3kxgyrAnzto9xy5taEt/CY=
golang.org/x/arch v0.10.1-0.20240910142527-7874f23b9c06 h1:UQRD9d43XiTfPsm0o04gmvWqcLLGkwqV+bOwtb7AP6c=
golang.org/x/arch v0.10.1-0.20240910142527-7874f23b9c06/go.mod h1:FEVrYAQjsQXMVJ1nsMoVVXPZg6p2JE2mx8psSWTDQys=
golang.org/x/arch v0.11.1-0.20241106162200-f977c2e4e3f4 h1:B9d6SEXeIaY1QC4c7Gsf88ratIIcxShKAlz60Urrqzw=
golang.org/x/arch v0.11.1-0.20241106162200-f977c2e4e3f4/go.mod h1:FEVrYAQjsQXMVJ1nsMoVVXPZg6p2JE2mx8psSWTDQys=
golang.org/x/build v0.0.0-20240722200705-b9910f320300 h1:2Cqg4LnvfD2ZpG8+6KbyYUkweWhNS3SgfcN/eeVseJ0=
golang.org/x/build v0.0.0-20240722200705-b9910f320300/go.mod h1:YsGhg4JUVUWLzdqU2wCrtpRrOveOql6w56FLDHq/CJ4=
golang.org/x/mod v0.20.0 h1:utOm6MM3R3dnawAiJgn0y+xvuYRsm1RKM/4giyfDgV0=

4
src/cmd/internal/objfile/disasm.go
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@ -421,9 +421,9 @@ func disasm_s390x(code []byte, pc uint64, lookup lookupFunc, _ binary.ByteOrder,
text = "?"
} else {
if gnuAsm {
text = fmt.Sprintf("%s", s390xasm.GNUSyntax(inst, pc))
text = fmt.Sprintf("%-36s // %s", s390xasm.GoSyntax(inst, pc, lookup), s390xasm.GNUSyntax(inst, pc))
} else {
text = fmt.Sprintf("%s", "Go/plan9 syntax unsupported..!!")
text = s390xasm.GoSyntax(inst, pc, lookup)
}
}
return text, size

50
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/decode.go generated vendored
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@ -8,6 +8,8 @@ import (
"encoding/binary"
"fmt"
"log"
"sort"
"sync"
)
const debugDecode = false
@ -111,6 +113,47 @@ const (
TypeLast // must be the last one
)
type InstMaskMap struct {
mask uint64
insn map[uint64]*instFormat
}
// Note, plxv/pstxv have a 5 bit opcode in the second instruction word. Only match the most significant 5 of 6 bits of the second primary opcode.
const lookupOpcodeMask = uint64(0xFC000000F8000000)
// Three level lookup for any instruction:
// 1. Primary opcode map to a list of secondary opcode maps.
// 2. A list of opcodes with distinct masks, sorted by largest to smallest mask.
// 3. A map to a specific opcodes with a given mask.
var getLookupMap = sync.OnceValue(func() map[uint64][]InstMaskMap {
lMap := make(map[uint64][]InstMaskMap)
for idx, _ := range instFormats {
i := &instFormats[idx]
pop := i.Value & lookupOpcodeMask
var me *InstMaskMap
masks := lMap[pop]
for im, m := range masks {
if m.mask == i.Mask {
me = &masks[im]
break
}
}
if me == nil {
me = &InstMaskMap{i.Mask, map[uint64]*instFormat{}}
masks = append(masks, *me)
}
me.insn[i.Value] = i
lMap[pop] = masks
}
// Reverse sort masks to ensure extended mnemonics match before more generic forms of an opcode (e.x nop over ori 0,0,0)
for _, v := range lMap {
sort.Slice(v, func(i, j int) bool {
return v[i].mask > v[j].mask
})
}
return lMap
})
func (t ArgType) String() string {
switch t {
default:
@ -191,10 +234,13 @@ func Decode(src []byte, ord binary.ByteOrder) (inst Inst, err error) {
ui |= uint64(ui_extn[1])
inst.SuffixEnc = ui_extn[1]
}
for i, iform := range instFormats {
if ui&iform.Mask != iform.Value {
fmts := getLookupMap()[ui&lookupOpcodeMask]
for i, masks := range fmts {
if _, fnd := masks.insn[masks.mask&ui]; !fnd {
continue
}
iform := masks.insn[masks.mask&ui]
if ui&iform.DontCare != 0 {
if debugDecode {
log.Printf("Decode(%#x): unused bit is 1 for Op %s", ui, iform.Op)

51
src/cmd/vendor/golang.org/x/arch/s390x/s390xasm/field.go generated vendored
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@ -6,7 +6,6 @@ package s390xasm
import (
"fmt"
"strings"
)
// A BitField is a bit-field in a 64-bit double word.
@ -46,53 +45,3 @@ func (b BitField) ParseSigned(i uint64) int64 {
u := int64(b.Parse(i))
return u << (64 - b.Bits) >> (64 - b.Bits)
}
// BitFields is a series of BitFields representing a single number.
type BitFields []BitField
func (bs BitFields) String() string {
ss := make([]string, len(bs))
for i, bf := range bs {
ss[i] = bf.String()
}
return fmt.Sprintf("<%s>", strings.Join(ss, "|"))
}
func (bs *BitFields) Append(b BitField) {
*bs = append(*bs, b)
}
// parse extracts the bitfields from i, concatenate them and return the result
// as an unsigned integer and the total length of all the bitfields.
// parse will panic if any bitfield in b is invalid, but it doesn't check if
// the sequence of bitfields is reasonable.
func (bs BitFields) parse(i uint64) (u uint64, Bits uint8) {
for _, b := range bs {
u = (u << b.Bits) | uint64(b.Parse(i))
Bits += b.Bits
}
return u, Bits
}
// Parse extracts the bitfields from i, concatenate them and return the result
// as an unsigned integer. Parse will panic if any bitfield in b is invalid.
func (bs BitFields) Parse(i uint64) uint64 {
u, _ := bs.parse(i)
return u
}
// ParseSigned extracts the bitfields from i, concatenate them and return the result
// as a signed integer. Parse will panic if any bitfield in b is invalid.
func (bs BitFields) ParseSigned(i uint64) int64 {
u, l := bs.parse(i)
return int64(u) << (64 - l) >> (64 - l)
}
// Count the number of bits in the aggregate BitFields
func (bs BitFields) NumBits() int {
num := 0
for _, b := range bs {
num += int(b.Bits)
}
return num
}

28
src/cmd/vendor/golang.org/x/arch/s390x/s390xasm/gnu.go generated vendored
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@ -280,6 +280,7 @@ func HandleExtndMnemonic(inst *Inst) string {
typ5ExtndMnics{BaseOpStr: "vfce", Value1: 2, Value2: 0, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfcesb"},
typ5ExtndMnics{BaseOpStr: "vfce", Value1: 2, Value2: 0, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfcesbs"},
typ5ExtndMnics{BaseOpStr: "vfce", Value1: 3, Value2: 0, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfcedb"},
typ5ExtndMnics{BaseOpStr: "vfce", Value1: 3, Value2: 0, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfcedbs"},
typ5ExtndMnics{BaseOpStr: "vfce", Value1: 2, Value2: 8, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfcesb"},
typ5ExtndMnics{BaseOpStr: "vfce", Value1: 2, Value2: 8, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfcesbs"},
typ5ExtndMnics{BaseOpStr: "vfce", Value1: 3, Value2: 8, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfcedb"},
@ -453,8 +454,7 @@ func HandleExtndMnemonic(inst *Inst) string {
case "vavg", "vavgl", "verllv", "veslv", "vesrav", "vesrlv", "vgfm", "vgm", "vmx", "vmxl", "vmrh", "vmrl", "vmn", "vmnl", "vrep",
"vclz", "vctz", "vec", "vecl", "vlc", "vlp", "vpopct", "vrepi", "verim", "verll", "vesl", "vesra", "vesrl", "vgfma", "vlrep",
"vlgv", "vlvg", "vlbrrep", "vler", "vlbr", "vstbr", "vster", "vpk", "vme", "vmh", "vmle", "vmlh", "vmlo", "vml", "vmo", "vmae",
"vmale", "vmalo", "vmal", "vmah", "vmalh", "vmao", "vmph", "vmplh", "vupl", "vupll", "vscbi", "vs", "vsum", "vsumg", "vsumq",
"va", "vacc":
"vmale", "vmalo", "vmal", "vmah", "vmalh", "vmao", "vmph", "vmplh", "vupl", "vupll", "vscbi", "vs", "vsum", "vsumg", "vsumq", "va", "vacc":
switch opString {
@ -569,16 +569,18 @@ func HandleExtndMnemonic(inst *Inst) string {
break
}
}
case "vsum", "vsumg":
for i := 1; i < len(vecInstrExtndMnics)-4; i++ {
if uint8(inst.Args[vecInstrExtndMnics[i].Offset].(Mask)) == vecInstrExtndMnics[i].Value {
newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr
removeArg(inst, int8(vecInstrExtndMnics[i].Offset))
break
}
case "vsum", "vsumg", "vsumq":
var off int
switch opString {
case "vsum":
off = 0
case "vsumg":
off = 1
case "vsumq":
off = 2
}
case "vsumq":
for i := 2; i < len(vecInstrExtndMnics)-2; i++ {
for i := off; i < len(vecInstrExtndMnics)-4+off; i++ {
if uint8(inst.Args[vecInstrExtndMnics[i].Offset].(Mask)) == vecInstrExtndMnics[i].Value {
newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr
removeArg(inst, int8(vecInstrExtndMnics[i].Offset))
@ -668,8 +670,8 @@ func HandleExtndMnemonic(inst *Inst) string {
case "vac", "vaccc":
if uint8(inst.Args[4].(Mask)) == uint8(4) {
newOpStr = opString + vecInstrExtndMnics[3].ExtnOpStr
removeArg(inst, int8(3))
newOpStr = opString + vecInstrExtndMnics[4].ExtnOpStr
removeArg(inst, int8(4))
}
case "vceq", "vch", "vchl":

62
src/cmd/vendor/golang.org/x/arch/s390x/s390xasm/inst.go generated vendored
View File

@ -12,9 +12,9 @@ import (
type Inst struct {
Op Op // Opcode mnemonic
Enc uint64 // Raw encoding bits (if Len == 8, this is the prefix word)
Enc uint64 // Raw encoding bits
Len int // Length of encoding in bytes.
Args Args // Instruction arguments, in Power ISA manual order.
Args Args // Instruction arguments, in s390x ISA manual order.
}
func (i Inst) String(pc uint64) string {
@ -26,19 +26,32 @@ func (i Inst) String(pc uint64) string {
}
mnemonic := HandleExtndMnemonic(&i)
buf.WriteString(fmt.Sprintf("%s", mnemonic))
for j, arg := range i.Args {
if arg == nil {
for j := 0; j < len(i.Args); j++ {
if i.Args[j] == nil {
break
}
str := i.Args[j].String(pc)
if j == 0 {
buf.WriteString(" ")
} else {
switch arg.(type) {
case VReg, Reg:
switch i.Args[j].(type) {
case VReg:
if _, ok := i.Args[j-1].(Disp12); ok {
buf.WriteString("")
buf.WriteString("(")
} else if _, ok := i.Args[j-1].(Disp20); ok {
buf.WriteString("")
buf.WriteString("(")
} else {
buf.WriteString(",")
}
case Reg:
if _, ok := i.Args[j-1].(Disp12); ok {
if str != "" {
buf.WriteString("(")
}
} else if _, ok := i.Args[j-1].(Disp20); ok {
if str != "" {
buf.WriteString("(")
}
} else {
buf.WriteString(",")
}
@ -47,13 +60,34 @@ func (i Inst) String(pc uint64) string {
buf.WriteString(",")
} else if _, ok := i.Args[j-1].(Reg); ok {
buf.WriteString(",")
} else if _, ok := i.Args[j-1].(Disp12); ok {
if str != "" {
buf.WriteString("(")
}
} else if _, ok := i.Args[j-1].(Disp20); ok {
if str != "" {
buf.WriteString("(")
}
} else if _, ok := i.Args[j-1].(Len); ok {
buf.WriteString(",")
} else if _, ok := i.Args[j-1].(Index); ok {
if ((i.Args[j-1].String(pc)) != "") && str != "" {
str = "," + str
} else if str == "" {
str = ")"
}
}
case Index, Len:
if str != "" || (i.Args[j+1].String(pc)) != "" {
buf.WriteString("(")
} else {
j = j + 1
}
default:
buf.WriteString(",")
}
}
buf.WriteString(arg.String(pc))
buf.WriteString(str)
if rxb_check && i.Args[j+2] == nil {
break
}
@ -145,7 +179,7 @@ func (r Index) String(pc uint64) string {
switch {
case X1 <= r && r <= X15:
s := "%"
return fmt.Sprintf("%sr%d,", s, int(r-X0))
return fmt.Sprintf("%sr%d", s, int(r-X0))
case X0 == r:
return fmt.Sprintf("")
default:
@ -159,9 +193,9 @@ type Disp20 uint32
func (Disp20) IsArg() {}
func (r Disp20) String(pc uint64) string {
if (r>>19)&0x01 == 1 {
return fmt.Sprintf("%d(", int32(r|0xfff<<20))
return fmt.Sprintf("%d", int32(r|0xfff<<20))
} else {
return fmt.Sprintf("%d(", int32(r))
return fmt.Sprintf("%d", int32(r))
}
}
@ -170,7 +204,7 @@ type Disp12 uint16
func (Disp12) IsArg() {}
func (r Disp12) String(pc uint64) string {
return fmt.Sprintf("%d(", r)
return fmt.Sprintf("%d", r)
}
// RegIm12 represents an 12-bit Register immediate number.
@ -395,5 +429,5 @@ type Len uint8
func (Len) IsArg() {}
func (i Len) String(pc uint64) string {
return fmt.Sprintf("%d,", uint16(i)+1)
return fmt.Sprintf("%d", uint16(i)+1)
}

1282
src/cmd/vendor/golang.org/x/arch/s390x/s390xasm/plan9.go generated vendored Normal file
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File diff suppressed because it is too large Load Diff

75
src/cmd/vendor/golang.org/x/arch/s390x/s390xasm/tables.go generated vendored
View File

@ -2518,8 +2518,6 @@ var (
ap_ImmUnsigned_16_47 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{16, 32}}
ap_FPReg_12_15 = &argField{Type: TypeFPReg, flags: 0x2, BitField: BitField{12, 4}}
ap_Len_8_15 = &argField{Type: TypeLen, flags: 0x10, BitField: BitField{8, 8}}
ap_ImmUnsigned_8_15 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{8, 8}}
ap_ImmUnsigned_16_31 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{16, 16}}
ap_Mask_8_11 = &argField{Type: TypeMask, flags: 0x800, BitField: BitField{8, 4}}
ap_RegImSigned16_32_47 = &argField{Type: TypeRegImSigned16, flags: 0x80, BitField: BitField{32, 16}}
ap_RegImSigned12_12_23 = &argField{Type: TypeRegImSigned12, flags: 0x80, BitField: BitField{12, 12}}
@ -2531,8 +2529,10 @@ var (
ap_ImmSigned16_32_47 = &argField{Type: TypeImmSigned16, flags: 0x0, BitField: BitField{32, 16}}
ap_ImmSigned8_32_39 = &argField{Type: TypeImmSigned8, flags: 0x0, BitField: BitField{32, 8}}
ap_Mask_12_15 = &argField{Type: TypeMask, flags: 0x800, BitField: BitField{12, 4}}
ap_ImmUnsigned_8_15 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{8, 8}}
ap_ImmUnsigned_32_47 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{32, 16}}
ap_ImmUnsigned_32_39 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{32, 8}}
ap_ImmUnsigned_16_31 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{16, 16}}
ap_FPReg_32_35 = &argField{Type: TypeFPReg, flags: 0x2, BitField: BitField{32, 4}}
ap_Mask_36_39 = &argField{Type: TypeMask, flags: 0x800, BitField: BitField{36, 4}}
ap_ACReg_24_27 = &argField{Type: TypeACReg, flags: 0x3, BitField: BitField{24, 4}}
@ -2546,6 +2546,7 @@ var (
ap_ACReg_12_15 = &argField{Type: TypeACReg, flags: 0x3, BitField: BitField{12, 4}}
ap_CReg_8_11 = &argField{Type: TypeCReg, flags: 0x4, BitField: BitField{8, 4}}
ap_CReg_12_15 = &argField{Type: TypeCReg, flags: 0x4, BitField: BitField{12, 4}}
ap_ImmSigned32_16_31 = &argField{Type: TypeImmSigned32, flags: 0x0, BitField: BitField{16, 16}}
ap_ImmUnsigned_24_27 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{24, 4}}
ap_ImmUnsigned_28_31 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{28, 4}}
ap_ImmUnsigned_16_23 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{16, 8}}
@ -2706,21 +2707,21 @@ var instFormats = [...]instFormat{
{NC, 0xff00000000000000, 0xd400000000000000, 0x0, // AND (character) (NC D1(L1,B1),D2(B2))
[8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
{NI, 0xff00000000000000, 0x9400000000000000, 0x0, // AND (immediate) (NI D1(B1),I2)
[8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}},
[8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmSigned8_8_15}},
{NIY, 0xff00000000ff0000, 0xeb00000000540000, 0x0, // AND (immediate) (NIY D1(B1),I2)
[8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}},
[8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmSigned8_8_15}},
{NIHH, 0xff0f000000000000, 0xa504000000000000, 0x0, // AND IMMEDIATE (high high) (NIHH R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}},
{NIHL, 0xff0f000000000000, 0xa505000000000000, 0x0, // AND IMMEDIATE (high low) (NIHL R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}},
{NIHF, 0xff0f000000000000, 0xc00a000000000000, 0x0, // AND IMMEDIATE (high) (NIHF R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}},
{NILH, 0xff0f000000000000, 0xa506000000000000, 0x0, // AND IMMEDIATE (low high) (NILH R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}},
{NILL, 0xff0f000000000000, 0xa507000000000000, 0x0, // AND IMMEDIATE (low low) (NILL R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}},
{NILF, 0xff0f000000000000, 0xc00b000000000000, 0x0, // AND IMMEDIATE (low) (NILF R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}},
{NCRK, 0xffff000000000000, 0xb9f5000000000000, 0xf0000000000, // AND WITH COMPLEMENT(32) (NCRK R1,R2,R3)
[8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
{NCGRK, 0xffff000000000000, 0xb9e5000000000000, 0xf0000000000, // AND WITH COMPLEMENT(64) (NCGRK R1,R2,R3)
@ -3338,13 +3339,13 @@ var instFormats = [...]instFormat{
{XC, 0xff00000000000000, 0xd700000000000000, 0x0, // EXCLUSIVE OR (character) (XC D1(L1,B1),D2(B2))
[8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
{XI, 0xff00000000000000, 0x9700000000000000, 0x0, // EXCLUSIVE OR (immediate) (XI D1(B1),I2)
[8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}},
[8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmSigned8_8_15}},
{XIY, 0xff00000000ff0000, 0xeb00000000570000, 0x0, // EXCLUSIVE OR (immediate) (XIY D1(B1),I2)
[8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}},
[8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmSigned8_8_15}},
{XIHF, 0xff0f000000000000, 0xc006000000000000, 0x0, // EXCLUSIVE OR IMMEDIATE (high) (XIHF R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}},
{XILF, 0xff0f000000000000, 0xc007000000000000, 0x0, // EXCLUSIVE OR IMMEDIATE (low) (XILF R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}},
{EX, 0xff00000000000000, 0x4400000000000000, 0x0, // EXECUTE (EX R1,D2(X2,B2))
[8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
{EXRL, 0xff0f000000000000, 0xc600000000000000, 0x0, // EXECUTE RELATIVE LONG (EXRL R1,RI2)
@ -3642,7 +3643,7 @@ var instFormats = [...]instFormat{
{LOCFHR, 0xffff000000000000, 0xb9e0000000000000, 0xf0000000000, // LOAD HIGH ON CONDITION (32) (LOCFHR R1,R2,M3)
[8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}},
{LGFI, 0xff0f000000000000, 0xc001000000000000, 0x0, // LOAD IMMEDIATE (64→32) (LGFI R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}},
{LXDB, 0xff00000000ff0000, 0xed00000000050000, 0xff000000, // LOAD LENGTHENED (long to extended BFP) (LXDB R1,D2(X2,B2))
[8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
{LXDBR, 0xffff000000000000, 0xb305000000000000, 0xff0000000000, // LOAD LENGTHENED (long to extended BFP) (LXDBR R1,R2)
@ -3706,17 +3707,17 @@ var instFormats = [...]instFormat{
{LLGHRL, 0xff0f000000000000, 0xc406000000000000, 0x0, // LOAD LOGICAL HALFWORD RELATIVE LONG(64→16) (LLGHRL R1,RI2)
[8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
{LLIHH, 0xff0f000000000000, 0xa50c000000000000, 0x0, // LOAD LOGICAL IMMEDIATE (high high) (LLIHH R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}},
{LLIHL, 0xff0f000000000000, 0xa50d000000000000, 0x0, // LOAD LOGICAL IMMEDIATE (high low) (LLIHL R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}},
{LLIHF, 0xff0f000000000000, 0xc00e000000000000, 0x0, // LOAD LOGICAL IMMEDIATE (high) (LLIHF R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}},
{LLILH, 0xff0f000000000000, 0xa50e000000000000, 0x0, // LOAD LOGICAL IMMEDIATE (low high) (LLILH R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}},
{LLILL, 0xff0f000000000000, 0xa50f000000000000, 0x0, // LOAD LOGICAL IMMEDIATE (low low) (LLILL R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}},
{LLILF, 0xff0f000000000000, 0xc00f000000000000, 0x0, // LOAD LOGICAL IMMEDIATE (low) (LLILF R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}},
{LLGFRL, 0xff0f000000000000, 0xc40e000000000000, 0x0, // LOAD LOGICAL RELATIVE LONG (64→32) (LLGFRL R1,RI2)
[8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}},
{LLGT, 0xff00000000ff0000, 0xe300000000170000, 0x0, // LOAD LOGICAL THIRTY ONE BITS (64→31) (LLGT R1,D2(X2,B2))
@ -4016,9 +4017,9 @@ var instFormats = [...]instFormat{
{MGH, 0xff00000000ff0000, 0xe3000000003c0000, 0x0, // MULTIPLY HALFWORD (64→16) (MGH R1,D2(X2,B2))
[8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
{MHI, 0xff0f000000000000, 0xa70c000000000000, 0x0, // MULTIPLY HALFWORD IMMEDIATE (32→16) (MHI R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_31}},
{MGHI, 0xff0f000000000000, 0xa70d000000000000, 0x0, // MULTIPLY HALFWORD IMMEDIATE (64→16) (MGHI R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_31}},
{MLG, 0xff00000000ff0000, 0xe300000000860000, 0x0, // MULTIPLY LOGICAL (128→64) (MLG R1,D2(X2,B2))
[8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}},
{MLGR, 0xffff000000000000, 0xb986000000000000, 0xff0000000000, // MULTIPLY LOGICAL (128→64) (MLGR R1,R2)
@ -4050,9 +4051,9 @@ var instFormats = [...]instFormat{
{MSGFR, 0xffff000000000000, 0xb91c000000000000, 0xff0000000000, // MULTIPLY SINGLE (64←32) (MSGFR R1,R2)
[8]*argField{ap_Reg_24_27, ap_Reg_28_31}},
{MSFI, 0xff0f000000000000, 0xc201000000000000, 0x0, // MULTIPLY SINGLE IMMEDIATE (32) (MSFI R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}},
{MSGFI, 0xff0f000000000000, 0xc200000000000000, 0x0, // MULTIPLY SINGLE IMMEDIATE (64←32) (MSGFI R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}},
{MYH, 0xff00000000ff0000, 0xed000000003d0000, 0xf000000, // MULTIPLY UNNORM. (long to ext. high HFP) (MYH R1,R3,D2(X2,B2))
[8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}},
{MYHR, 0xffff000000000000, 0xb33d000000000000, 0xf0000000000, // MULTIPLY UNNORM. (long to ext. high HFP) (MYHR R1,R3,R2)
@ -4100,21 +4101,21 @@ var instFormats = [...]instFormat{
{OC, 0xff00000000000000, 0xd600000000000000, 0x0, // OR (character) (OC D1(L1,B1),D2(B2))
[8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}},
{OI, 0xff00000000000000, 0x9600000000000000, 0x0, // OR (immediate) (OI D1(B1),I2)
[8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}},
[8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmSigned8_8_15}},
{OIY, 0xff00000000ff0000, 0xeb00000000560000, 0x0, // OR (immediate) (OIY D1(B1),I2)
[8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}},
[8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmSigned8_8_15}},
{OIHH, 0xff0f000000000000, 0xa508000000000000, 0x0, // OR IMMEDIATE (high high) (OIHH R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}},
{OIHL, 0xff0f000000000000, 0xa509000000000000, 0x0, // OR IMMEDIATE (high low) (OIHL R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}},
{OIHF, 0xff0f000000000000, 0xc00c000000000000, 0x0, // OR IMMEDIATE (high) (OIHF R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}},
{OILH, 0xff0f000000000000, 0xa50a000000000000, 0x0, // OR IMMEDIATE (low high) (OILH R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}},
{OILL, 0xff0f000000000000, 0xa50b000000000000, 0x0, // OR IMMEDIATE (low low) (OILL R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}},
{OILF, 0xff0f000000000000, 0xc00d000000000000, 0x0, // OR IMMEDIATE (low) (OILF R1,I2)
[8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}},
[8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}},
{OCRK, 0xffff000000000000, 0xb975000000000000, 0xf0000000000, // OR WITH COMPLEMENT (32) (OCRK R1,R2,R3)
[8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}},
{OCGRK, 0xffff000000000000, 0xb965000000000000, 0xf0000000000, // OR WITH COMPLEMENT (64) (OCGRK R1,R2,R3)
@ -4830,13 +4831,13 @@ var instFormats = [...]instFormat{
{VLEB, 0xff00000000ff0000, 0xe700000000000000, 0x0, // VECTOR LOAD ELEMENT (8) (VLEB V1,D2(X2,B2),M3)
[8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
{VLEIH, 0xff00000000ff0000, 0xe700000000410000, 0xf000000000000, // VECTOR LOAD ELEMENT IMMEDIATE (16) (VLEIH V1,I2,M3)
[8]*argField{ap_VecReg_8_11, ap_ImmUnsigned_16_31, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
[8]*argField{ap_VecReg_8_11, ap_ImmSigned16_16_31, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
{VLEIF, 0xff00000000ff0000, 0xe700000000430000, 0xf000000000000, // VECTOR LOAD ELEMENT IMMEDIATE (32) (VLEIF V1,I2,M3)
[8]*argField{ap_VecReg_8_11, ap_ImmUnsigned_16_31, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
[8]*argField{ap_VecReg_8_11, ap_ImmSigned16_16_31, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
{VLEIG, 0xff00000000ff0000, 0xe700000000420000, 0xf000000000000, // VECTOR LOAD ELEMENT IMMEDIATE (64) (VLEIG V1,I2,M3)
[8]*argField{ap_VecReg_8_11, ap_ImmUnsigned_16_31, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
[8]*argField{ap_VecReg_8_11, ap_ImmSigned16_16_31, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
{VLEIB, 0xff00000000ff0000, 0xe700000000400000, 0xf000000000000, // VECTOR LOAD ELEMENT IMMEDIATE (8) (VLEIB V1,I2,M3)
[8]*argField{ap_VecReg_8_11, ap_ImmUnsigned_16_31, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
[8]*argField{ap_VecReg_8_11, ap_ImmSigned16_16_31, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
{VLER, 0xff00000000ff0000, 0xe600000000070000, 0x0, // VECTOR LOAD ELEMENTS REVERSED (VLER V1,D2(X2,B2),M3)
[8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}},
{VFI, 0xff00000000ff0000, 0xe700000000c70000, 0xff0000000000, // VECTOR LOAD FP INTEGER (VFI V1,V2,M3,M4,M5)

2
src/cmd/vendor/modules.txt vendored
View File

@ -16,7 +16,7 @@ github.com/google/pprof/third_party/svgpan
# github.com/ianlancetaylor/demangle v0.0.0-20240312041847-bd984b5ce465
## explicit; go 1.13
github.com/ianlancetaylor/demangle
# golang.org/x/arch v0.10.1-0.20240910142527-7874f23b9c06
# golang.org/x/arch v0.11.1-0.20241106162200-f977c2e4e3f4
## explicit; go 1.18
golang.org/x/arch/arm/armasm
golang.org/x/arch/arm64/arm64asm