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https://github.com/golang/go
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[dev.ssa] cmd/compile: promote byte/word operation
Writing to low 8/16 bits of register creates false dependency Generate 32-bit operations when possible. Change-Id: I8eb6c1c43a66424eec6baa91a660bceb6b80d1d3 Reviewed-on: https://go-review.googlesource.com/19506 Reviewed-by: Keith Randall <khr@golang.org> Run-TryBot: Ilya Tocar <ilya.tocar@intel.com> TryBot-Result: Gobot Gobot <gobot@golang.org>
This commit is contained in:
Ilya Tocar
Keith Randall
parent
6a8a9da572
commit
e96b232993
@ -3793,7 +3793,7 @@ func (s *genState) genValue(v *ssa.Value) {
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case ssa.OpAMD64ADDL:
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asm = x86.ALEAL
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case ssa.OpAMD64ADDW:
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asm = x86.ALEAW
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asm = x86.ALEAL
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}
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p := Prog(asm)
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p.From.Type = obj.TYPE_MEM
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@ -3843,9 +3843,15 @@ func (s *genState) genValue(v *ssa.Value) {
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opregreg(v.Op.Asm(), r, y)
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if neg {
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p := Prog(x86.ANEGQ) // TODO: use correct size? This is mostly a hack until regalloc does 2-address correctly
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if v.Op == ssa.OpAMD64SUBQ {
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p := Prog(x86.ANEGQ)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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} else { // Avoids partial registers write
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p := Prog(x86.ANEGL)
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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}
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}
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case ssa.OpAMD64SUBSS, ssa.OpAMD64SUBSD, ssa.OpAMD64DIVSS, ssa.OpAMD64DIVSD:
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r := regnum(v)
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@ -4035,7 +4041,7 @@ func (s *genState) genValue(v *ssa.Value) {
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case ssa.OpAMD64ADDLconst:
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asm = x86.AINCL
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case ssa.OpAMD64ADDWconst:
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asm = x86.AINCW
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asm = x86.AINCL
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}
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p := Prog(asm)
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p.To.Type = obj.TYPE_REG
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@ -4049,7 +4055,7 @@ func (s *genState) genValue(v *ssa.Value) {
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case ssa.OpAMD64ADDLconst:
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asm = x86.ADECL
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case ssa.OpAMD64ADDWconst:
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asm = x86.ADECW
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asm = x86.ADECL
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}
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p := Prog(asm)
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p.To.Type = obj.TYPE_REG
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@ -4071,7 +4077,7 @@ func (s *genState) genValue(v *ssa.Value) {
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case ssa.OpAMD64ADDLconst:
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asm = x86.ALEAL
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case ssa.OpAMD64ADDWconst:
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asm = x86.ALEAW
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asm = x86.ALEAL
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}
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p := Prog(asm)
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p.From.Type = obj.TYPE_MEM
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@ -4131,7 +4137,7 @@ func (s *genState) genValue(v *ssa.Value) {
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case ssa.OpAMD64SUBLconst:
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asm = x86.AINCL
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case ssa.OpAMD64SUBWconst:
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asm = x86.AINCW
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asm = x86.AINCL
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}
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p := Prog(asm)
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p.To.Type = obj.TYPE_REG
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@ -4144,7 +4150,7 @@ func (s *genState) genValue(v *ssa.Value) {
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case ssa.OpAMD64SUBLconst:
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asm = x86.ADECL
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case ssa.OpAMD64SUBWconst:
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asm = x86.ADECW
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asm = x86.ADECL
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}
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p := Prog(asm)
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p.To.Type = obj.TYPE_REG
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@ -4157,7 +4163,7 @@ func (s *genState) genValue(v *ssa.Value) {
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case ssa.OpAMD64SUBLconst:
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asm = x86.ALEAL
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case ssa.OpAMD64SUBWconst:
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asm = x86.ALEAW
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asm = x86.ALEAL
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}
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p := Prog(asm)
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p.From.Type = obj.TYPE_MEM
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@ -4596,8 +4602,8 @@ func (s *genState) genValue(v *ssa.Value) {
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q := Prog(x86.ASETPS)
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q.To.Type = obj.TYPE_REG
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q.To.Reg = x86.REG_AX
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// TODO AORQ copied from old code generator, why not AORB?
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opregreg(x86.AORQ, regnum(v), x86.REG_AX)
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// ORL avoids partial register write and is smaller than ORQ, used by old compiler
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opregreg(x86.AORL, regnum(v), x86.REG_AX)
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case ssa.OpAMD64SETEQF:
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p := Prog(v.Op.Asm())
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@ -4606,8 +4612,8 @@ func (s *genState) genValue(v *ssa.Value) {
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q := Prog(x86.ASETPC)
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q.To.Type = obj.TYPE_REG
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q.To.Reg = x86.REG_AX
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// TODO AANDQ copied from old code generator, why not AANDB?
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opregreg(x86.AANDQ, regnum(v), x86.REG_AX)
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// ANDL avoids partial register write and is smaller than ANDQ, used by old compiler
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opregreg(x86.AANDL, regnum(v), x86.REG_AX)
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case ssa.OpAMD64InvertFlags:
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v.Fatalf("InvertFlags should never make it to codegen %v", v)
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@ -5019,7 +5025,15 @@ var ssaRegToReg = [...]int16{
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// loadByType returns the load instruction of the given type.
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func loadByType(t ssa.Type) int {
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// For x86, there's no difference between load and store opcodes.
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// Avoid partial register write
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if !t.IsFloat() && t.Size() <= 2 {
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if t.Size() == 1 {
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return x86.AMOVBLZX
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} else {
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return x86.AMOVWLZX
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}
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}
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// Otherwise, there's no difference between load and store opcodes.
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return storeByType(t)
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}
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@ -5059,9 +5073,10 @@ func moveByType(t ssa.Type) int {
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} else {
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switch t.Size() {
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case 1:
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return x86.AMOVB
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// Avoids partial register write
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return x86.AMOVL
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case 2:
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return x86.AMOVW
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return x86.AMOVL
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case 4:
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return x86.AMOVL
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case 8:
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@ -168,21 +168,21 @@ func init() {
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// binary ops
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{name: "ADDQ", argLength: 2, reg: gp21, asm: "ADDQ"}, // arg0 + arg1
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{name: "ADDL", argLength: 2, reg: gp21, asm: "ADDL"}, // arg0 + arg1
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{name: "ADDW", argLength: 2, reg: gp21, asm: "ADDW"}, // arg0 + arg1
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{name: "ADDB", argLength: 2, reg: gp21, asm: "ADDB"}, // arg0 + arg1
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{name: "ADDW", argLength: 2, reg: gp21, asm: "ADDL"}, // arg0 + arg1
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{name: "ADDB", argLength: 2, reg: gp21, asm: "ADDL"}, // arg0 + arg1
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{name: "ADDQconst", argLength: 1, reg: gp11, asm: "ADDQ", aux: "Int64", typ: "UInt64"}, // arg0 + auxint
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{name: "ADDLconst", argLength: 1, reg: gp11, asm: "ADDL", aux: "Int32"}, // arg0 + auxint
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{name: "ADDWconst", argLength: 1, reg: gp11, asm: "ADDW", aux: "Int16"}, // arg0 + auxint
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{name: "ADDBconst", argLength: 1, reg: gp11, asm: "ADDB", aux: "Int8"}, // arg0 + auxint
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{name: "ADDWconst", argLength: 1, reg: gp11, asm: "ADDL", aux: "Int16"}, // arg0 + auxint
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{name: "ADDBconst", argLength: 1, reg: gp11, asm: "ADDL", aux: "Int8"}, // arg0 + auxint
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{name: "SUBQ", argLength: 2, reg: gp21, asm: "SUBQ"}, // arg0 - arg1
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{name: "SUBL", argLength: 2, reg: gp21, asm: "SUBL"}, // arg0 - arg1
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{name: "SUBW", argLength: 2, reg: gp21, asm: "SUBW"}, // arg0 - arg1
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{name: "SUBB", argLength: 2, reg: gp21, asm: "SUBB"}, // arg0 - arg1
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{name: "SUBW", argLength: 2, reg: gp21, asm: "SUBL"}, // arg0 - arg1
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{name: "SUBB", argLength: 2, reg: gp21, asm: "SUBL"}, // arg0 - arg1
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{name: "SUBQconst", argLength: 1, reg: gp11, asm: "SUBQ", aux: "Int64"}, // arg0 - auxint
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{name: "SUBLconst", argLength: 1, reg: gp11, asm: "SUBL", aux: "Int32"}, // arg0 - auxint
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{name: "SUBWconst", argLength: 1, reg: gp11, asm: "SUBW", aux: "Int16"}, // arg0 - auxint
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{name: "SUBBconst", argLength: 1, reg: gp11, asm: "SUBB", aux: "Int8"}, // arg0 - auxint
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{name: "SUBWconst", argLength: 1, reg: gp11, asm: "SUBL", aux: "Int16"}, // arg0 - auxint
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{name: "SUBBconst", argLength: 1, reg: gp11, asm: "SUBL", aux: "Int8"}, // arg0 - auxint
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{name: "MULQ", argLength: 2, reg: gp21, asm: "IMULQ"}, // arg0 * arg1
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{name: "MULL", argLength: 2, reg: gp21, asm: "IMULL"}, // arg0 * arg1
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@ -220,30 +220,30 @@ func init() {
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{name: "ANDQ", argLength: 2, reg: gp21, asm: "ANDQ"}, // arg0 & arg1
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{name: "ANDL", argLength: 2, reg: gp21, asm: "ANDL"}, // arg0 & arg1
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{name: "ANDW", argLength: 2, reg: gp21, asm: "ANDW"}, // arg0 & arg1
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{name: "ANDB", argLength: 2, reg: gp21, asm: "ANDB"}, // arg0 & arg1
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{name: "ANDW", argLength: 2, reg: gp21, asm: "ANDL"}, // arg0 & arg1
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{name: "ANDB", argLength: 2, reg: gp21, asm: "ANDL"}, // arg0 & arg1
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{name: "ANDQconst", argLength: 1, reg: gp11, asm: "ANDQ", aux: "Int64"}, // arg0 & auxint
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{name: "ANDLconst", argLength: 1, reg: gp11, asm: "ANDL", aux: "Int32"}, // arg0 & auxint
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{name: "ANDWconst", argLength: 1, reg: gp11, asm: "ANDW", aux: "Int16"}, // arg0 & auxint
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{name: "ANDBconst", argLength: 1, reg: gp11, asm: "ANDB", aux: "Int8"}, // arg0 & auxint
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{name: "ANDWconst", argLength: 1, reg: gp11, asm: "ANDL", aux: "Int16"}, // arg0 & auxint
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{name: "ANDBconst", argLength: 1, reg: gp11, asm: "ANDL", aux: "Int8"}, // arg0 & auxint
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{name: "ORQ", argLength: 2, reg: gp21, asm: "ORQ"}, // arg0 | arg1
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{name: "ORL", argLength: 2, reg: gp21, asm: "ORL"}, // arg0 | arg1
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{name: "ORW", argLength: 2, reg: gp21, asm: "ORW"}, // arg0 | arg1
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{name: "ORB", argLength: 2, reg: gp21, asm: "ORB"}, // arg0 | arg1
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{name: "ORW", argLength: 2, reg: gp21, asm: "ORL"}, // arg0 | arg1
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{name: "ORB", argLength: 2, reg: gp21, asm: "ORL"}, // arg0 | arg1
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{name: "ORQconst", argLength: 1, reg: gp11, asm: "ORQ", aux: "Int64"}, // arg0 | auxint
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{name: "ORLconst", argLength: 1, reg: gp11, asm: "ORL", aux: "Int32"}, // arg0 | auxint
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{name: "ORWconst", argLength: 1, reg: gp11, asm: "ORW", aux: "Int16"}, // arg0 | auxint
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{name: "ORBconst", argLength: 1, reg: gp11, asm: "ORB", aux: "Int8"}, // arg0 | auxint
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{name: "ORWconst", argLength: 1, reg: gp11, asm: "ORL", aux: "Int16"}, // arg0 | auxint
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{name: "ORBconst", argLength: 1, reg: gp11, asm: "ORL", aux: "Int8"}, // arg0 | auxint
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{name: "XORQ", argLength: 2, reg: gp21, asm: "XORQ"}, // arg0 ^ arg1
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{name: "XORL", argLength: 2, reg: gp21, asm: "XORL"}, // arg0 ^ arg1
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{name: "XORW", argLength: 2, reg: gp21, asm: "XORW"}, // arg0 ^ arg1
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{name: "XORB", argLength: 2, reg: gp21, asm: "XORB"}, // arg0 ^ arg1
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{name: "XORW", argLength: 2, reg: gp21, asm: "XORL"}, // arg0 ^ arg1
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{name: "XORB", argLength: 2, reg: gp21, asm: "XORL"}, // arg0 ^ arg1
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{name: "XORQconst", argLength: 1, reg: gp11, asm: "XORQ", aux: "Int64"}, // arg0 ^ auxint
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{name: "XORLconst", argLength: 1, reg: gp11, asm: "XORL", aux: "Int32"}, // arg0 ^ auxint
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{name: "XORWconst", argLength: 1, reg: gp11, asm: "XORW", aux: "Int16"}, // arg0 ^ auxint
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{name: "XORBconst", argLength: 1, reg: gp11, asm: "XORB", aux: "Int8"}, // arg0 ^ auxint
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{name: "XORWconst", argLength: 1, reg: gp11, asm: "XORL", aux: "Int16"}, // arg0 ^ auxint
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{name: "XORBconst", argLength: 1, reg: gp11, asm: "XORL", aux: "Int8"}, // arg0 ^ auxint
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{name: "CMPQ", argLength: 2, reg: gp2flags, asm: "CMPQ", typ: "Flags"}, // arg0 compare to arg1
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{name: "CMPL", argLength: 2, reg: gp2flags, asm: "CMPL", typ: "Flags"}, // arg0 compare to arg1
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@ -268,12 +268,12 @@ func init() {
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{name: "SHLQ", argLength: 2, reg: gp21shift, asm: "SHLQ"}, // arg0 << arg1, shift amount is mod 64
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{name: "SHLL", argLength: 2, reg: gp21shift, asm: "SHLL"}, // arg0 << arg1, shift amount is mod 32
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{name: "SHLW", argLength: 2, reg: gp21shift, asm: "SHLW"}, // arg0 << arg1, shift amount is mod 32
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{name: "SHLB", argLength: 2, reg: gp21shift, asm: "SHLB"}, // arg0 << arg1, shift amount is mod 32
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{name: "SHLW", argLength: 2, reg: gp21shift, asm: "SHLL"}, // arg0 << arg1, shift amount is mod 32
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{name: "SHLB", argLength: 2, reg: gp21shift, asm: "SHLL"}, // arg0 << arg1, shift amount is mod 32
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{name: "SHLQconst", argLength: 1, reg: gp11, asm: "SHLQ", aux: "Int64"}, // arg0 << auxint, shift amount 0-63
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{name: "SHLLconst", argLength: 1, reg: gp11, asm: "SHLL", aux: "Int32"}, // arg0 << auxint, shift amount 0-31
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{name: "SHLWconst", argLength: 1, reg: gp11, asm: "SHLW", aux: "Int16"}, // arg0 << auxint, shift amount 0-31
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{name: "SHLBconst", argLength: 1, reg: gp11, asm: "SHLB", aux: "Int8"}, // arg0 << auxint, shift amount 0-31
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{name: "SHLWconst", argLength: 1, reg: gp11, asm: "SHLL", aux: "Int16"}, // arg0 << auxint, shift amount 0-31
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{name: "SHLBconst", argLength: 1, reg: gp11, asm: "SHLL", aux: "Int8"}, // arg0 << auxint, shift amount 0-31
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// Note: x86 is weird, the 16 and 8 byte shifts still use all 5 bits of shift amount!
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{name: "SHRQ", argLength: 2, reg: gp21shift, asm: "SHRQ"}, // unsigned arg0 >> arg1, shift amount is mod 64
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@ -302,13 +302,13 @@ func init() {
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// unary ops
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{name: "NEGQ", argLength: 1, reg: gp11, asm: "NEGQ"}, // -arg0
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{name: "NEGL", argLength: 1, reg: gp11, asm: "NEGL"}, // -arg0
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{name: "NEGW", argLength: 1, reg: gp11, asm: "NEGW"}, // -arg0
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{name: "NEGB", argLength: 1, reg: gp11, asm: "NEGB"}, // -arg0
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{name: "NEGW", argLength: 1, reg: gp11, asm: "NEGL"}, // -arg0
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{name: "NEGB", argLength: 1, reg: gp11, asm: "NEGL"}, // -arg0
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{name: "NOTQ", argLength: 1, reg: gp11, asm: "NOTQ"}, // ^arg0
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{name: "NOTL", argLength: 1, reg: gp11, asm: "NOTL"}, // ^arg0
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{name: "NOTW", argLength: 1, reg: gp11, asm: "NOTW"}, // ^arg0
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{name: "NOTB", argLength: 1, reg: gp11, asm: "NOTB"}, // ^arg0
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{name: "NOTW", argLength: 1, reg: gp11, asm: "NOTL"}, // ^arg0
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{name: "NOTB", argLength: 1, reg: gp11, asm: "NOTL"}, // ^arg0
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{name: "SQRTSD", argLength: 1, reg: fp11, asm: "SQRTSD"}, // sqrt(arg0)
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@ -370,10 +370,10 @@ func init() {
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// Note: LEAQ{1,2,4,8} must not have OpSB as either argument.
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// auxint+aux == add auxint and the offset of the symbol in aux (if any) to the effective address
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{name: "MOVBload", argLength: 2, reg: gpload, asm: "MOVB", aux: "SymOff", typ: "UInt8"}, // load byte from arg0+auxint+aux. arg1=mem
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{name: "MOVBload", argLength: 2, reg: gpload, asm: "MOVBLZX", aux: "SymOff", typ: "UInt8"}, // load byte from arg0+auxint+aux. arg1=mem
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{name: "MOVBQSXload", argLength: 2, reg: gpload, asm: "MOVBQSX", aux: "SymOff"}, // ditto, extend to int64
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{name: "MOVBQZXload", argLength: 2, reg: gpload, asm: "MOVBQZX", aux: "SymOff"}, // ditto, extend to uint64
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{name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVW", aux: "SymOff", typ: "UInt16"}, // load 2 bytes from arg0+auxint+aux. arg1=mem
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{name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVWLZX", aux: "SymOff", typ: "UInt16"}, // load 2 bytes from arg0+auxint+aux. arg1=mem
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{name: "MOVWQSXload", argLength: 2, reg: gpload, asm: "MOVWQSX", aux: "SymOff"}, // ditto, extend to int64
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{name: "MOVWQZXload", argLength: 2, reg: gpload, asm: "MOVWQZX", aux: "SymOff"}, // ditto, extend to uint64
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{name: "MOVLload", argLength: 2, reg: gpload, asm: "MOVL", aux: "SymOff", typ: "UInt32"}, // load 4 bytes from arg0+auxint+aux. arg1=mem
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@ -388,8 +388,8 @@ func init() {
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{name: "MOVOstore", argLength: 3, reg: fpstore, asm: "MOVUPS", aux: "SymOff", typ: "Mem"}, // store 16 bytes in arg1 to arg0+auxint+aux. arg2=mem
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// indexed loads/stores
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{name: "MOVBloadidx1", argLength: 3, reg: gploadidx, asm: "MOVB", aux: "SymOff"}, // load a byte from arg0+arg1+auxint+aux. arg2=mem
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{name: "MOVWloadidx2", argLength: 3, reg: gploadidx, asm: "MOVW", aux: "SymOff"}, // load 2 bytes from arg0+2*arg1+auxint+aux. arg2=mem
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{name: "MOVBloadidx1", argLength: 3, reg: gploadidx, asm: "MOVBLZX", aux: "SymOff"}, // load a byte from arg0+arg1+auxint+aux. arg2=mem
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{name: "MOVWloadidx2", argLength: 3, reg: gploadidx, asm: "MOVWLZX", aux: "SymOff"}, // load 2 bytes from arg0+2*arg1+auxint+aux. arg2=mem
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{name: "MOVLloadidx4", argLength: 3, reg: gploadidx, asm: "MOVL", aux: "SymOff"}, // load 4 bytes from arg0+4*arg1+auxint+aux. arg2=mem
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{name: "MOVQloadidx8", argLength: 3, reg: gploadidx, asm: "MOVQ", aux: "SymOff"}, // load 8 bytes from arg0+8*arg1+auxint+aux. arg2=mem
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// TODO: sign-extending indexed loads
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@ -865,7 +865,7 @@ var opcodeTable = [...]opInfo{
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{
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name: "ADDW",
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argLen: 2,
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asm: x86.AADDW,
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asm: x86.AADDL,
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reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -880,7 +880,7 @@ var opcodeTable = [...]opInfo{
|
||||
{
|
||||
name: "ADDB",
|
||||
argLen: 2,
|
||||
asm: x86.AADDB,
|
||||
asm: x86.AADDL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -926,7 +926,7 @@ var opcodeTable = [...]opInfo{
|
||||
name: "ADDWconst",
|
||||
auxType: auxInt16,
|
||||
argLen: 1,
|
||||
asm: x86.AADDW,
|
||||
asm: x86.AADDL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -941,7 +941,7 @@ var opcodeTable = [...]opInfo{
|
||||
name: "ADDBconst",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AADDB,
|
||||
asm: x86.AADDL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -985,7 +985,7 @@ var opcodeTable = [...]opInfo{
|
||||
{
|
||||
name: "SUBW",
|
||||
argLen: 2,
|
||||
asm: x86.ASUBW,
|
||||
asm: x86.ASUBL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -1000,7 +1000,7 @@ var opcodeTable = [...]opInfo{
|
||||
{
|
||||
name: "SUBB",
|
||||
argLen: 2,
|
||||
asm: x86.ASUBB,
|
||||
asm: x86.ASUBL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -1046,7 +1046,7 @@ var opcodeTable = [...]opInfo{
|
||||
name: "SUBWconst",
|
||||
auxType: auxInt16,
|
||||
argLen: 1,
|
||||
asm: x86.ASUBW,
|
||||
asm: x86.ASUBL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -1061,7 +1061,7 @@ var opcodeTable = [...]opInfo{
|
||||
name: "SUBBconst",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.ASUBB,
|
||||
asm: x86.ASUBL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -1539,7 +1539,7 @@ var opcodeTable = [...]opInfo{
|
||||
{
|
||||
name: "ANDW",
|
||||
argLen: 2,
|
||||
asm: x86.AANDW,
|
||||
asm: x86.AANDL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -1554,7 +1554,7 @@ var opcodeTable = [...]opInfo{
|
||||
{
|
||||
name: "ANDB",
|
||||
argLen: 2,
|
||||
asm: x86.AANDB,
|
||||
asm: x86.AANDL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -1600,7 +1600,7 @@ var opcodeTable = [...]opInfo{
|
||||
name: "ANDWconst",
|
||||
auxType: auxInt16,
|
||||
argLen: 1,
|
||||
asm: x86.AANDW,
|
||||
asm: x86.AANDL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -1615,7 +1615,7 @@ var opcodeTable = [...]opInfo{
|
||||
name: "ANDBconst",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AANDB,
|
||||
asm: x86.AANDL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -1659,7 +1659,7 @@ var opcodeTable = [...]opInfo{
|
||||
{
|
||||
name: "ORW",
|
||||
argLen: 2,
|
||||
asm: x86.AORW,
|
||||
asm: x86.AORL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -1674,7 +1674,7 @@ var opcodeTable = [...]opInfo{
|
||||
{
|
||||
name: "ORB",
|
||||
argLen: 2,
|
||||
asm: x86.AORB,
|
||||
asm: x86.AORL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -1720,7 +1720,7 @@ var opcodeTable = [...]opInfo{
|
||||
name: "ORWconst",
|
||||
auxType: auxInt16,
|
||||
argLen: 1,
|
||||
asm: x86.AORW,
|
||||
asm: x86.AORL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -1735,7 +1735,7 @@ var opcodeTable = [...]opInfo{
|
||||
name: "ORBconst",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AORB,
|
||||
asm: x86.AORL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -1779,7 +1779,7 @@ var opcodeTable = [...]opInfo{
|
||||
{
|
||||
name: "XORW",
|
||||
argLen: 2,
|
||||
asm: x86.AXORW,
|
||||
asm: x86.AXORL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -1794,7 +1794,7 @@ var opcodeTable = [...]opInfo{
|
||||
{
|
||||
name: "XORB",
|
||||
argLen: 2,
|
||||
asm: x86.AXORB,
|
||||
asm: x86.AXORL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -1840,7 +1840,7 @@ var opcodeTable = [...]opInfo{
|
||||
name: "XORWconst",
|
||||
auxType: auxInt16,
|
||||
argLen: 1,
|
||||
asm: x86.AXORW,
|
||||
asm: x86.AXORL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -1855,7 +1855,7 @@ var opcodeTable = [...]opInfo{
|
||||
name: "XORBconst",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.AXORB,
|
||||
asm: x86.AXORL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -2151,7 +2151,7 @@ var opcodeTable = [...]opInfo{
|
||||
{
|
||||
name: "SHLW",
|
||||
argLen: 2,
|
||||
asm: x86.ASHLW,
|
||||
asm: x86.ASHLL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 2}, // .CX
|
||||
@ -2166,7 +2166,7 @@ var opcodeTable = [...]opInfo{
|
||||
{
|
||||
name: "SHLB",
|
||||
argLen: 2,
|
||||
asm: x86.ASHLB,
|
||||
asm: x86.ASHLL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 2}, // .CX
|
||||
@ -2212,7 +2212,7 @@ var opcodeTable = [...]opInfo{
|
||||
name: "SHLWconst",
|
||||
auxType: auxInt16,
|
||||
argLen: 1,
|
||||
asm: x86.ASHLW,
|
||||
asm: x86.ASHLL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -2227,7 +2227,7 @@ var opcodeTable = [...]opInfo{
|
||||
name: "SHLBconst",
|
||||
auxType: auxInt8,
|
||||
argLen: 1,
|
||||
asm: x86.ASHLB,
|
||||
asm: x86.ASHLL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -2569,7 +2569,7 @@ var opcodeTable = [...]opInfo{
|
||||
{
|
||||
name: "NEGW",
|
||||
argLen: 1,
|
||||
asm: x86.ANEGW,
|
||||
asm: x86.ANEGL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -2583,7 +2583,7 @@ var opcodeTable = [...]opInfo{
|
||||
{
|
||||
name: "NEGB",
|
||||
argLen: 1,
|
||||
asm: x86.ANEGB,
|
||||
asm: x86.ANEGL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -2625,7 +2625,7 @@ var opcodeTable = [...]opInfo{
|
||||
{
|
||||
name: "NOTW",
|
||||
argLen: 1,
|
||||
asm: x86.ANOTW,
|
||||
asm: x86.ANOTL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -2639,7 +2639,7 @@ var opcodeTable = [...]opInfo{
|
||||
{
|
||||
name: "NOTB",
|
||||
argLen: 1,
|
||||
asm: x86.ANOTB,
|
||||
asm: x86.ANOTL,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -3243,7 +3243,7 @@ var opcodeTable = [...]opInfo{
|
||||
name: "MOVBload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 2,
|
||||
asm: x86.AMOVB,
|
||||
asm: x86.AMOVBLZX,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
||||
@ -3285,7 +3285,7 @@ var opcodeTable = [...]opInfo{
|
||||
name: "MOVWload",
|
||||
auxType: auxSymOff,
|
||||
argLen: 2,
|
||||
asm: x86.AMOVW,
|
||||
asm: x86.AMOVWLZX,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
|
||||
@ -3457,7 +3457,7 @@ var opcodeTable = [...]opInfo{
|
||||
name: "MOVBloadidx1",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
asm: x86.AMOVB,
|
||||
asm: x86.AMOVBLZX,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
@ -3472,7 +3472,7 @@ var opcodeTable = [...]opInfo{
|
||||
name: "MOVWloadidx2",
|
||||
auxType: auxSymOff,
|
||||
argLen: 3,
|
||||
asm: x86.AMOVW,
|
||||
asm: x86.AMOVWLZX,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
|
||||
|
||||
Loading…
Reference in New Issue
Block a user