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[dev.ssa] cmd/compile: promote byte/word operation

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Writing to low 8/16 bits of register creates false dependency
Generate 32-bit operations when possible.

Change-Id: I8eb6c1c43a66424eec6baa91a660bceb6b80d1d3
Reviewed-on: https://go-review.googlesource.com/19506
Reviewed-by: Keith Randall <khr@golang.org>
Run-TryBot: Ilya Tocar <ilya.tocar@intel.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
This commit is contained in:
Ilya Tocar 2016-02-15 17:01:26 +03:00 committed by Keith Randall
parent 6a8a9da572
commit e96b232993
3 changed files with 112 additions and 97 deletions
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49
src/cmd/compile/internal/gc/ssa.go
View File

@ -3793,7 +3793,7 @@ func (s *genState) genValue(v *ssa.Value) {
case ssa.OpAMD64ADDL: case ssa.OpAMD64ADDL:
asm = x86.ALEAL asm = x86.ALEAL
case ssa.OpAMD64ADDW: case ssa.OpAMD64ADDW:
asm = x86.ALEAW asm = x86.ALEAL
} }
p := Prog(asm) p := Prog(asm)
p.From.Type = obj.TYPE_MEM p.From.Type = obj.TYPE_MEM
@ -3843,9 +3843,15 @@ func (s *genState) genValue(v *ssa.Value) {
opregreg(v.Op.Asm(), r, y) opregreg(v.Op.Asm(), r, y)
if neg { if neg {
p := Prog(x86.ANEGQ) // TODO: use correct size? This is mostly a hack until regalloc does 2-address correctly if v.Op == ssa.OpAMD64SUBQ {
p.To.Type = obj.TYPE_REG p := Prog(x86.ANEGQ)
p.To.Reg = r p.To.Type = obj.TYPE_REG
p.To.Reg = r
} else { // Avoids partial registers write
p := Prog(x86.ANEGL)
p.To.Type = obj.TYPE_REG
p.To.Reg = r
}
} }
case ssa.OpAMD64SUBSS, ssa.OpAMD64SUBSD, ssa.OpAMD64DIVSS, ssa.OpAMD64DIVSD: case ssa.OpAMD64SUBSS, ssa.OpAMD64SUBSD, ssa.OpAMD64DIVSS, ssa.OpAMD64DIVSD:
r := regnum(v) r := regnum(v)
@ -4035,7 +4041,7 @@ func (s *genState) genValue(v *ssa.Value) {
case ssa.OpAMD64ADDLconst: case ssa.OpAMD64ADDLconst:
asm = x86.AINCL asm = x86.AINCL
case ssa.OpAMD64ADDWconst: case ssa.OpAMD64ADDWconst:
asm = x86.AINCW asm = x86.AINCL
} }
p := Prog(asm) p := Prog(asm)
p.To.Type = obj.TYPE_REG p.To.Type = obj.TYPE_REG
@ -4049,7 +4055,7 @@ func (s *genState) genValue(v *ssa.Value) {
case ssa.OpAMD64ADDLconst: case ssa.OpAMD64ADDLconst:
asm = x86.ADECL asm = x86.ADECL
case ssa.OpAMD64ADDWconst: case ssa.OpAMD64ADDWconst:
asm = x86.ADECW asm = x86.ADECL
} }
p := Prog(asm) p := Prog(asm)
p.To.Type = obj.TYPE_REG p.To.Type = obj.TYPE_REG
@ -4071,7 +4077,7 @@ func (s *genState) genValue(v *ssa.Value) {
case ssa.OpAMD64ADDLconst: case ssa.OpAMD64ADDLconst:
asm = x86.ALEAL asm = x86.ALEAL
case ssa.OpAMD64ADDWconst: case ssa.OpAMD64ADDWconst:
asm = x86.ALEAW asm = x86.ALEAL
} }
p := Prog(asm) p := Prog(asm)
p.From.Type = obj.TYPE_MEM p.From.Type = obj.TYPE_MEM
@ -4131,7 +4137,7 @@ func (s *genState) genValue(v *ssa.Value) {
case ssa.OpAMD64SUBLconst: case ssa.OpAMD64SUBLconst:
asm = x86.AINCL asm = x86.AINCL
case ssa.OpAMD64SUBWconst: case ssa.OpAMD64SUBWconst:
asm = x86.AINCW asm = x86.AINCL
} }
p := Prog(asm) p := Prog(asm)
p.To.Type = obj.TYPE_REG p.To.Type = obj.TYPE_REG
@ -4144,7 +4150,7 @@ func (s *genState) genValue(v *ssa.Value) {
case ssa.OpAMD64SUBLconst: case ssa.OpAMD64SUBLconst:
asm = x86.ADECL asm = x86.ADECL
case ssa.OpAMD64SUBWconst: case ssa.OpAMD64SUBWconst:
asm = x86.ADECW asm = x86.ADECL
} }
p := Prog(asm) p := Prog(asm)
p.To.Type = obj.TYPE_REG p.To.Type = obj.TYPE_REG
@ -4157,7 +4163,7 @@ func (s *genState) genValue(v *ssa.Value) {
case ssa.OpAMD64SUBLconst: case ssa.OpAMD64SUBLconst:
asm = x86.ALEAL asm = x86.ALEAL
case ssa.OpAMD64SUBWconst: case ssa.OpAMD64SUBWconst:
asm = x86.ALEAW asm = x86.ALEAL
} }
p := Prog(asm) p := Prog(asm)
p.From.Type = obj.TYPE_MEM p.From.Type = obj.TYPE_MEM
@ -4596,8 +4602,8 @@ func (s *genState) genValue(v *ssa.Value) {
q := Prog(x86.ASETPS) q := Prog(x86.ASETPS)
q.To.Type = obj.TYPE_REG q.To.Type = obj.TYPE_REG
q.To.Reg = x86.REG_AX q.To.Reg = x86.REG_AX
// TODO AORQ copied from old code generator, why not AORB? // ORL avoids partial register write and is smaller than ORQ, used by old compiler
opregreg(x86.AORQ, regnum(v), x86.REG_AX) opregreg(x86.AORL, regnum(v), x86.REG_AX)
case ssa.OpAMD64SETEQF: case ssa.OpAMD64SETEQF:
p := Prog(v.Op.Asm()) p := Prog(v.Op.Asm())
@ -4606,8 +4612,8 @@ func (s *genState) genValue(v *ssa.Value) {
q := Prog(x86.ASETPC) q := Prog(x86.ASETPC)
q.To.Type = obj.TYPE_REG q.To.Type = obj.TYPE_REG
q.To.Reg = x86.REG_AX q.To.Reg = x86.REG_AX
// TODO AANDQ copied from old code generator, why not AANDB? // ANDL avoids partial register write and is smaller than ANDQ, used by old compiler
opregreg(x86.AANDQ, regnum(v), x86.REG_AX) opregreg(x86.AANDL, regnum(v), x86.REG_AX)
case ssa.OpAMD64InvertFlags: case ssa.OpAMD64InvertFlags:
v.Fatalf("InvertFlags should never make it to codegen %v", v) v.Fatalf("InvertFlags should never make it to codegen %v", v)
@ -5019,7 +5025,15 @@ var ssaRegToReg = [...]int16{
// loadByType returns the load instruction of the given type. // loadByType returns the load instruction of the given type.
func loadByType(t ssa.Type) int { func loadByType(t ssa.Type) int {
// For x86, there's no difference between load and store opcodes. // Avoid partial register write
if !t.IsFloat() && t.Size() <= 2 {
if t.Size() == 1 {
return x86.AMOVBLZX
} else {
return x86.AMOVWLZX
}
}
// Otherwise, there's no difference between load and store opcodes.
return storeByType(t) return storeByType(t)
} }
@ -5059,9 +5073,10 @@ func moveByType(t ssa.Type) int {
} else { } else {
switch t.Size() { switch t.Size() {
case 1: case 1:
return x86.AMOVB // Avoids partial register write
return x86.AMOVL
case 2: case 2:
return x86.AMOVW return x86.AMOVL
case 4: case 4:
return x86.AMOVL return x86.AMOVL
case 8: case 8:

96
src/cmd/compile/internal/ssa/gen/AMD64Ops.go
View File

@ -168,21 +168,21 @@ func init() {
// binary ops // binary ops
{name: "ADDQ", argLength: 2, reg: gp21, asm: "ADDQ"}, // arg0 + arg1 {name: "ADDQ", argLength: 2, reg: gp21, asm: "ADDQ"}, // arg0 + arg1
{name: "ADDL", argLength: 2, reg: gp21, asm: "ADDL"}, // arg0 + arg1 {name: "ADDL", argLength: 2, reg: gp21, asm: "ADDL"}, // arg0 + arg1
{name: "ADDW", argLength: 2, reg: gp21, asm: "ADDW"}, // arg0 + arg1 {name: "ADDW", argLength: 2, reg: gp21, asm: "ADDL"}, // arg0 + arg1
{name: "ADDB", argLength: 2, reg: gp21, asm: "ADDB"}, // arg0 + arg1 {name: "ADDB", argLength: 2, reg: gp21, asm: "ADDL"}, // arg0 + arg1
{name: "ADDQconst", argLength: 1, reg: gp11, asm: "ADDQ", aux: "Int64", typ: "UInt64"}, // arg0 + auxint {name: "ADDQconst", argLength: 1, reg: gp11, asm: "ADDQ", aux: "Int64", typ: "UInt64"}, // arg0 + auxint
{name: "ADDLconst", argLength: 1, reg: gp11, asm: "ADDL", aux: "Int32"}, // arg0 + auxint {name: "ADDLconst", argLength: 1, reg: gp11, asm: "ADDL", aux: "Int32"}, // arg0 + auxint
{name: "ADDWconst", argLength: 1, reg: gp11, asm: "ADDW", aux: "Int16"}, // arg0 + auxint {name: "ADDWconst", argLength: 1, reg: gp11, asm: "ADDL", aux: "Int16"}, // arg0 + auxint
{name: "ADDBconst", argLength: 1, reg: gp11, asm: "ADDB", aux: "Int8"}, // arg0 + auxint {name: "ADDBconst", argLength: 1, reg: gp11, asm: "ADDL", aux: "Int8"}, // arg0 + auxint
{name: "SUBQ", argLength: 2, reg: gp21, asm: "SUBQ"}, // arg0 - arg1 {name: "SUBQ", argLength: 2, reg: gp21, asm: "SUBQ"}, // arg0 - arg1
{name: "SUBL", argLength: 2, reg: gp21, asm: "SUBL"}, // arg0 - arg1 {name: "SUBL", argLength: 2, reg: gp21, asm: "SUBL"}, // arg0 - arg1
{name: "SUBW", argLength: 2, reg: gp21, asm: "SUBW"}, // arg0 - arg1 {name: "SUBW", argLength: 2, reg: gp21, asm: "SUBL"}, // arg0 - arg1
{name: "SUBB", argLength: 2, reg: gp21, asm: "SUBB"}, // arg0 - arg1 {name: "SUBB", argLength: 2, reg: gp21, asm: "SUBL"}, // arg0 - arg1
{name: "SUBQconst", argLength: 1, reg: gp11, asm: "SUBQ", aux: "Int64"}, // arg0 - auxint {name: "SUBQconst", argLength: 1, reg: gp11, asm: "SUBQ", aux: "Int64"}, // arg0 - auxint
{name: "SUBLconst", argLength: 1, reg: gp11, asm: "SUBL", aux: "Int32"}, // arg0 - auxint {name: "SUBLconst", argLength: 1, reg: gp11, asm: "SUBL", aux: "Int32"}, // arg0 - auxint
{name: "SUBWconst", argLength: 1, reg: gp11, asm: "SUBW", aux: "Int16"}, // arg0 - auxint {name: "SUBWconst", argLength: 1, reg: gp11, asm: "SUBL", aux: "Int16"}, // arg0 - auxint
{name: "SUBBconst", argLength: 1, reg: gp11, asm: "SUBB", aux: "Int8"}, // arg0 - auxint {name: "SUBBconst", argLength: 1, reg: gp11, asm: "SUBL", aux: "Int8"}, // arg0 - auxint
{name: "MULQ", argLength: 2, reg: gp21, asm: "IMULQ"}, // arg0 * arg1 {name: "MULQ", argLength: 2, reg: gp21, asm: "IMULQ"}, // arg0 * arg1
{name: "MULL", argLength: 2, reg: gp21, asm: "IMULL"}, // arg0 * arg1 {name: "MULL", argLength: 2, reg: gp21, asm: "IMULL"}, // arg0 * arg1
@ -220,30 +220,30 @@ func init() {
{name: "ANDQ", argLength: 2, reg: gp21, asm: "ANDQ"}, // arg0 & arg1 {name: "ANDQ", argLength: 2, reg: gp21, asm: "ANDQ"}, // arg0 & arg1
{name: "ANDL", argLength: 2, reg: gp21, asm: "ANDL"}, // arg0 & arg1 {name: "ANDL", argLength: 2, reg: gp21, asm: "ANDL"}, // arg0 & arg1
{name: "ANDW", argLength: 2, reg: gp21, asm: "ANDW"}, // arg0 & arg1 {name: "ANDW", argLength: 2, reg: gp21, asm: "ANDL"}, // arg0 & arg1
{name: "ANDB", argLength: 2, reg: gp21, asm: "ANDB"}, // arg0 & arg1 {name: "ANDB", argLength: 2, reg: gp21, asm: "ANDL"}, // arg0 & arg1
{name: "ANDQconst", argLength: 1, reg: gp11, asm: "ANDQ", aux: "Int64"}, // arg0 & auxint {name: "ANDQconst", argLength: 1, reg: gp11, asm: "ANDQ", aux: "Int64"}, // arg0 & auxint
{name: "ANDLconst", argLength: 1, reg: gp11, asm: "ANDL", aux: "Int32"}, // arg0 & auxint {name: "ANDLconst", argLength: 1, reg: gp11, asm: "ANDL", aux: "Int32"}, // arg0 & auxint
{name: "ANDWconst", argLength: 1, reg: gp11, asm: "ANDW", aux: "Int16"}, // arg0 & auxint {name: "ANDWconst", argLength: 1, reg: gp11, asm: "ANDL", aux: "Int16"}, // arg0 & auxint
{name: "ANDBconst", argLength: 1, reg: gp11, asm: "ANDB", aux: "Int8"}, // arg0 & auxint {name: "ANDBconst", argLength: 1, reg: gp11, asm: "ANDL", aux: "Int8"}, // arg0 & auxint
{name: "ORQ", argLength: 2, reg: gp21, asm: "ORQ"}, // arg0 | arg1 {name: "ORQ", argLength: 2, reg: gp21, asm: "ORQ"}, // arg0 | arg1
{name: "ORL", argLength: 2, reg: gp21, asm: "ORL"}, // arg0 | arg1 {name: "ORL", argLength: 2, reg: gp21, asm: "ORL"}, // arg0 | arg1
{name: "ORW", argLength: 2, reg: gp21, asm: "ORW"}, // arg0 | arg1 {name: "ORW", argLength: 2, reg: gp21, asm: "ORL"}, // arg0 | arg1
{name: "ORB", argLength: 2, reg: gp21, asm: "ORB"}, // arg0 | arg1 {name: "ORB", argLength: 2, reg: gp21, asm: "ORL"}, // arg0 | arg1
{name: "ORQconst", argLength: 1, reg: gp11, asm: "ORQ", aux: "Int64"}, // arg0 | auxint {name: "ORQconst", argLength: 1, reg: gp11, asm: "ORQ", aux: "Int64"}, // arg0 | auxint
{name: "ORLconst", argLength: 1, reg: gp11, asm: "ORL", aux: "Int32"}, // arg0 | auxint {name: "ORLconst", argLength: 1, reg: gp11, asm: "ORL", aux: "Int32"}, // arg0 | auxint
{name: "ORWconst", argLength: 1, reg: gp11, asm: "ORW", aux: "Int16"}, // arg0 | auxint {name: "ORWconst", argLength: 1, reg: gp11, asm: "ORL", aux: "Int16"}, // arg0 | auxint
{name: "ORBconst", argLength: 1, reg: gp11, asm: "ORB", aux: "Int8"}, // arg0 | auxint {name: "ORBconst", argLength: 1, reg: gp11, asm: "ORL", aux: "Int8"}, // arg0 | auxint
{name: "XORQ", argLength: 2, reg: gp21, asm: "XORQ"}, // arg0 ^ arg1 {name: "XORQ", argLength: 2, reg: gp21, asm: "XORQ"}, // arg0 ^ arg1
{name: "XORL", argLength: 2, reg: gp21, asm: "XORL"}, // arg0 ^ arg1 {name: "XORL", argLength: 2, reg: gp21, asm: "XORL"}, // arg0 ^ arg1
{name: "XORW", argLength: 2, reg: gp21, asm: "XORW"}, // arg0 ^ arg1 {name: "XORW", argLength: 2, reg: gp21, asm: "XORL"}, // arg0 ^ arg1
{name: "XORB", argLength: 2, reg: gp21, asm: "XORB"}, // arg0 ^ arg1 {name: "XORB", argLength: 2, reg: gp21, asm: "XORL"}, // arg0 ^ arg1
{name: "XORQconst", argLength: 1, reg: gp11, asm: "XORQ", aux: "Int64"}, // arg0 ^ auxint {name: "XORQconst", argLength: 1, reg: gp11, asm: "XORQ", aux: "Int64"}, // arg0 ^ auxint
{name: "XORLconst", argLength: 1, reg: gp11, asm: "XORL", aux: "Int32"}, // arg0 ^ auxint {name: "XORLconst", argLength: 1, reg: gp11, asm: "XORL", aux: "Int32"}, // arg0 ^ auxint
{name: "XORWconst", argLength: 1, reg: gp11, asm: "XORW", aux: "Int16"}, // arg0 ^ auxint {name: "XORWconst", argLength: 1, reg: gp11, asm: "XORL", aux: "Int16"}, // arg0 ^ auxint
{name: "XORBconst", argLength: 1, reg: gp11, asm: "XORB", aux: "Int8"}, // arg0 ^ auxint {name: "XORBconst", argLength: 1, reg: gp11, asm: "XORL", aux: "Int8"}, // arg0 ^ auxint
{name: "CMPQ", argLength: 2, reg: gp2flags, asm: "CMPQ", typ: "Flags"}, // arg0 compare to arg1 {name: "CMPQ", argLength: 2, reg: gp2flags, asm: "CMPQ", typ: "Flags"}, // arg0 compare to arg1
{name: "CMPL", argLength: 2, reg: gp2flags, asm: "CMPL", typ: "Flags"}, // arg0 compare to arg1 {name: "CMPL", argLength: 2, reg: gp2flags, asm: "CMPL", typ: "Flags"}, // arg0 compare to arg1
@ -268,12 +268,12 @@ func init() {
{name: "SHLQ", argLength: 2, reg: gp21shift, asm: "SHLQ"}, // arg0 << arg1, shift amount is mod 64 {name: "SHLQ", argLength: 2, reg: gp21shift, asm: "SHLQ"}, // arg0 << arg1, shift amount is mod 64
{name: "SHLL", argLength: 2, reg: gp21shift, asm: "SHLL"}, // arg0 << arg1, shift amount is mod 32 {name: "SHLL", argLength: 2, reg: gp21shift, asm: "SHLL"}, // arg0 << arg1, shift amount is mod 32
{name: "SHLW", argLength: 2, reg: gp21shift, asm: "SHLW"}, // arg0 << arg1, shift amount is mod 32 {name: "SHLW", argLength: 2, reg: gp21shift, asm: "SHLL"}, // arg0 << arg1, shift amount is mod 32
{name: "SHLB", argLength: 2, reg: gp21shift, asm: "SHLB"}, // arg0 << arg1, shift amount is mod 32 {name: "SHLB", argLength: 2, reg: gp21shift, asm: "SHLL"}, // arg0 << arg1, shift amount is mod 32
{name: "SHLQconst", argLength: 1, reg: gp11, asm: "SHLQ", aux: "Int64"}, // arg0 << auxint, shift amount 0-63 {name: "SHLQconst", argLength: 1, reg: gp11, asm: "SHLQ", aux: "Int64"}, // arg0 << auxint, shift amount 0-63
{name: "SHLLconst", argLength: 1, reg: gp11, asm: "SHLL", aux: "Int32"}, // arg0 << auxint, shift amount 0-31 {name: "SHLLconst", argLength: 1, reg: gp11, asm: "SHLL", aux: "Int32"}, // arg0 << auxint, shift amount 0-31
{name: "SHLWconst", argLength: 1, reg: gp11, asm: "SHLW", aux: "Int16"}, // arg0 << auxint, shift amount 0-31 {name: "SHLWconst", argLength: 1, reg: gp11, asm: "SHLL", aux: "Int16"}, // arg0 << auxint, shift amount 0-31
{name: "SHLBconst", argLength: 1, reg: gp11, asm: "SHLB", aux: "Int8"}, // arg0 << auxint, shift amount 0-31 {name: "SHLBconst", argLength: 1, reg: gp11, asm: "SHLL", aux: "Int8"}, // arg0 << auxint, shift amount 0-31
// Note: x86 is weird, the 16 and 8 byte shifts still use all 5 bits of shift amount! // Note: x86 is weird, the 16 and 8 byte shifts still use all 5 bits of shift amount!
{name: "SHRQ", argLength: 2, reg: gp21shift, asm: "SHRQ"}, // unsigned arg0 >> arg1, shift amount is mod 64 {name: "SHRQ", argLength: 2, reg: gp21shift, asm: "SHRQ"}, // unsigned arg0 >> arg1, shift amount is mod 64
@ -302,13 +302,13 @@ func init() {
// unary ops // unary ops
{name: "NEGQ", argLength: 1, reg: gp11, asm: "NEGQ"}, // -arg0 {name: "NEGQ", argLength: 1, reg: gp11, asm: "NEGQ"}, // -arg0
{name: "NEGL", argLength: 1, reg: gp11, asm: "NEGL"}, // -arg0 {name: "NEGL", argLength: 1, reg: gp11, asm: "NEGL"}, // -arg0
{name: "NEGW", argLength: 1, reg: gp11, asm: "NEGW"}, // -arg0 {name: "NEGW", argLength: 1, reg: gp11, asm: "NEGL"}, // -arg0
{name: "NEGB", argLength: 1, reg: gp11, asm: "NEGB"}, // -arg0 {name: "NEGB", argLength: 1, reg: gp11, asm: "NEGL"}, // -arg0
{name: "NOTQ", argLength: 1, reg: gp11, asm: "NOTQ"}, // ^arg0 {name: "NOTQ", argLength: 1, reg: gp11, asm: "NOTQ"}, // ^arg0
{name: "NOTL", argLength: 1, reg: gp11, asm: "NOTL"}, // ^arg0 {name: "NOTL", argLength: 1, reg: gp11, asm: "NOTL"}, // ^arg0
{name: "NOTW", argLength: 1, reg: gp11, asm: "NOTW"}, // ^arg0 {name: "NOTW", argLength: 1, reg: gp11, asm: "NOTL"}, // ^arg0
{name: "NOTB", argLength: 1, reg: gp11, asm: "NOTB"}, // ^arg0 {name: "NOTB", argLength: 1, reg: gp11, asm: "NOTL"}, // ^arg0
{name: "SQRTSD", argLength: 1, reg: fp11, asm: "SQRTSD"}, // sqrt(arg0) {name: "SQRTSD", argLength: 1, reg: fp11, asm: "SQRTSD"}, // sqrt(arg0)
@ -370,28 +370,28 @@ func init() {
// Note: LEAQ{1,2,4,8} must not have OpSB as either argument. // Note: LEAQ{1,2,4,8} must not have OpSB as either argument.
// auxint+aux == add auxint and the offset of the symbol in aux (if any) to the effective address // auxint+aux == add auxint and the offset of the symbol in aux (if any) to the effective address
{name: "MOVBload", argLength: 2, reg: gpload, asm: "MOVB", aux: "SymOff", typ: "UInt8"}, // load byte from arg0+auxint+aux. arg1=mem {name: "MOVBload", argLength: 2, reg: gpload, asm: "MOVBLZX", aux: "SymOff", typ: "UInt8"}, // load byte from arg0+auxint+aux. arg1=mem
{name: "MOVBQSXload", argLength: 2, reg: gpload, asm: "MOVBQSX", aux: "SymOff"}, // ditto, extend to int64 {name: "MOVBQSXload", argLength: 2, reg: gpload, asm: "MOVBQSX", aux: "SymOff"}, // ditto, extend to int64
{name: "MOVBQZXload", argLength: 2, reg: gpload, asm: "MOVBQZX", aux: "SymOff"}, // ditto, extend to uint64 {name: "MOVBQZXload", argLength: 2, reg: gpload, asm: "MOVBQZX", aux: "SymOff"}, // ditto, extend to uint64
{name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVW", aux: "SymOff", typ: "UInt16"}, // load 2 bytes from arg0+auxint+aux. arg1=mem {name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVWLZX", aux: "SymOff", typ: "UInt16"}, // load 2 bytes from arg0+auxint+aux. arg1=mem
{name: "MOVWQSXload", argLength: 2, reg: gpload, asm: "MOVWQSX", aux: "SymOff"}, // ditto, extend to int64 {name: "MOVWQSXload", argLength: 2, reg: gpload, asm: "MOVWQSX", aux: "SymOff"}, // ditto, extend to int64
{name: "MOVWQZXload", argLength: 2, reg: gpload, asm: "MOVWQZX", aux: "SymOff"}, // ditto, extend to uint64 {name: "MOVWQZXload", argLength: 2, reg: gpload, asm: "MOVWQZX", aux: "SymOff"}, // ditto, extend to uint64
{name: "MOVLload", argLength: 2, reg: gpload, asm: "MOVL", aux: "SymOff", typ: "UInt32"}, // load 4 bytes from arg0+auxint+aux. arg1=mem {name: "MOVLload", argLength: 2, reg: gpload, asm: "MOVL", aux: "SymOff", typ: "UInt32"}, // load 4 bytes from arg0+auxint+aux. arg1=mem
{name: "MOVLQSXload", argLength: 2, reg: gpload, asm: "MOVLQSX", aux: "SymOff"}, // ditto, extend to int64 {name: "MOVLQSXload", argLength: 2, reg: gpload, asm: "MOVLQSX", aux: "SymOff"}, // ditto, extend to int64
{name: "MOVLQZXload", argLength: 2, reg: gpload, asm: "MOVLQZX", aux: "SymOff"}, // ditto, extend to uint64 {name: "MOVLQZXload", argLength: 2, reg: gpload, asm: "MOVLQZX", aux: "SymOff"}, // ditto, extend to uint64
{name: "MOVQload", argLength: 2, reg: gpload, asm: "MOVQ", aux: "SymOff", typ: "UInt64"}, // load 8 bytes from arg0+auxint+aux. arg1=mem {name: "MOVQload", argLength: 2, reg: gpload, asm: "MOVQ", aux: "SymOff", typ: "UInt64"}, // load 8 bytes from arg0+auxint+aux. arg1=mem
{name: "MOVBstore", argLength: 3, reg: gpstore, asm: "MOVB", aux: "SymOff", typ: "Mem"}, // store byte in arg1 to arg0+auxint+aux. arg2=mem {name: "MOVBstore", argLength: 3, reg: gpstore, asm: "MOVB", aux: "SymOff", typ: "Mem"}, // store byte in arg1 to arg0+auxint+aux. arg2=mem
{name: "MOVWstore", argLength: 3, reg: gpstore, asm: "MOVW", aux: "SymOff", typ: "Mem"}, // store 2 bytes in arg1 to arg0+auxint+aux. arg2=mem {name: "MOVWstore", argLength: 3, reg: gpstore, asm: "MOVW", aux: "SymOff", typ: "Mem"}, // store 2 bytes in arg1 to arg0+auxint+aux. arg2=mem
{name: "MOVLstore", argLength: 3, reg: gpstore, asm: "MOVL", aux: "SymOff", typ: "Mem"}, // store 4 bytes in arg1 to arg0+auxint+aux. arg2=mem {name: "MOVLstore", argLength: 3, reg: gpstore, asm: "MOVL", aux: "SymOff", typ: "Mem"}, // store 4 bytes in arg1 to arg0+auxint+aux. arg2=mem
{name: "MOVQstore", argLength: 3, reg: gpstore, asm: "MOVQ", aux: "SymOff", typ: "Mem"}, // store 8 bytes in arg1 to arg0+auxint+aux. arg2=mem {name: "MOVQstore", argLength: 3, reg: gpstore, asm: "MOVQ", aux: "SymOff", typ: "Mem"}, // store 8 bytes in arg1 to arg0+auxint+aux. arg2=mem
{name: "MOVOload", argLength: 2, reg: fpload, asm: "MOVUPS", aux: "SymOff", typ: "Int128"}, // load 16 bytes from arg0+auxint+aux. arg1=mem {name: "MOVOload", argLength: 2, reg: fpload, asm: "MOVUPS", aux: "SymOff", typ: "Int128"}, // load 16 bytes from arg0+auxint+aux. arg1=mem
{name: "MOVOstore", argLength: 3, reg: fpstore, asm: "MOVUPS", aux: "SymOff", typ: "Mem"}, // store 16 bytes in arg1 to arg0+auxint+aux. arg2=mem {name: "MOVOstore", argLength: 3, reg: fpstore, asm: "MOVUPS", aux: "SymOff", typ: "Mem"}, // store 16 bytes in arg1 to arg0+auxint+aux. arg2=mem
// indexed loads/stores // indexed loads/stores
{name: "MOVBloadidx1", argLength: 3, reg: gploadidx, asm: "MOVB", aux: "SymOff"}, // load a byte from arg0+arg1+auxint+aux. arg2=mem {name: "MOVBloadidx1", argLength: 3, reg: gploadidx, asm: "MOVBLZX", aux: "SymOff"}, // load a byte from arg0+arg1+auxint+aux. arg2=mem
{name: "MOVWloadidx2", argLength: 3, reg: gploadidx, asm: "MOVW", aux: "SymOff"}, // load 2 bytes from arg0+2*arg1+auxint+aux. arg2=mem {name: "MOVWloadidx2", argLength: 3, reg: gploadidx, asm: "MOVWLZX", aux: "SymOff"}, // load 2 bytes from arg0+2*arg1+auxint+aux. arg2=mem
{name: "MOVLloadidx4", argLength: 3, reg: gploadidx, asm: "MOVL", aux: "SymOff"}, // load 4 bytes from arg0+4*arg1+auxint+aux. arg2=mem {name: "MOVLloadidx4", argLength: 3, reg: gploadidx, asm: "MOVL", aux: "SymOff"}, // load 4 bytes from arg0+4*arg1+auxint+aux. arg2=mem
{name: "MOVQloadidx8", argLength: 3, reg: gploadidx, asm: "MOVQ", aux: "SymOff"}, // load 8 bytes from arg0+8*arg1+auxint+aux. arg2=mem {name: "MOVQloadidx8", argLength: 3, reg: gploadidx, asm: "MOVQ", aux: "SymOff"}, // load 8 bytes from arg0+8*arg1+auxint+aux. arg2=mem
// TODO: sign-extending indexed loads // TODO: sign-extending indexed loads
{name: "MOVBstoreidx1", argLength: 4, reg: gpstoreidx, asm: "MOVB", aux: "SymOff"}, // store byte in arg2 to arg0+arg1+auxint+aux. arg3=mem {name: "MOVBstoreidx1", argLength: 4, reg: gpstoreidx, asm: "MOVB", aux: "SymOff"}, // store byte in arg2 to arg0+arg1+auxint+aux. arg3=mem
{name: "MOVWstoreidx2", argLength: 4, reg: gpstoreidx, asm: "MOVW", aux: "SymOff"}, // store 2 bytes in arg2 to arg0+2*arg1+auxint+aux. arg3=mem {name: "MOVWstoreidx2", argLength: 4, reg: gpstoreidx, asm: "MOVW", aux: "SymOff"}, // store 2 bytes in arg2 to arg0+2*arg1+auxint+aux. arg3=mem

64
src/cmd/compile/internal/ssa/opGen.go
View File

@ -865,7 +865,7 @@ var opcodeTable = [...]opInfo{
{ {
name: "ADDW", name: "ADDW",
argLen: 2, argLen: 2,
asm: x86.AADDW, asm: x86.AADDL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -880,7 +880,7 @@ var opcodeTable = [...]opInfo{
{ {
name: "ADDB", name: "ADDB",
argLen: 2, argLen: 2,
asm: x86.AADDB, asm: x86.AADDL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -926,7 +926,7 @@ var opcodeTable = [...]opInfo{
name: "ADDWconst", name: "ADDWconst",
auxType: auxInt16, auxType: auxInt16,
argLen: 1, argLen: 1,
asm: x86.AADDW, asm: x86.AADDL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -941,7 +941,7 @@ var opcodeTable = [...]opInfo{
name: "ADDBconst", name: "ADDBconst",
auxType: auxInt8, auxType: auxInt8,
argLen: 1, argLen: 1,
asm: x86.AADDB, asm: x86.AADDL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -985,7 +985,7 @@ var opcodeTable = [...]opInfo{
{ {
name: "SUBW", name: "SUBW",
argLen: 2, argLen: 2,
asm: x86.ASUBW, asm: x86.ASUBL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -1000,7 +1000,7 @@ var opcodeTable = [...]opInfo{
{ {
name: "SUBB", name: "SUBB",
argLen: 2, argLen: 2,
asm: x86.ASUBB, asm: x86.ASUBL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -1046,7 +1046,7 @@ var opcodeTable = [...]opInfo{
name: "SUBWconst", name: "SUBWconst",
auxType: auxInt16, auxType: auxInt16,
argLen: 1, argLen: 1,
asm: x86.ASUBW, asm: x86.ASUBL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -1061,7 +1061,7 @@ var opcodeTable = [...]opInfo{
name: "SUBBconst", name: "SUBBconst",
auxType: auxInt8, auxType: auxInt8,
argLen: 1, argLen: 1,
asm: x86.ASUBB, asm: x86.ASUBL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -1539,7 +1539,7 @@ var opcodeTable = [...]opInfo{
{ {
name: "ANDW", name: "ANDW",
argLen: 2, argLen: 2,
asm: x86.AANDW, asm: x86.AANDL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -1554,7 +1554,7 @@ var opcodeTable = [...]opInfo{
{ {
name: "ANDB", name: "ANDB",
argLen: 2, argLen: 2,
asm: x86.AANDB, asm: x86.AANDL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -1600,7 +1600,7 @@ var opcodeTable = [...]opInfo{
name: "ANDWconst", name: "ANDWconst",
auxType: auxInt16, auxType: auxInt16,
argLen: 1, argLen: 1,
asm: x86.AANDW, asm: x86.AANDL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -1615,7 +1615,7 @@ var opcodeTable = [...]opInfo{
name: "ANDBconst", name: "ANDBconst",
auxType: auxInt8, auxType: auxInt8,
argLen: 1, argLen: 1,
asm: x86.AANDB, asm: x86.AANDL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -1659,7 +1659,7 @@ var opcodeTable = [...]opInfo{
{ {
name: "ORW", name: "ORW",
argLen: 2, argLen: 2,
asm: x86.AORW, asm: x86.AORL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -1674,7 +1674,7 @@ var opcodeTable = [...]opInfo{
{ {
name: "ORB", name: "ORB",
argLen: 2, argLen: 2,
asm: x86.AORB, asm: x86.AORL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -1720,7 +1720,7 @@ var opcodeTable = [...]opInfo{
name: "ORWconst", name: "ORWconst",
auxType: auxInt16, auxType: auxInt16,
argLen: 1, argLen: 1,
asm: x86.AORW, asm: x86.AORL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -1735,7 +1735,7 @@ var opcodeTable = [...]opInfo{
name: "ORBconst", name: "ORBconst",
auxType: auxInt8, auxType: auxInt8,
argLen: 1, argLen: 1,
asm: x86.AORB, asm: x86.AORL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -1779,7 +1779,7 @@ var opcodeTable = [...]opInfo{
{ {
name: "XORW", name: "XORW",
argLen: 2, argLen: 2,
asm: x86.AXORW, asm: x86.AXORL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -1794,7 +1794,7 @@ var opcodeTable = [...]opInfo{
{ {
name: "XORB", name: "XORB",
argLen: 2, argLen: 2,
asm: x86.AXORB, asm: x86.AXORL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -1840,7 +1840,7 @@ var opcodeTable = [...]opInfo{
name: "XORWconst", name: "XORWconst",
auxType: auxInt16, auxType: auxInt16,
argLen: 1, argLen: 1,
asm: x86.AXORW, asm: x86.AXORL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -1855,7 +1855,7 @@ var opcodeTable = [...]opInfo{
name: "XORBconst", name: "XORBconst",
auxType: auxInt8, auxType: auxInt8,
argLen: 1, argLen: 1,
asm: x86.AXORB, asm: x86.AXORL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -2151,7 +2151,7 @@ var opcodeTable = [...]opInfo{
{ {
name: "SHLW", name: "SHLW",
argLen: 2, argLen: 2,
asm: x86.ASHLW, asm: x86.ASHLL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 2}, // .CX {1, 2}, // .CX
@ -2166,7 +2166,7 @@ var opcodeTable = [...]opInfo{
{ {
name: "SHLB", name: "SHLB",
argLen: 2, argLen: 2,
asm: x86.ASHLB, asm: x86.ASHLL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 2}, // .CX {1, 2}, // .CX
@ -2212,7 +2212,7 @@ var opcodeTable = [...]opInfo{
name: "SHLWconst", name: "SHLWconst",
auxType: auxInt16, auxType: auxInt16,
argLen: 1, argLen: 1,
asm: x86.ASHLW, asm: x86.ASHLL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -2227,7 +2227,7 @@ var opcodeTable = [...]opInfo{
name: "SHLBconst", name: "SHLBconst",
auxType: auxInt8, auxType: auxInt8,
argLen: 1, argLen: 1,
asm: x86.ASHLB, asm: x86.ASHLL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -2569,7 +2569,7 @@ var opcodeTable = [...]opInfo{
{ {
name: "NEGW", name: "NEGW",
argLen: 1, argLen: 1,
asm: x86.ANEGW, asm: x86.ANEGL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -2583,7 +2583,7 @@ var opcodeTable = [...]opInfo{
{ {
name: "NEGB", name: "NEGB",
argLen: 1, argLen: 1,
asm: x86.ANEGB, asm: x86.ANEGL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -2625,7 +2625,7 @@ var opcodeTable = [...]opInfo{
{ {
name: "NOTW", name: "NOTW",
argLen: 1, argLen: 1,
asm: x86.ANOTW, asm: x86.ANOTL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -2639,7 +2639,7 @@ var opcodeTable = [...]opInfo{
{ {
name: "NOTB", name: "NOTB",
argLen: 1, argLen: 1,
asm: x86.ANOTB, asm: x86.ANOTL,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {0, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -3243,7 +3243,7 @@ var opcodeTable = [...]opInfo{
name: "MOVBload", name: "MOVBload",
auxType: auxSymOff, auxType: auxSymOff,
argLen: 2, argLen: 2,
asm: x86.AMOVB, asm: x86.AMOVBLZX,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
@ -3285,7 +3285,7 @@ var opcodeTable = [...]opInfo{
name: "MOVWload", name: "MOVWload",
auxType: auxSymOff, auxType: auxSymOff,
argLen: 2, argLen: 2,
asm: x86.AMOVW, asm: x86.AMOVWLZX,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB {0, 4295032831}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .SB
@ -3457,7 +3457,7 @@ var opcodeTable = [...]opInfo{
name: "MOVBloadidx1", name: "MOVBloadidx1",
auxType: auxSymOff, auxType: auxSymOff,
argLen: 3, argLen: 3,
asm: x86.AMOVB, asm: x86.AMOVBLZX,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
@ -3472,7 +3472,7 @@ var opcodeTable = [...]opInfo{
name: "MOVWloadidx2", name: "MOVWloadidx2",
auxType: auxSymOff, auxType: auxSymOff,
argLen: 3, argLen: 3,
asm: x86.AMOVW, asm: x86.AMOVWLZX,
reg: regInfo{ reg: regInfo{
inputs: []inputInfo{ inputs: []inputInfo{
{1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 {1, 65535}, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15