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[dev.cc] 9g: fill progtable for CC, V, and VCC instruction variants
This adds some utilities for converting between the CC, V, and VCC variants of operations and uses these to derive the ProgInfo entries for these variants (which are identical to the ProgInfo for the base operations). The 9g peephole optimizer will also use these conversion utilities. LGTM=minux, rsc R=rsc, dave, minux CC=golang-codereviews https://golang.org/cl/180110044
This commit is contained in:
Austin Clements
parent
6ddc2cb80c
commit
e78777ebfe
@ -225,6 +225,16 @@ enum
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void proginfo(ProgInfo*, Prog*);
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// Many Power ISA arithmetic and logical instructions come in four
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// standard variants. These bits let us map between variants.
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enum {
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V_CC = 1<<0, // xCC (affect CR field 0 flags)
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V_V = 1<<1, // xV (affect SO and OV flags)
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};
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int as2variant(int);
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int variant2as(int, int);
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// To allow use of AJMP, ACALL, ARET in ../gc/popt.c.
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enum
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{
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@ -101,9 +101,36 @@ static ProgInfo progtable[ALAST] = {
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[ADUFFCOPY]= {Call},
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};
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static void
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initproginfo(void)
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{
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static int initialized;
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int addvariant[] = {V_CC, V_V, V_CC|V_V};
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int as, as2, i, variant;
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if(initialized)
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return;
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initialized = 1;
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// Perform one-time expansion of instructions in progtable to
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// their CC, V, and VCC variants
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for(as=0; as<nelem(progtable); as++) {
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if(progtable[as].flags == 0)
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continue;
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variant = as2variant(as);
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for(i=0; i<nelem(addvariant); i++) {
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as2 = variant2as(as, variant | addvariant[i]);
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if(as2 != 0 && progtable[as2].flags == 0)
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progtable[as2] = progtable[as];
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}
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}
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}
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void
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proginfo(ProgInfo *info, Prog *p)
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{
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initproginfo();
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*info = progtable[p->as];
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if(info->flags == 0) {
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*info = progtable[AADD];
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@ -143,3 +170,138 @@ proginfo(ProgInfo *info, Prog *p)
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info->regset |= RtoB(3) | RtoB(4);
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}
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}
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// Instruction variants table. Initially this contains entries only
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// for the "base" form of each instruction. On the first call to
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// as2variant or variant2as, we'll add the variants to the table.
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static int varianttable[ALAST][4] = {
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[AADD]= {AADD, AADDCC, AADDV, AADDVCC},
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[AADDC]= {AADDC, AADDCCC, AADDCV, AADDCVCC},
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[AADDE]= {AADDE, AADDECC, AADDEV, AADDEVCC},
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[AADDME]= {AADDME, AADDMECC, AADDMEV, AADDMEVCC},
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[AADDZE]= {AADDZE, AADDZECC, AADDZEV, AADDZEVCC},
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[AAND]= {AAND, AANDCC, 0, 0},
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[AANDN]= {AANDN, AANDNCC, 0, 0},
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[ACNTLZD]= {ACNTLZD, ACNTLZDCC, 0, 0},
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[ACNTLZW]= {ACNTLZW, ACNTLZWCC, 0, 0},
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[ADIVD]= {ADIVD, ADIVDCC, ADIVDV, ADIVDVCC},
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[ADIVDU]= {ADIVDU, ADIVDUCC, ADIVDUV, ADIVDUVCC},
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[ADIVW]= {ADIVW, ADIVWCC, ADIVWV, ADIVWVCC},
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[ADIVWU]= {ADIVWU, ADIVWUCC, ADIVWUV, ADIVWUVCC},
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[AEQV]= {AEQV, AEQVCC, 0, 0},
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[AEXTSB]= {AEXTSB, AEXTSBCC, 0, 0},
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[AEXTSH]= {AEXTSH, AEXTSHCC, 0, 0},
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[AEXTSW]= {AEXTSW, AEXTSWCC, 0, 0},
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[AFABS]= {AFABS, AFABSCC, 0, 0},
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[AFADD]= {AFADD, AFADDCC, 0, 0},
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[AFADDS]= {AFADDS, AFADDSCC, 0, 0},
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[AFCFID]= {AFCFID, AFCFIDCC, 0, 0},
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[AFCTID]= {AFCTID, AFCTIDCC, 0, 0},
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[AFCTIDZ]= {AFCTIDZ, AFCTIDZCC, 0, 0},
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[AFCTIW]= {AFCTIW, AFCTIWCC, 0, 0},
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[AFCTIWZ]= {AFCTIWZ, AFCTIWZCC, 0, 0},
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[AFDIV]= {AFDIV, AFDIVCC, 0, 0},
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[AFDIVS]= {AFDIVS, AFDIVSCC, 0, 0},
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[AFMADD]= {AFMADD, AFMADDCC, 0, 0},
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[AFMADDS]= {AFMADDS, AFMADDSCC, 0, 0},
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[AFMOVD]= {AFMOVD, AFMOVDCC, 0, 0},
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[AFMSUB]= {AFMSUB, AFMSUBCC, 0, 0},
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[AFMSUBS]= {AFMSUBS, AFMSUBSCC, 0, 0},
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[AFMUL]= {AFMUL, AFMULCC, 0, 0},
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[AFMULS]= {AFMULS, AFMULSCC, 0, 0},
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[AFNABS]= {AFNABS, AFNABSCC, 0, 0},
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[AFNEG]= {AFNEG, AFNEGCC, 0, 0},
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[AFNMADD]= {AFNMADD, AFNMADDCC, 0, 0},
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[AFNMADDS]= {AFNMADDS, AFNMADDSCC, 0, 0},
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[AFNMSUB]= {AFNMSUB, AFNMSUBCC, 0, 0},
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[AFNMSUBS]= {AFNMSUBS, AFNMSUBSCC, 0, 0},
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[AFRES]= {AFRES, AFRESCC, 0, 0},
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[AFRSP]= {AFRSP, AFRSPCC, 0, 0},
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[AFRSQRTE]= {AFRSQRTE, AFRSQRTECC, 0, 0},
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[AFSEL]= {AFSEL, AFSELCC, 0, 0},
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[AFSQRT]= {AFSQRT, AFSQRTCC, 0, 0},
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[AFSQRTS]= {AFSQRTS, AFSQRTSCC, 0, 0},
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[AFSUB]= {AFSUB, AFSUBCC, 0, 0},
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[AFSUBS]= {AFSUBS, AFSUBSCC, 0, 0},
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[AMTFSB0]= {AMTFSB0, AMTFSB0CC, 0, 0},
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[AMTFSB1]= {AMTFSB1, AMTFSB1CC, 0, 0},
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[AMULHD]= {AMULHD, AMULHDCC, 0, 0},
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[AMULHDU]= {AMULHDU, AMULHDUCC, 0, 0},
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[AMULHW]= {AMULHW, AMULHWCC, 0, 0},
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[AMULHWU]= {AMULHWU, AMULHWUCC, 0, 0},
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[AMULLD]= {AMULLD, AMULLDCC, AMULLDV, AMULLDVCC},
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[AMULLW]= {AMULLW, AMULLWCC, AMULLWV, AMULLWVCC},
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[ANAND]= {ANAND, ANANDCC, 0, 0},
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[ANEG]= {ANEG, ANEGCC, ANEGV, ANEGVCC},
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[ANOR]= {ANOR, ANORCC, 0, 0},
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[AOR]= {AOR, AORCC, 0, 0},
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[AORN]= {AORN, AORNCC, 0, 0},
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[AREM]= {AREM, AREMCC, AREMV, AREMVCC},
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[AREMD]= {AREMD, AREMDCC, AREMDV, AREMDVCC},
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[AREMDU]= {AREMDU, AREMDUCC, AREMDUV, AREMDUVCC},
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[AREMU]= {AREMU, AREMUCC, AREMUV, AREMUVCC},
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[ARLDC]= {ARLDC, ARLDCCC, 0, 0},
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[ARLDCL]= {ARLDCL, ARLDCLCC, 0, 0},
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[ARLDCR]= {ARLDCR, ARLDCRCC, 0, 0},
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[ARLDMI]= {ARLDMI, ARLDMICC, 0, 0},
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[ARLWMI]= {ARLWMI, ARLWMICC, 0, 0},
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[ARLWNM]= {ARLWNM, ARLWNMCC, 0, 0},
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[ASLD]= {ASLD, ASLDCC, 0, 0},
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[ASLW]= {ASLW, ASLWCC, 0, 0},
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[ASRAD]= {ASRAD, ASRADCC, 0, 0},
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[ASRAW]= {ASRAW, ASRAWCC, 0, 0},
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[ASRD]= {ASRD, ASRDCC, 0, 0},
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[ASRW]= {ASRW, ASRWCC, 0, 0},
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[ASUB]= {ASUB, ASUBCC, ASUBV, ASUBVCC},
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[ASUBC]= {ASUBC, ASUBCCC, ASUBCV, ASUBCVCC},
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[ASUBE]= {ASUBE, ASUBECC, ASUBEV, ASUBEVCC},
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[ASUBME]= {ASUBME, ASUBMECC, ASUBMEV, ASUBMEVCC},
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[ASUBZE]= {ASUBZE, ASUBZECC, ASUBZEV, ASUBZEVCC},
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[AXOR]= {AXOR, AXORCC, 0, 0},
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};
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static void
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initvariants(void)
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{
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static int initialized;
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int i, j;
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if(initialized)
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return;
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initialized = 1;
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for(i=0; i<nelem(varianttable); i++) {
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if(varianttable[i][0] == 0) {
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// Instruction has no variants
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varianttable[i][0] = i;
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continue;
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}
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// Copy base form to other variants
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if(varianttable[i][0] == i) {
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for(j=0; j<nelem(varianttable[i]); j++)
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memmove(&varianttable[varianttable[i][j]], &varianttable[i], sizeof(varianttable[i]));
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}
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}
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}
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// as2variant returns the variant (V_*) flags of instruction as.
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int
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as2variant(int as)
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{
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int i;
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initvariants();
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for(i=0; i<nelem(varianttable[as]); i++)
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if(varianttable[as][i] == as)
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return i;
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fatal("as2variant: instruction %A is not a variant of itself", as);
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return 0;
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}
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// variant2as returns the instruction as with the given variant (V_*) flags.
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// If no such variant exists, this returns 0.
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int
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variant2as(int as, int flags)
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{
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initvariants();
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return varianttable[as][flags];
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}
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