mirror of
https://github.com/golang/go
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cmd/internal/obj/riscv: update references to RISC-V specification
Update references to version 20240411 of the RISC-V specifications. Reorder and regroup instructions to maintain ordering. Change-Id: Iea2a5d22ad677e04948e9a9325986ad301c03f35 Reviewed-on: https://go-review.googlesource.com/c/go/+/616115 Reviewed-by: Cherry Mui <cherryyz@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com> Reviewed-by: Mark Ryan <markdryan@rivosinc.com> Reviewed-by: Meng Zhuo <mengzhuo1203@gmail.com> Reviewed-by: David Chase <drchase@google.com>
This commit is contained in:
Joel Sing
parent
2ef8e41f95
commit
e5e552b816
55
src/cmd/asm/internal/asm/testdata/riscv64.s
vendored
55
src/cmd/asm/internal/asm/testdata/riscv64.s
vendored
@ -6,7 +6,9 @@
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TEXT asmtest(SB),DUPOK|NOSPLIT,$0
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start:
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//
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// Unprivileged ISA
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//
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// 2.4: Integer Computational Instructions
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@ -139,7 +141,7 @@ start:
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// 2.7: Memory Ordering Instructions
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FENCE // 0f00f00f
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// 5.2: Integer Computational Instructions (RV64I)
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// 4.2: Integer Computational Instructions (RV64I)
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ADDIW $1, X5, X6 // 1b831200
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SLLIW $1, X5, X6 // 1b931200
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SRLIW $1, X5, X6 // 1bd31200
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@ -164,18 +166,25 @@ start:
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SUBW $1, X6 // 1b03f3ff
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SRAW $1, X6 // 1b531340
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// 5.3: Load and Store Instructions (RV64I)
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// 4.3: Load and Store Instructions (RV64I)
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LD (X5), X6 // 03b30200
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LD 4(X5), X6 // 03b34200
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SD X5, (X6) // 23305300
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SD X5, 4(X6) // 23325300
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// 7.1: Multiplication Operations
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// 8.1: Base Counters and Timers (Zicntr)
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RDCYCLE X5 // f32200c0
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RDTIME X5 // f32210c0
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RDINSTRET X5 // f32220c0
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// 13.1: Multiplication Operations
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MUL X5, X6, X7 // b3035302
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MULH X5, X6, X7 // b3135302
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MULHU X5, X6, X7 // b3335302
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MULHSU X5, X6, X7 // b3235302
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MULW X5, X6, X7 // bb035302
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// 13.2: Division Operations
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DIV X5, X6, X7 // b3435302
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DIVU X5, X6, X7 // b3535302
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REM X5, X6, X7 // b3635302
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@ -185,13 +194,13 @@ start:
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REMW X5, X6, X7 // bb635302
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REMUW X5, X6, X7 // bb735302
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// 8.2: Load-Reserved/Store-Conditional
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// 14.2: Load-Reserved/Store-Conditional (Zalrsc)
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LRW (X5), X6 // 2fa30214
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LRD (X5), X6 // 2fb30214
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SCW X5, (X6), X7 // af23531a
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SCD X5, (X6), X7 // af33531a
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// 8.3: Atomic Memory Operations
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// 14.4: Atomic Memory Operations (Zaamo)
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AMOSWAPW X5, (X6), X7 // af23530e
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AMOSWAPD X5, (X6), X7 // af33530e
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AMOADDW X5, (X6), X7 // af235306
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@ -211,18 +220,13 @@ start:
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AMOMINUW X5, (X6), X7 // af2353c6
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AMOMINUD X5, (X6), X7 // af3353c6
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// 10.1: Base Counters and Timers
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RDCYCLE X5 // f32200c0
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RDTIME X5 // f32210c0
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RDINSTRET X5 // f32220c0
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// 11.5: Single-Precision Load and Store Instructions
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// 20.5: Single-Precision Load and Store Instructions
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FLW (X5), F0 // 07a00200
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FLW 4(X5), F0 // 07a04200
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FSW F0, (X5) // 27a00200
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FSW F0, 4(X5) // 27a20200
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// 11.6: Single-Precision Floating-Point Computational Instructions
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// 20.6: Single-Precision Floating-Point Computational Instructions
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FADDS F1, F0, F2 // 53011000
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FSUBS F1, F0, F2 // 53011008
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FMULS F1, F0, F2 // 53011010
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@ -231,7 +235,7 @@ start:
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FMAXS F1, F0, F2 // 53111028
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FSQRTS F0, F1 // d3000058
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// 11.7: Single-Precision Floating-Point Conversion and Move Instructions
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// 20.7: Single-Precision Floating-Point Conversion and Move Instructions
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FCVTWS F0, X5 // d31200c0
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FCVTWS.RNE F0, X5 // d30200c0
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FCVTWS.RTZ F0, X5 // d31200c0
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@ -272,21 +276,21 @@ start:
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FNMSUBS F1, F2, F3, F4 // 4b822018
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FNMADDS F1, F2, F3, F4 // 4f822018
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// 11.8: Single-Precision Floating-Point Compare Instructions
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// 20.8: Single-Precision Floating-Point Compare Instructions
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FEQS F0, F1, X7 // d3a300a0
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FLTS F0, F1, X7 // d39300a0
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FLES F0, F1, X7 // d38300a0
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// 11.9: Single-Precision Floating-Point Classify Instruction
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// 20.9: Single-Precision Floating-Point Classify Instruction
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FCLASSS F0, X5 // d31200e0
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// 12.3: Double-Precision Load and Store Instructions
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// 21.3: Double-Precision Load and Store Instructions
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FLD (X5), F0 // 07b00200
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FLD 4(X5), F0 // 07b04200
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FSD F0, (X5) // 27b00200
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FSD F0, 4(X5) // 27b20200
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// 12.4: Double-Precision Floating-Point Computational Instructions
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// 21.4: Double-Precision Floating-Point Computational Instructions
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FADDD F1, F0, F2 // 53011002
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FSUBD F1, F0, F2 // 5301100a
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FMULD F1, F0, F2 // 53011012
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@ -295,7 +299,7 @@ start:
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FMAXD F1, F0, F2 // 5311102a
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FSQRTD F0, F1 // d300005a
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// 12.5: Double-Precision Floating-Point Conversion and Move Instructions
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// 21.5: Double-Precision Floating-Point Conversion and Move Instructions
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FCVTWD F0, X5 // d31200c2
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FCVTWD.RNE F0, X5 // d30200c2
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FCVTWD.RTZ F0, X5 // d31200c2
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@ -336,11 +340,10 @@ start:
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FNMSUBD F1, F2, F3, F4 // 4b82201a
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FNMADDD F1, F2, F3, F4 // 4f82201a
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// 12.6: Double-Precision Floating-Point Classify Instruction
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// 21.7: Double-Precision Floating-Point Classify Instruction
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FCLASSD F0, X5 // d31200e2
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// RISC-V Bit-Manipulation ISA-extensions (1.0)
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// 1.1: Address Generation Instructions (Zba)
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// 28.4.1: Address Generation Instructions (Zba)
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ADDUW X10, X11, X12 // 3b86a508
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ADDUW X10, X11 // bb85a508
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SH1ADD X11, X12, X13 // b326b620
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@ -360,7 +363,7 @@ start:
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SLLIUW $63, X17, X18 // 1b99f80b
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SLLIUW $1, X18, X19 // 9b191908
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// 1.2: Basic Bit Manipulation (Zbb)
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// 28.4.2: Basic Bit Manipulation (Zbb)
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ANDN X19, X20, X21 // b37a3a41 or 93caf9ffb37a5a01
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ANDN X19, X20 // 337a3a41 or 93cff9ff337afa01
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CLZ X20, X21 // 931a0a60
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@ -385,7 +388,7 @@ start:
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XNOR X18, X19 // b3c92941 or b3c9290193c9f9ff
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ZEXTH X19, X20 // 3bca0908
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// 1.3: Bitwise Rotation (Zbb)
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// 28.4.2: Bitwise Rotation (Zbb)
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ROL X8, X9, X10 // 33958460 or b30f8040b3dff4013395840033e5af00
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ROL X8, X9 // b3948460 or b30f8040b3dff401b3948400b3e49f00
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ROLW X9, X10, X11 // bb159560 or b30f9040bb5ff501bb159500b3e5bf00
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@ -403,7 +406,7 @@ start:
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ORCB X5, X6 // 13d37228
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REV8 X7, X8 // 13d4836b
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// 1.5: Single-bit Instructions (Zbs)
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// 28.4.4: Single-bit Instructions (Zbs)
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BCLR X23, X24, X25 // b31c7c49
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BCLR $63, X24 // 131cfc4b
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BCLRI $1, X25, X26 // 139d1c48
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@ -417,9 +420,11 @@ start:
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BSET $63, X9 // 9394f42b
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BSETI $1, X10, X11 // 93151528
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//
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// Privileged ISA
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//
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// 3.2.1: Environment Call and Breakpoint
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// 3.3.1: Environment Call and Breakpoint
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ECALL // 73000000
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SCALL // 73000000
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EBREAK // 73001000
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@ -57,6 +57,18 @@ var Anames = []string{
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"SRAW",
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"LD",
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"SD",
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"CSRRW",
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"CSRRS",
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"CSRRC",
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"CSRRWI",
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"CSRRSI",
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"CSRRCI",
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"RDCYCLE",
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"RDCYCLEH",
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"RDTIME",
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"RDTIMEH",
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"RDINSTRET",
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"RDINSTRETH",
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"MUL",
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"MULH",
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"MULHU",
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@ -92,12 +104,6 @@ var Anames = []string{
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"AMOMAXUW",
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"AMOMINW",
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"AMOMINUW",
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"RDCYCLE",
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"RDCYCLEH",
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"RDTIME",
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"RDTIMEH",
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"RDINSTRET",
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"RDINSTRETH",
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"FRCSR",
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"FSCSR",
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"FRRM",
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@ -202,21 +208,6 @@ var Anames = []string{
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"FLEQ",
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"FLTQ",
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"FCLASSQ",
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"CSRRW",
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"CSRRS",
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"CSRRC",
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"CSRRWI",
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"CSRRSI",
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"CSRRCI",
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"ECALL",
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"SCALL",
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"EBREAK",
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"SBREAK",
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"MRET",
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"SRET",
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"DRET",
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"WFI",
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"SFENCEVMA",
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"ADDUW",
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"SH1ADD",
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"SH1ADDUW",
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@ -632,6 +623,15 @@ var Anames = []string{
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"VMV2RV",
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"VMV4RV",
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"VMV8RV",
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"ECALL",
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"SCALL",
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"EBREAK",
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"SBREAK",
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"MRET",
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"SRET",
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"DRET",
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"WFI",
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"SFENCEVMA",
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"WORD",
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"BEQZ",
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"BGEZ",
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@ -324,11 +324,13 @@ const (
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//
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// As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler.
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//
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// See also "The RISC-V Instruction Set Manual" at https://riscv.org/specifications/.
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// See also "The RISC-V Instruction Set Manual" at https://riscv.org/technical/specifications/.
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//
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// If you modify this table, you MUST run 'go generate' to regenerate anames.go!
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const (
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// Unprivileged ISA (Document Version 20190608-Base-Ratified)
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//
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// Unprivileged ISA (version 20240411)
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//
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// 2.4: Integer Computational Instructions
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AADDI = obj.ABaseRISCV + obj.A_ARCHSPECIFIC + iota
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@ -379,7 +381,7 @@ const (
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AFENCETSO
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APAUSE
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// 5.2: Integer Computational Instructions (RV64I)
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// 4.2: Integer Computational Instructions (RV64I)
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AADDIW
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ASLLIW
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ASRLIW
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@ -390,16 +392,34 @@ const (
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ASUBW
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ASRAW
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// 5.3: Load and Store Instructions (RV64I)
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// 4.3: Load and Store Instructions (RV64I)
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ALD
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ASD
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// 7.1: Multiplication Operations
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// 7.1: CSR Instructions (Zicsr)
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ACSRRW
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ACSRRS
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ACSRRC
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ACSRRWI
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ACSRRSI
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ACSRRCI
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// 8.1: Base Counters and Timers (Zicntr)
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ARDCYCLE
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ARDCYCLEH
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ARDTIME
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ARDTIMEH
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ARDINSTRET
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ARDINSTRETH
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// 13.1: Multiplication Operations
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AMUL
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AMULH
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AMULHU
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AMULHSU
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AMULW
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// 13.2: Division Operations
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ADIV
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ADIVU
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AREM
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@ -409,13 +429,13 @@ const (
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AREMW
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AREMUW
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// 8.2: Load-Reserved/Store-Conditional Instructions
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// 14.2: Load-Reserved/Store-Conditional Instructions (Zalrsc)
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ALRD
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ASCD
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ALRW
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ASCW
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// 8.3: Atomic Memory Operations
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// 14.4: Atomic Memory Operations (Zaamo)
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AAMOSWAPD
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AAMOADDD
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AAMOANDD
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@ -435,15 +455,7 @@ const (
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AAMOMINW
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AAMOMINUW
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// 10.1: Base Counters and Timers
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ARDCYCLE
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ARDCYCLEH
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ARDTIME
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ARDTIMEH
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ARDINSTRET
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ARDINSTRETH
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// 11.2: Floating-Point Control and Status Register
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// 20.2: Floating-Point Control and Status Register
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AFRCSR
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AFSCSR
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AFRRM
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@ -453,11 +465,11 @@ const (
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AFSRMI
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AFSFLAGSI
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// 11.5: Single-Precision Load and Store Instructions
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// 20.5: Single-Precision Load and Store Instructions
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AFLW
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AFSW
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// 11.6: Single-Precision Floating-Point Computational Instructions
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// 20.6: Single-Precision Floating-Point Computational Instructions
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AFADDS
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AFSUBS
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AFMULS
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@ -470,7 +482,7 @@ const (
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AFNMADDS
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AFNMSUBS
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// 11.7: Single-Precision Floating-Point Conversion and Move Instructions
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// 20.7: Single-Precision Floating-Point Conversion and Move Instructions
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AFCVTWS
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AFCVTLS
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AFCVTSW
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@ -487,19 +499,19 @@ const (
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AFMVXW
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AFMVWX
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// 11.8: Single-Precision Floating-Point Compare Instructions
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// 20.8: Single-Precision Floating-Point Compare Instructions
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AFEQS
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AFLTS
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AFLES
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// 11.9: Single-Precision Floating-Point Classify Instruction
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// 20.9: Single-Precision Floating-Point Classify Instruction
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AFCLASSS
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// 12.3: Double-Precision Load and Store Instructions
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// 21.3: Double-Precision Load and Store Instructions
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AFLD
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AFSD
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// 12.4: Double-Precision Floating-Point Computational Instructions
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// 21.4: Double-Precision Floating-Point Computational Instructions
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AFADDD
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AFSUBD
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AFMULD
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@ -512,7 +524,7 @@ const (
|
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AFNMADDD
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AFNMSUBD
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// 12.5: Double-Precision Floating-Point Conversion and Move Instructions
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// 21.5: Double-Precision Floating-Point Conversion and Move Instructions
|
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AFCVTWD
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AFCVTLD
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AFCVTDW
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@ -529,19 +541,19 @@ const (
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AFMVXD
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AFMVDX
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// 12.6: Double-Precision Floating-Point Compare Instructions
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// 21.6: Double-Precision Floating-Point Compare Instructions
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AFEQD
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AFLTD
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AFLED
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// 12.7: Double-Precision Floating-Point Classify Instruction
|
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// 21.7: Double-Precision Floating-Point Classify Instruction
|
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AFCLASSD
|
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// 13.1 Quad-Precision Load and Store Instructions
|
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// 22.1 Quad-Precision Load and Store Instructions
|
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AFLQ
|
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AFSQ
|
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|
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// 13.2: Quad-Precision Computational Instructions
|
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// 22.2: Quad-Precision Computational Instructions
|
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AFADDQ
|
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AFSUBQ
|
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AFMULQ
|
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@ -554,7 +566,7 @@ const (
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AFNMADDQ
|
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AFNMSUBQ
|
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// 13.3 Quad-Precision Convert and Move Instructions
|
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// 22.3 Quad-Precision Convert and Move Instructions
|
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AFCVTWQ
|
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AFCVTLQ
|
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AFCVTSQ
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@ -571,46 +583,15 @@ const (
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AFSGNJNQ
|
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AFSGNJXQ
|
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|
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// 13.4 Quad-Precision Floating-Point Compare Instructions
|
||||
// 22.4 Quad-Precision Floating-Point Compare Instructions
|
||||
AFEQQ
|
||||
AFLEQ
|
||||
AFLTQ
|
||||
|
||||
// 13.5 Quad-Precision Floating-Point Classify Instruction
|
||||
// 22.5 Quad-Precision Floating-Point Classify Instruction
|
||||
AFCLASSQ
|
||||
|
||||
// Privileged ISA (Version 20190608-Priv-MSU-Ratified)
|
||||
|
||||
// 3.1.9: Instructions to Access CSRs
|
||||
ACSRRW
|
||||
ACSRRS
|
||||
ACSRRC
|
||||
ACSRRWI
|
||||
ACSRRSI
|
||||
ACSRRCI
|
||||
|
||||
// 3.2.1: Environment Call and Breakpoint
|
||||
AECALL
|
||||
ASCALL
|
||||
AEBREAK
|
||||
ASBREAK
|
||||
|
||||
// 3.2.2: Trap-Return Instructions
|
||||
AMRET
|
||||
ASRET
|
||||
ADRET
|
||||
|
||||
// 3.2.3: Wait for Interrupt
|
||||
AWFI
|
||||
|
||||
// 4.2.1: Supervisor Memory-Management Fence Instruction
|
||||
ASFENCEVMA
|
||||
|
||||
//
|
||||
// RISC-V Bit-Manipulation ISA-extensions (1.0)
|
||||
//
|
||||
|
||||
// 1.1: Address Generation Instructions (Zba)
|
||||
// 28.4.1: Address Generation Instructions (Zba)
|
||||
AADDUW
|
||||
ASH1ADD
|
||||
ASH1ADDUW
|
||||
@ -620,7 +601,7 @@ const (
|
||||
ASH3ADDUW
|
||||
ASLLIUW
|
||||
|
||||
// 1.2: Basic Bit Manipulation (Zbb)
|
||||
// 28.4.2: Basic Bit Manipulation (Zbb)
|
||||
AANDN
|
||||
AORN
|
||||
AXNOR
|
||||
@ -638,7 +619,7 @@ const (
|
||||
ASEXTH
|
||||
AZEXTH
|
||||
|
||||
// 1.3: Bitwise Rotation (Zbb)
|
||||
// 28.4.3: Bitwise Rotation (Zbb)
|
||||
AROL
|
||||
AROLW
|
||||
AROR
|
||||
@ -648,7 +629,7 @@ const (
|
||||
AORCB
|
||||
AREV8
|
||||
|
||||
// 1.5: Single-bit Instructions (Zbs)
|
||||
// 28.4.4: Single-bit Instructions (Zbs)
|
||||
ABCLR
|
||||
ABCLRI
|
||||
ABEXT
|
||||
@ -1149,6 +1130,27 @@ const (
|
||||
AVMV4RV
|
||||
AVMV8RV
|
||||
|
||||
//
|
||||
// Privileged ISA (version 20240411)
|
||||
//
|
||||
|
||||
// 3.3.1: Environment Call and Breakpoint
|
||||
AECALL
|
||||
ASCALL
|
||||
AEBREAK
|
||||
ASBREAK
|
||||
|
||||
// 3.3.2: Trap-Return Instructions
|
||||
AMRET
|
||||
ASRET
|
||||
ADRET
|
||||
|
||||
// 3.3.3: Wait for Interrupt
|
||||
AWFI
|
||||
|
||||
// 10.2: Supervisor Memory-Management Fence Instruction
|
||||
ASFENCEVMA
|
||||
|
||||
// The escape hatch. Inserts a single 32-bit word.
|
||||
AWORD
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user