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cmd/internal/obj: support Zba, Zbb, Zbs extensions in riscv64 assembler
Add assembler support for Zba, Zbb, Zbs extensions, which are mandatory in the rva22u64 profile. These can be used to accelerate address computation and bit manipulation. Change-Id: Ie90fe6b76b1382cf69984a0e71a72d3cba0e750a Reviewed-on: https://go-review.googlesource.com/c/go/+/559655 Reviewed-by: M Zhuo <mengzhuo1203@gmail.com> Run-TryBot: Joel Sing <joel@sing.id.au> Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Joel Sing <joel@sing.id.au> Reviewed-by: Keith Randall <khr@google.com> TryBot-Result: Gopher Robot <gobot@golang.org> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
This commit is contained in:
Wang Yaduo
M Zhuo
parent
e39af550f8
commit
db423dde85
96
src/cmd/asm/internal/asm/testdata/riscv64.s
vendored
96
src/cmd/asm/internal/asm/testdata/riscv64.s
vendored
@ -339,6 +339,84 @@ start:
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// 12.6: Double-Precision Floating-Point Classify Instruction
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FCLASSD F0, X5 // d31200e2
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// RISC-V Bit-Manipulation ISA-extensions (1.0)
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// 1.1: Address Generation Instructions (Zba)
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ADDUW X10, X11, X12 // 3b86a508
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ADDUW X10, X11 // bb85a508
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SH1ADD X11, X12, X13 // b326b620
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SH1ADD X11, X12 // 3326b620
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SH1ADDUW X12, X13, X14 // 3ba7c620
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SH1ADDUW X12, X13 // bba6c620
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SH2ADD X13, X14, X15 // b347d720
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SH2ADD X13, X14 // 3347d720
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SH2ADDUW X14, X15, X16 // 3bc8e720
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SH2ADDUW X14, X15 // bbc7e720
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SH3ADD X15, X16, X17 // b368f820
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SH3ADD X15, X16 // 3368f820
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SH3ADDUW X16, X17, X18 // 3be90821
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SH3ADDUW X16, X17 // bbe80821
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SLLIUW $31, X17, X18 // 1b99f809
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SLLIUW $63, X17 // 9b98f80b
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SLLIUW $63, X17, X18 // 1b99f80b
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SLLIUW $1, X18, X19 // 9b191908
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// 1.2: Basic Bit Manipulation (Zbb)
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ANDN X19, X20, X21 // b37a3a41
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ANDN X19, X20 // 337a3a41
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CLZ X20, X21 // 931a0a60
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CLZW X21, X22 // 1b9b0a60
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CPOP X22, X23 // 931b2b60
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CPOPW X23, X24 // 1b9c2b60
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CTZ X24, X25 // 931c1c60
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CTZW X25, X26 // 1b9d1c60
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MAX X26, X28, X29 // b36eae0b
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MAX X26, X28 // 336eae0b
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MAXU X28, X29, X30 // 33ffce0b
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MAXU X28, X29 // b3fece0b
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MIN X29, X30, X5 // b342df0b
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MIN X29, X30 // 334fdf0b
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MINU X30, X5, X6 // 33d3e20b
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MINU X30, X5 // b3d2e20b
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ORN X6, X7, X8 // 33e46340
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ORN X6, X7 // b3e36340
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SEXTB X16, X17 // 93184860
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SEXTH X17, X18 // 13995860
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XNOR X18, X19, X20 // 33ca2941
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XNOR X18, X19 // b3c92941
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ZEXTH X19, X20 // 3bca0908
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// 1.3: Bitwise Rotation (Zbb)
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ROL X8, X9, X10 // 33958460 or b30f8040b3dff4013395840033e5af00
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ROL X8, X9 // b3948460 or b30f8040b3dff401b3948400b3e49f00
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ROLW X9, X10, X11 // bb159560 or b30f9040bb5ff501bb159500b3e5bf00
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ROLW X9, X10 // 3b159560 or b30f9040bb5ff5013b15950033e5af00
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ROR X10, X11, X12 // 33d6a560 or b30fa040b39ff50133d6a50033e6cf00
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ROR X10, X11 // b3d5a560 or b30fa040b39ff501b3d5a500b3e5bf00
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ROR $63, X11 // 93d5f563 or 93dff50393951500b3e5bf00
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RORI $63, X11, X12 // 13d6f563 or 93dff5031396150033e6cf00
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RORI $1, X12, X13 // 93561660 or 935f16009316f603b3e6df00
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RORIW $31, X13, X14 // 1bd7f661 or 9bdff6011b97160033e7ef00
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RORIW $1, X14, X15 // 9b571760 or 9b5f17009b17f701b3e7ff00
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RORW X15, X16, X17 // bb58f860 or b30ff040bb1ff801bb58f800b3e81f01
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RORW X15, X16 // 3b58f860 or b30ff040bb1ff8013b58f80033e80f01
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RORW $31, X13 // 9bd6f661 or 9bdff6019b961600b3e6df00
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ORCB X5, X6 // 13d37228
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REV8 X7, X8 // 13d4836b
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// 1.5: Single-bit Instructions (Zbs)
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BCLR X23, X24, X25 // b31c7c49
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BCLR $63, X24 // 131cfc4b
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BCLRI $1, X25, X26 // 139d1c48
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BEXT X26, X28, X29 // b35eae49
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BEXT $63, X28 // 135efe4b
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BEXTI $1, X29, X30 // 13df1e48
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BINV X30, X5, X6 // 3393e269
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BINV $63, X6 // 1313f36b
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BINVI $1, X7, X8 // 13941368
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BSET X8, X9, X10 // 33958428
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BSET $63, X9 // 9394f42b
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BSETI $1, X10, X11 // 93151528
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// Privileged ISA
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// 3.2.1: Environment Call and Breakpoint
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@ -417,24 +495,6 @@ start:
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NEGW X5 // bb025040
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NEGW X5, X6 // 3b035040
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// Bitwise rotation pseudo-instructions
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ROL X5, X6, X7 // b30f5040b35ff301b3135300b3e37f00
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ROL X5, X6 // b30f5040b35ff3013313530033e36f00
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ROLW X5, X6, X7 // b30f5040bb5ff301bb135300b3e37f00
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ROLW X5, X6 // b30f5040bb5ff3013b13530033e36f00
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ROR X5, X6, X7 // b30f5040b31ff301b3535300b3e37f00
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ROR X5, X6 // b30f5040b31ff3013353530033e36f00
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RORW X5, X6, X7 // b30f5040bb1ff301bb535300b3e37f00
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RORW X5, X6 // b30f5040bb1ff3013b53530033e36f00
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RORI $5, X6, X7 // 935f53009313b303b3e37f00
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RORI $5, X6 // 935f53001313b30333e36f00
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RORIW $5, X6, X7 // 9b5f53009b13b301b3e37f00
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RORIW $5, X6 // 9b5f53001b13b30133e36f00
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ROR $5, X6, X7 // 935f53009313b303b3e37f00
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ROR $5, X6 // 935f53001313b30333e36f00
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RORW $5, X6, X7 // 9b5f53009b13b301b3e37f00
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RORW $5, X6 // 9b5f53001b13b30133e36f00
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// This jumps to the second instruction in the function (the
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// first instruction is an invisible stack pointer adjustment).
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JMP start // JMP 2
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@ -217,6 +217,46 @@ var Anames = []string{
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"DRET",
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"WFI",
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"SFENCEVMA",
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"ADDUW",
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"SH1ADD",
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"SH1ADDUW",
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"SH2ADD",
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"SH2ADDUW",
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"SH3ADD",
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"SH3ADDUW",
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"SLLIUW",
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"ANDN",
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"ORN",
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"XNOR",
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"CLZ",
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"CLZW",
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"CTZ",
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"CTZW",
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"CPOP",
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"CPOPW",
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"MAX",
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"MAXU",
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"MIN",
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"MINU",
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"SEXTB",
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"SEXTH",
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"ZEXTH",
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"ROL",
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"ROLW",
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"ROR",
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"RORI",
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"RORIW",
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"RORW",
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"ORCB",
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"REV8",
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"BCLR",
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"BCLRI",
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"BEXT",
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"BEXTI",
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"BINV",
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"BINVI",
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"BSET",
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"BSETI",
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"WORD",
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"BEQZ",
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"BGEZ",
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@ -246,12 +286,6 @@ var Anames = []string{
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"NEG",
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"NEGW",
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"NOT",
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"ROL",
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"ROLW",
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"ROR",
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"RORI",
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"RORIW",
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"RORW",
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"SEQZ",
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"SNEZ",
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"LAST",
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@ -572,6 +572,58 @@ const (
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// 4.2.1: Supervisor Memory-Management Fence Instruction
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ASFENCEVMA
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//
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// RISC-V Bit-Manipulation ISA-extensions (1.0)
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//
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// 1.1: Address Generation Instructions (Zba)
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AADDUW
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ASH1ADD
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ASH1ADDUW
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ASH2ADD
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ASH2ADDUW
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ASH3ADD
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ASH3ADDUW
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ASLLIUW
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// 1.2: Basic Bit Manipulation (Zbb)
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AANDN
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AORN
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AXNOR
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ACLZ
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ACLZW
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ACTZ
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ACTZW
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ACPOP
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ACPOPW
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AMAX
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AMAXU
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AMIN
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AMINU
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ASEXTB
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ASEXTH
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AZEXTH
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// 1.3: Bitwise Rotation (Zbb)
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AROL
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AROLW
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AROR
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ARORI
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ARORIW
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ARORW
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AORCB
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AREV8
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// 1.5: Single-bit Instructions (Zbs)
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ABCLR
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ABCLRI
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ABEXT
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ABEXTI
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ABINV
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ABINVI
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ABSET
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ABSETI
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// The escape hatch. Inserts a single 32-bit word.
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AWORD
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@ -605,12 +657,6 @@ const (
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ANEG
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ANEGW
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ANOT
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AROL
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AROLW
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AROR
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ARORI
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ARORIW
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ARORW
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ASEQZ
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ASNEZ
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@ -1,4 +1,4 @@
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// Code generated by parse.py -go rv64_a rv64_d rv64_f rv64_i rv64_m rv64_q rv_a rv_d rv_f rv_i rv_m rv_q rv_s rv_system rv_zicsr; DO NOT EDIT.
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// Code generated by ./parse.py -go rv64_a rv64_d rv64_f rv64_i rv64_m rv64_q rv64_zba rv64_zbb rv64_zbs rv_a rv_d rv_f rv_i rv_m rv_q rv_zba rv_zbb rv_zbs rv_s rv_system rv_zicsr; DO NOT EDIT.
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package riscv
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import "cmd/internal/obj"
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@ -15,6 +15,8 @@ func encode(a obj.As) *inst {
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switch a {
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case AADD:
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return &inst{0x33, 0x0, 0x0, 0, 0x0}
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case AADDUW:
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return &inst{0x3b, 0x0, 0x0, 128, 0x4}
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case AADDI:
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return &inst{0x13, 0x0, 0x0, 0, 0x0}
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case AADDIW:
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@ -61,20 +63,46 @@ func encode(a obj.As) *inst {
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return &inst{0x33, 0x7, 0x0, 0, 0x0}
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case AANDI:
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return &inst{0x13, 0x7, 0x0, 0, 0x0}
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case AANDN:
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return &inst{0x33, 0x7, 0x0, 1024, 0x20}
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case AAUIPC:
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return &inst{0x17, 0x0, 0x0, 0, 0x0}
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case ABCLR:
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return &inst{0x33, 0x1, 0x0, 1152, 0x24}
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case ABCLRI:
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return &inst{0x13, 0x1, 0x0, 1152, 0x24}
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case ABEQ:
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return &inst{0x63, 0x0, 0x0, 0, 0x0}
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case ABEXT:
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return &inst{0x33, 0x5, 0x0, 1152, 0x24}
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case ABEXTI:
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return &inst{0x13, 0x5, 0x0, 1152, 0x24}
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case ABGE:
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return &inst{0x63, 0x5, 0x0, 0, 0x0}
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case ABGEU:
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return &inst{0x63, 0x7, 0x0, 0, 0x0}
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case ABINV:
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return &inst{0x33, 0x1, 0x0, 1664, 0x34}
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case ABINVI:
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return &inst{0x13, 0x1, 0x0, 1664, 0x34}
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case ABLT:
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return &inst{0x63, 0x4, 0x0, 0, 0x0}
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case ABLTU:
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return &inst{0x63, 0x6, 0x0, 0, 0x0}
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case ABNE:
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return &inst{0x63, 0x1, 0x0, 0, 0x0}
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case ABSET:
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return &inst{0x33, 0x1, 0x0, 640, 0x14}
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case ABSETI:
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return &inst{0x13, 0x1, 0x0, 640, 0x14}
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case ACLZ:
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return &inst{0x13, 0x1, 0x0, 1536, 0x30}
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case ACLZW:
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return &inst{0x1b, 0x1, 0x0, 1536, 0x30}
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case ACPOP:
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return &inst{0x13, 0x1, 0x2, 1538, 0x30}
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case ACPOPW:
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return &inst{0x1b, 0x1, 0x2, 1538, 0x30}
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case ACSRRC:
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return &inst{0x73, 0x3, 0x0, 0, 0x0}
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case ACSRRCI:
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@ -87,6 +115,10 @@ func encode(a obj.As) *inst {
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return &inst{0x73, 0x1, 0x0, 0, 0x0}
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case ACSRRWI:
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return &inst{0x73, 0x5, 0x0, 0, 0x0}
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case ACTZ:
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return &inst{0x13, 0x1, 0x1, 1537, 0x30}
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case ACTZW:
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return &inst{0x1b, 0x1, 0x1, 1537, 0x30}
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case ADIV:
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return &inst{0x33, 0x4, 0x0, 32, 0x1}
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case ADIVU:
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@ -95,8 +127,6 @@ func encode(a obj.As) *inst {
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return &inst{0x3b, 0x5, 0x0, 32, 0x1}
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case ADIVW:
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return &inst{0x3b, 0x4, 0x0, 32, 0x1}
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case ADRET:
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return &inst{0x73, 0x0, 0x12, 1970, 0x3d}
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case AEBREAK:
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return &inst{0x73, 0x0, 0x1, 1, 0x0}
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case AECALL:
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@ -337,6 +367,14 @@ func encode(a obj.As) *inst {
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return &inst{0x3, 0x2, 0x0, 0, 0x0}
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case ALWU:
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return &inst{0x3, 0x6, 0x0, 0, 0x0}
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case AMAX:
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return &inst{0x33, 0x6, 0x0, 160, 0x5}
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case AMAXU:
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return &inst{0x33, 0x7, 0x0, 160, 0x5}
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case AMIN:
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return &inst{0x33, 0x4, 0x0, 160, 0x5}
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case AMINU:
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return &inst{0x33, 0x5, 0x0, 160, 0x5}
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case AMRET:
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return &inst{0x73, 0x0, 0x2, 770, 0x18}
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case AMUL:
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@ -351,8 +389,12 @@ func encode(a obj.As) *inst {
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return &inst{0x3b, 0x0, 0x0, 32, 0x1}
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case AOR:
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return &inst{0x33, 0x6, 0x0, 0, 0x0}
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case AORCB:
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return &inst{0x13, 0x5, 0x7, 647, 0x14}
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case AORI:
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return &inst{0x13, 0x6, 0x0, 0, 0x0}
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case AORN:
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return &inst{0x33, 0x6, 0x0, 1024, 0x20}
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case APAUSE:
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return &inst{0xf, 0x0, 0x10, 16, 0x0}
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case ARDCYCLE:
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@ -375,6 +417,20 @@ func encode(a obj.As) *inst {
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return &inst{0x3b, 0x7, 0x0, 32, 0x1}
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case AREMW:
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return &inst{0x3b, 0x6, 0x0, 32, 0x1}
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case AREV8:
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return &inst{0x13, 0x5, 0x18, 1720, 0x35}
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case AROL:
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return &inst{0x33, 0x1, 0x0, 1536, 0x30}
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case AROLW:
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return &inst{0x3b, 0x1, 0x0, 1536, 0x30}
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case AROR:
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return &inst{0x33, 0x5, 0x0, 1536, 0x30}
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case ARORI:
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return &inst{0x13, 0x5, 0x0, 1536, 0x30}
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case ARORIW:
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return &inst{0x1b, 0x5, 0x0, 1536, 0x30}
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case ARORW:
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return &inst{0x3b, 0x5, 0x0, 1536, 0x30}
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case ASB:
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return &inst{0x23, 0x0, 0x0, 0, 0x0}
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case ASBREAK:
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@ -387,14 +443,32 @@ func encode(a obj.As) *inst {
|
||||
return &inst{0x73, 0x0, 0x0, 0, 0x0}
|
||||
case ASD:
|
||||
return &inst{0x23, 0x3, 0x0, 0, 0x0}
|
||||
case ASEXTB:
|
||||
return &inst{0x13, 0x1, 0x4, 1540, 0x30}
|
||||
case ASEXTH:
|
||||
return &inst{0x13, 0x1, 0x5, 1541, 0x30}
|
||||
case ASFENCEVMA:
|
||||
return &inst{0x73, 0x0, 0x0, 288, 0x9}
|
||||
case ASH:
|
||||
return &inst{0x23, 0x1, 0x0, 0, 0x0}
|
||||
case ASH1ADD:
|
||||
return &inst{0x33, 0x2, 0x0, 512, 0x10}
|
||||
case ASH1ADDUW:
|
||||
return &inst{0x3b, 0x2, 0x0, 512, 0x10}
|
||||
case ASH2ADD:
|
||||
return &inst{0x33, 0x4, 0x0, 512, 0x10}
|
||||
case ASH2ADDUW:
|
||||
return &inst{0x3b, 0x4, 0x0, 512, 0x10}
|
||||
case ASH3ADD:
|
||||
return &inst{0x33, 0x6, 0x0, 512, 0x10}
|
||||
case ASH3ADDUW:
|
||||
return &inst{0x3b, 0x6, 0x0, 512, 0x10}
|
||||
case ASLL:
|
||||
return &inst{0x33, 0x1, 0x0, 0, 0x0}
|
||||
case ASLLI:
|
||||
return &inst{0x13, 0x1, 0x0, 0, 0x0}
|
||||
case ASLLIUW:
|
||||
return &inst{0x1b, 0x1, 0x0, 128, 0x4}
|
||||
case ASLLIW:
|
||||
return &inst{0x1b, 0x1, 0x0, 0, 0x0}
|
||||
case ASLLW:
|
||||
@ -433,10 +507,14 @@ func encode(a obj.As) *inst {
|
||||
return &inst{0x23, 0x2, 0x0, 0, 0x0}
|
||||
case AWFI:
|
||||
return &inst{0x73, 0x0, 0x5, 261, 0x8}
|
||||
case AXNOR:
|
||||
return &inst{0x33, 0x4, 0x0, 1024, 0x20}
|
||||
case AXOR:
|
||||
return &inst{0x33, 0x4, 0x0, 0, 0x0}
|
||||
case AXORI:
|
||||
return &inst{0x13, 0x4, 0x0, 0, 0x0}
|
||||
case AZEXTH:
|
||||
return &inst{0x3b, 0x4, 0x0, 128, 0x4}
|
||||
}
|
||||
return nil
|
||||
}
|
||||
|
||||
@ -60,7 +60,9 @@ func progedit(ctxt *obj.Link, p *obj.Prog, newprog obj.ProgAlloc) {
|
||||
AADD, AAND, AOR, AXOR, ASLL, ASRL, ASUB, ASRA,
|
||||
AMUL, AMULH, AMULHU, AMULHSU, AMULW, ADIV, ADIVU, ADIVW, ADIVUW,
|
||||
AREM, AREMU, AREMW, AREMUW,
|
||||
AROL, AROLW, AROR, ARORW, ARORI, ARORIW:
|
||||
AADDUW, ASH1ADD, ASH1ADDUW, ASH2ADD, ASH2ADDUW, ASH3ADD, ASH3ADDUW, ASLLIUW,
|
||||
AANDN, AORN, AXNOR, AMAX, AMAXU, AMIN, AMINU, AROL, AROLW, AROR, ARORW, ARORI, ARORIW,
|
||||
ABCLR, ABCLRI, ABEXT, ABEXTI, ABINV, ABINVI, ABSET, ABSETI:
|
||||
p.Reg = p.To.Reg
|
||||
}
|
||||
}
|
||||
@ -91,10 +93,6 @@ func progedit(ctxt *obj.Link, p *obj.Prog, newprog obj.ProgAlloc) {
|
||||
p.As = ASRAI
|
||||
case AADDW:
|
||||
p.As = AADDIW
|
||||
case AROR:
|
||||
p.As = ARORI
|
||||
case ARORW:
|
||||
p.As = ARORIW
|
||||
case ASUBW:
|
||||
p.As, p.From.Offset = AADDIW, -p.From.Offset
|
||||
case ASLLW:
|
||||
@ -103,6 +101,18 @@ func progedit(ctxt *obj.Link, p *obj.Prog, newprog obj.ProgAlloc) {
|
||||
p.As = ASRLIW
|
||||
case ASRAW:
|
||||
p.As = ASRAIW
|
||||
case AROR:
|
||||
p.As = ARORI
|
||||
case ARORW:
|
||||
p.As = ARORIW
|
||||
case ABCLR:
|
||||
p.As = ABCLRI
|
||||
case ABEXT:
|
||||
p.As = ABEXTI
|
||||
case ABINV:
|
||||
p.As = ABINVI
|
||||
case ABSET:
|
||||
p.As = ABSETI
|
||||
}
|
||||
}
|
||||
|
||||
@ -1108,6 +1118,13 @@ func wantEvenOffset(ctxt *obj.Link, ins *instruction, offset int64) {
|
||||
}
|
||||
}
|
||||
|
||||
func validateRII(ctxt *obj.Link, ins *instruction) {
|
||||
wantIntReg(ctxt, ins, "rd", ins.rd)
|
||||
wantIntReg(ctxt, ins, "rs1", ins.rs1)
|
||||
wantNoneReg(ctxt, ins, "rs2", ins.rs2)
|
||||
wantNoneReg(ctxt, ins, "rs3", ins.rs3)
|
||||
}
|
||||
|
||||
func validateRIII(ctxt *obj.Link, ins *instruction) {
|
||||
wantIntReg(ctxt, ins, "rd", ins.rd)
|
||||
wantIntReg(ctxt, ins, "rs1", ins.rs1)
|
||||
@ -1261,6 +1278,10 @@ func encodeR4(as obj.As, rs1, rs2, rs3, rd, funct3, funct2 uint32) uint32 {
|
||||
return rs3<<27 | funct2<<25 | rs2<<20 | rs1<<15 | enc.funct3<<12 | funct3<<12 | rd<<7 | enc.opcode
|
||||
}
|
||||
|
||||
func encodeRII(ins *instruction) uint32 {
|
||||
return encodeR(ins.as, regI(ins.rs1), 0, regI(ins.rd), ins.funct3, ins.funct7)
|
||||
}
|
||||
|
||||
func encodeRIII(ins *instruction) uint32 {
|
||||
return encodeR(ins.as, regI(ins.rs1), regI(ins.rs2), regI(ins.rd), ins.funct3, ins.funct7)
|
||||
}
|
||||
@ -1492,6 +1513,7 @@ var (
|
||||
// indicates an S-type instruction with rs2 being a float register.
|
||||
|
||||
rIIIEncoding = encoding{encode: encodeRIII, validate: validateRIII, length: 4}
|
||||
rIIEncoding = encoding{encode: encodeRII, validate: validateRII, length: 4}
|
||||
rFFFEncoding = encoding{encode: encodeRFFF, validate: validateRFFF, length: 4}
|
||||
rFFFFEncoding = encoding{encode: encodeRFFFF, validate: validateRFFFF, length: 4}
|
||||
rFFIEncoding = encoding{encode: encodeRFFI, validate: validateRFFI, length: 4}
|
||||
@ -1724,6 +1746,58 @@ var encodings = [ALAST & obj.AMask]encoding{
|
||||
AECALL & obj.AMask: iIEncoding,
|
||||
AEBREAK & obj.AMask: iIEncoding,
|
||||
|
||||
//
|
||||
// RISC-V Bit-Manipulation ISA-extensions (1.0)
|
||||
//
|
||||
|
||||
// 1.1: Address Generation Instructions (Zba)
|
||||
AADDUW & obj.AMask: rIIIEncoding,
|
||||
ASH1ADD & obj.AMask: rIIIEncoding,
|
||||
ASH1ADDUW & obj.AMask: rIIIEncoding,
|
||||
ASH2ADD & obj.AMask: rIIIEncoding,
|
||||
ASH2ADDUW & obj.AMask: rIIIEncoding,
|
||||
ASH3ADD & obj.AMask: rIIIEncoding,
|
||||
ASH3ADDUW & obj.AMask: rIIIEncoding,
|
||||
ASLLIUW & obj.AMask: iIEncoding,
|
||||
|
||||
// 1.2: Basic Bit Manipulation (Zbb)
|
||||
AANDN & obj.AMask: rIIIEncoding,
|
||||
ACLZ & obj.AMask: rIIEncoding,
|
||||
ACLZW & obj.AMask: rIIEncoding,
|
||||
ACPOP & obj.AMask: rIIEncoding,
|
||||
ACPOPW & obj.AMask: rIIEncoding,
|
||||
ACTZ & obj.AMask: rIIEncoding,
|
||||
ACTZW & obj.AMask: rIIEncoding,
|
||||
AMAX & obj.AMask: rIIIEncoding,
|
||||
AMAXU & obj.AMask: rIIIEncoding,
|
||||
AMIN & obj.AMask: rIIIEncoding,
|
||||
AMINU & obj.AMask: rIIIEncoding,
|
||||
AORN & obj.AMask: rIIIEncoding,
|
||||
ASEXTB & obj.AMask: rIIEncoding,
|
||||
ASEXTH & obj.AMask: rIIEncoding,
|
||||
AXNOR & obj.AMask: rIIIEncoding,
|
||||
AZEXTH & obj.AMask: rIIEncoding,
|
||||
|
||||
// 1.3: Bitwise Rotation (Zbb)
|
||||
AROL & obj.AMask: rIIIEncoding,
|
||||
AROLW & obj.AMask: rIIIEncoding,
|
||||
AROR & obj.AMask: rIIIEncoding,
|
||||
ARORI & obj.AMask: iIEncoding,
|
||||
ARORIW & obj.AMask: iIEncoding,
|
||||
ARORW & obj.AMask: rIIIEncoding,
|
||||
AORCB & obj.AMask: iIEncoding,
|
||||
AREV8 & obj.AMask: iIEncoding,
|
||||
|
||||
// 1.5: Single-bit Instructions (Zbs)
|
||||
ABCLR & obj.AMask: rIIIEncoding,
|
||||
ABCLRI & obj.AMask: iIEncoding,
|
||||
ABEXT & obj.AMask: rIIIEncoding,
|
||||
ABEXTI & obj.AMask: iIEncoding,
|
||||
ABINV & obj.AMask: rIIIEncoding,
|
||||
ABINVI & obj.AMask: iIEncoding,
|
||||
ABSET & obj.AMask: rIIIEncoding,
|
||||
ABSETI & obj.AMask: iIEncoding,
|
||||
|
||||
// Escape hatch
|
||||
AWORD & obj.AMask: rawEncoding,
|
||||
|
||||
@ -2421,6 +2495,12 @@ func instructionsForProg(p *obj.Prog) []*instruction {
|
||||
if ins.imm < 0 || ins.imm > 31 {
|
||||
p.Ctxt.Diag("%v: shift amount out of range 0 to 31", p)
|
||||
}
|
||||
|
||||
case ACLZ, ACLZW, ACTZ, ACTZW, ACPOP, ACPOPW, ASEXTB, ASEXTH, AZEXTH:
|
||||
ins.rs1, ins.rs2 = uint32(p.From.Reg), obj.REG_NONE
|
||||
|
||||
case AORCB, AREV8:
|
||||
ins.rd, ins.rs1, ins.rs2 = uint32(p.To.Reg), uint32(p.From.Reg), obj.REG_NONE
|
||||
}
|
||||
|
||||
for _, ins := range inss {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user