mirror of
https://github.com/golang/go
synced 2024-11-26 06:27:58 -07:00
runtime/cgo,cmd/internal/obj/ppc64: fix signals with cgo
Recently some tsan tests were enabled on ppc64le which had not been enabled before. This resulted in failures on systems with tsan available, and while debugging it was determined that there were other issues related to the use of signals with cgo. Signals were not being forwarded within programs linked against libtsan because the nocgo sigaction was being called for ppc64le with or without cgo. Adding callCgoSigaction and calling that allows signals to be registered so that signal forwarding works. For linux-ppc64 and aix-ppc64, this won't change. On linux-ppc64 there is no cgo. I can't test aix-ppc64 so those owners can enable it if they want. In reviewing comments about sigtramp in sys_linux_arm64 it was noted that a previous issue in arm64 due to missing callee save registers could also be a problem on ppc64x, so code was added to save and restore those. Also, the use of R31 as a temp register in some cases caused an issue since it is a nonvolatile register in C and was being clobbered in cases where the C code expected it to be valid. The code sequences to load these addresses were changed to avoid the use of R31 when loading such an address. To get around a vet error, the stubs_ppc64x.go file in runtime was split into stubs_ppc64.go and stubs_ppc64le.go. Updates #45040 Change-Id: Ia4ecff950613cbe1b89471790b1d3819d5b5cfb9 Reviewed-on: https://go-review.googlesource.com/c/go/+/306369 Trust: Lynn Boger <laboger@linux.vnet.ibm.com> Run-TryBot: Lynn Boger <laboger@linux.vnet.ibm.com> TryBot-Result: Go Bot <gobot@golang.org> Reviewed-by: Carlos Eduardo Seo <carlos.seo@linaro.org>
This commit is contained in:
Lynn Boger
parent
deb3403ff5
commit
d9e068d289
4
src/cmd/asm/internal/asm/testdata/ppc64.s
vendored
4
src/cmd/asm/internal/asm/testdata/ppc64.s
vendored
@ -41,8 +41,8 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0
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MOVDBR (R3)(R4), R5 // 7ca41c28
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MOVWBR (R3)(R4), R5 // 7ca41c2c
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MOVHBR (R3)(R4), R5 // 7ca41e2c
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MOVD $foo+4009806848(FP), R5 // 3fe1ef0138bfcc20
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MOVD $foo(SB), R5 // 3fe0000038bf0000
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MOVD $foo+4009806848(FP), R5 // 3ca1ef0138a5cc20
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MOVD $foo(SB), R5 // 3ca0000038a50000
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MOVDU 8(R3), R4 // e8830009
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MOVDU (R3)(R4), R5 // 7ca4186a
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@ -2220,7 +2220,7 @@ func (c *ctxt9) opform(insn uint32) int {
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// Encode instructions and create relocation for accessing s+d according to the
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// instruction op with source or destination (as appropriate) register reg.
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func (c *ctxt9) symbolAccess(s *obj.LSym, d int64, reg int16, op uint32) (o1, o2 uint32) {
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func (c *ctxt9) symbolAccess(s *obj.LSym, d int64, reg int16, op uint32, reuse bool) (o1, o2 uint32) {
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if c.ctxt.Headtype == objabi.Haix {
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// Every symbol access must be made via a TOC anchor.
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c.ctxt.Diag("symbolAccess called for %s", s.Name)
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@ -2232,8 +2232,15 @@ func (c *ctxt9) symbolAccess(s *obj.LSym, d int64, reg int16, op uint32) (o1, o2
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} else {
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base = REG_R0
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}
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// If reg can be reused when computing the symbol address,
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// use it instead of REGTMP.
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if !reuse {
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o1 = AOP_IRR(OP_ADDIS, REGTMP, base, 0)
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o2 = AOP_IRR(op, uint32(reg), REGTMP, 0)
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} else {
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o1 = AOP_IRR(OP_ADDIS, uint32(reg), base, 0)
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o2 = AOP_IRR(op, uint32(reg), uint32(reg), 0)
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}
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rel := obj.Addrel(c.cursym)
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rel.Off = int32(c.pc)
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rel.Siz = 8
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@ -2877,14 +2884,14 @@ func (c *ctxt9) asmout(p *obj.Prog, o *Optab, out []uint32) {
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switch p.From.Name {
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case obj.NAME_EXTERN, obj.NAME_STATIC:
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// Load a 32 bit constant, or relocation depending on if a symbol is attached
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o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, OP_ADDI)
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o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, OP_ADDI, true)
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default:
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if r == 0 {
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r = c.getimpliedreg(&p.From, p)
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}
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// Add a 32 bit offset to a register.
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o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(int32(v))))
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o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGTMP, uint32(v))
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o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), uint32(r), uint32(high16adjusted(int32(v))))
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o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(v))
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}
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case 27: /* subc ra,$simm,rd => subfic rd,ra,$simm */
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@ -3043,10 +3050,10 @@ func (c *ctxt9) asmout(p *obj.Prog, o *Optab, out []uint32) {
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if r == 0 {
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r = c.getimpliedreg(&p.From, p)
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}
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o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v)))
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o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), REGTMP, uint32(v))
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o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), uint32(r), uint32(high16adjusted(v)))
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o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(p.To.Reg), uint32(v))
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// Sign extend MOVB operations. This is ignored for other cases (o.size == 8).
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// Sign extend MOVB if needed
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o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
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case 40: /* word */
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@ -3404,7 +3411,8 @@ func (c *ctxt9) asmout(p *obj.Prog, o *Optab, out []uint32) {
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if c.opform(inst) == DS_FORM && v&0x3 != 0 {
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log.Fatalf("invalid offset for DS form load/store %v", p)
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}
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o1, o2 = c.symbolAccess(p.To.Sym, v, p.From.Reg, inst)
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// Can't reuse base for store instructions.
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o1, o2 = c.symbolAccess(p.To.Sym, v, p.From.Reg, inst, false)
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case 75: // 32 bit offset symbol loads (got/toc/addr)
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v := p.From.Offset
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@ -3432,10 +3440,11 @@ func (c *ctxt9) asmout(p *obj.Prog, o *Optab, out []uint32) {
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rel.Type = objabi.R_ADDRPOWER_TOCREL_DS
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}
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default:
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o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst)
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reuseBaseReg := p.As != AFMOVD && p.As != AFMOVS
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// Reuse To.Reg as base register if not FP move.
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o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst, reuseBaseReg)
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}
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// Sign extend MOVB operations. This is ignored for other cases (o.size == 8).
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o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
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case 79:
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@ -2,7 +2,7 @@
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// +build linux,amd64 linux,arm64
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// +build linux,amd64 linux,arm64 linux,ppc64le
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#include <errno.h>
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#include <stdint.h>
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@ -2,7 +2,7 @@
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// +build linux,amd64 linux,arm64
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// +build linux,amd64 linux,arm64 linux,ppc64le
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#include <errno.h>
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#include <stddef.h>
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@ -2,8 +2,8 @@
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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//go:build (linux && amd64) || (freebsd && amd64) || (linux && arm64)
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// +build linux,amd64 freebsd,amd64 linux,arm64
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//go:build (linux && amd64) || (freebsd && amd64) || (linux && arm64) || (linux && ppc64le)
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// +build linux,amd64 freebsd,amd64 linux,arm64 linux,ppc64le
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package cgo
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@ -11,8 +11,8 @@ package cgo
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import _ "unsafe"
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// When using cgo, call the C library for sigaction, so that we call into
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// any sanitizer interceptors. This supports using the memory
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// sanitizer with Go programs. The memory sanitizer only applies to
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// any sanitizer interceptors. This supports using the sanitizers
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// with Go programs. The thread and memory sanitizers only apply to
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// C/C++ code; this permits that code to see the Go runtime's existing signal
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// handlers when registering new signal handlers for the process.
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@ -2,10 +2,10 @@
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// Support for memory sanitizer. See runtime/cgo/sigaction.go.
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// Support for sanitizers. See runtime/cgo/sigaction.go.
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//go:build (linux && amd64) || (freebsd && amd64) || (linux && arm64)
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// +build linux,amd64 freebsd,amd64 linux,arm64
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//go:build (linux && amd64) || (freebsd && amd64) || (linux && arm64) || (linux && ppc64le)
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// +build linux,amd64 freebsd,amd64 linux,arm64 linux,ppc64le
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package runtime
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@ -2,8 +2,8 @@
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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//go:build (linux && !amd64 && !arm64) || (freebsd && !amd64)
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// +build linux,!amd64,!arm64 freebsd,!amd64
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//go:build (linux && !amd64 && !arm64 && !ppc64le) || (freebsd && !amd64)
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// +build linux,!amd64,!arm64,!ppc64le freebsd,!amd64
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package runtime
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16
src/runtime/stubs_ppc64.go
Normal file
16
src/runtime/stubs_ppc64.go
Normal file
@ -0,0 +1,16 @@
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// Copyright 2021 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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//go:build linux
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// +build linux
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package runtime
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// Called from assembly only; declared for go vet.
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func load_g()
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func save_g()
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func reginit()
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//go:noescape
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func callCgoSigaction(sig uintptr, new, old *sigactiont) int32
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@ -2,9 +2,6 @@
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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//go:build ppc64 || ppc64le
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// +build ppc64 ppc64le
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package runtime
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// Called from assembly only; declared for go vet.
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@ -336,6 +336,26 @@ TEXT runtime·rt_sigaction(SB),NOSPLIT|NOFRAME,$0-36
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MOVW R3, ret+32(FP)
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RET
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#ifdef GOARCH_ppc64le
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// Call the function stored in _cgo_sigaction using the GCC calling convention.
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TEXT runtime·callCgoSigaction(SB),NOSPLIT,$0
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MOVD sig+0(FP), R3
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MOVD new+8(FP), R4
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MOVD old+16(FP), R5
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MOVD _cgo_sigaction(SB), R12
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MOVD R12, CTR // R12 should contain the function address
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MOVD R1, R15 // Save R1
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MOVD R2, 24(R1) // Save R2
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SUB $48, R1 // reserve 32 (frame) + 16 bytes for sp-8 where fp may be saved.
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RLDICR $0, R1, $59, R1 // Align to 16 bytes for C code
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BL (CTR)
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XOR R0, R0, R0 // Clear R0 as Go expects
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MOVD R15, R1 // Restore R1
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MOVD 24(R1), R2 // Restore R2
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MOVW R3, ret+24(FP) // Return result
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RET
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#endif
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TEXT runtime·sigfwd(SB),NOSPLIT,$0-32
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MOVW sig+8(FP), R3
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MOVD info+16(FP), R4
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@ -351,15 +371,97 @@ TEXT runtime·sigreturn(SB),NOSPLIT,$0-0
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#ifdef GOARCH_ppc64le
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// ppc64le doesn't need function descriptors
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TEXT runtime·sigtramp(SB),NOSPLIT,$64
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// Save callee-save registers in the case of signal forwarding.
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// Same as on ARM64 https://golang.org/issue/31827 .
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TEXT runtime·sigtramp(SB),NOSPLIT|NOFRAME,$0
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#else
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// function descriptor for the real sigtramp
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TEXT runtime·sigtramp(SB),NOSPLIT|NOFRAME,$0
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DWORD $sigtramp<>(SB)
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DWORD $0
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DWORD $0
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TEXT sigtramp<>(SB),NOSPLIT,$64
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TEXT sigtramp<>(SB),NOSPLIT|NOFRAME,$0
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#endif
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// Start with standard C stack frame layout and linkage.
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MOVD LR, R0
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MOVD R0, 16(R1) // Save LR in caller's frame.
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MOVW CR, R0 // Save CR in caller's frame
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MOVD R0, 8(R1)
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// The stack must be acquired here and not
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// in the automatic way based on stack size
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// since that sequence clobbers R31 before it
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// gets saved.
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// We are being ultra safe here in saving the
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// Vregs. The case where they might need to
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// be saved is very unlikely.
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MOVDU R1, -544(R1)
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MOVD R14, 64(R1)
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MOVD R15, 72(R1)
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MOVD R16, 80(R1)
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MOVD R17, 88(R1)
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MOVD R18, 96(R1)
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MOVD R19, 104(R1)
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MOVD R20, 112(R1)
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MOVD R21, 120(R1)
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MOVD R22, 128(R1)
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MOVD R23, 136(R1)
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MOVD R24, 144(R1)
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MOVD R25, 152(R1)
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MOVD R26, 160(R1)
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MOVD R27, 168(R1)
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MOVD R28, 176(R1)
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MOVD R29, 184(R1)
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MOVD g, 192(R1) // R30
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MOVD R31, 200(R1)
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FMOVD F14, 208(R1)
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FMOVD F15, 216(R1)
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FMOVD F16, 224(R1)
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FMOVD F17, 232(R1)
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FMOVD F18, 240(R1)
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FMOVD F19, 248(R1)
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FMOVD F20, 256(R1)
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FMOVD F21, 264(R1)
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FMOVD F22, 272(R1)
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FMOVD F23, 280(R1)
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FMOVD F24, 288(R1)
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FMOVD F25, 296(R1)
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FMOVD F26, 304(R1)
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FMOVD F27, 312(R1)
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FMOVD F28, 320(R1)
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FMOVD F29, 328(R1)
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FMOVD F30, 336(R1)
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FMOVD F31, 344(R1)
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// Save V regs
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// STXVD2X and LXVD2X used since
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// we aren't sure of alignment.
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// Endianness doesn't matter
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// if we are just loading and
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// storing values.
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MOVD $352, R7 // V20
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STXVD2X VS52, (R7)(R1)
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ADD $16, R7 // V21 368
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STXVD2X VS53, (R7)(R1)
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ADD $16, R7 // V22 384
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STXVD2X VS54, (R7)(R1)
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ADD $16, R7 // V23 400
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STXVD2X VS55, (R7)(R1)
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ADD $16, R7 // V24 416
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STXVD2X VS56, (R7)(R1)
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ADD $16, R7 // V25 432
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STXVD2X VS57, (R7)(R1)
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ADD $16, R7 // V26 448
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STXVD2X VS58, (R7)(R1)
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ADD $16, R7 // V27 464
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STXVD2X VS59, (R7)(R1)
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ADD $16, R7 // V28 480
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STXVD2X VS60, (R7)(R1)
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ADD $16, R7 // V29 496
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STXVD2X VS61, (R7)(R1)
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ADD $16, R7 // V30 512
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STXVD2X VS62, (R7)(R1)
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ADD $16, R7 // V31 528
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STXVD2X VS63, (R7)(R1)
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// initialize essential registers (just in case)
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BL runtime·reginit(SB)
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@ -376,7 +478,74 @@ TEXT sigtramp<>(SB),NOSPLIT,$64
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MOVD $runtime·sigtrampgo(SB), R12
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MOVD R12, CTR
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BL (CTR)
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MOVD 24(R1), R2
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MOVD 24(R1), R2 // Should this be here? Where is it saved?
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// Starts at 64; FIXED_FRAME is 32
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MOVD 64(R1), R14
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MOVD 72(R1), R15
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MOVD 80(R1), R16
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MOVD 88(R1), R17
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MOVD 96(R1), R18
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MOVD 104(R1), R19
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MOVD 112(R1), R20
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MOVD 120(R1), R21
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MOVD 128(R1), R22
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MOVD 136(R1), R23
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MOVD 144(R1), R24
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MOVD 152(R1), R25
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MOVD 160(R1), R26
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MOVD 168(R1), R27
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MOVD 176(R1), R28
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MOVD 184(R1), R29
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MOVD 192(R1), g // R30
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MOVD 200(R1), R31
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FMOVD 208(R1), F14
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FMOVD 216(R1), F15
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FMOVD 224(R1), F16
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FMOVD 232(R1), F17
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FMOVD 240(R1), F18
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FMOVD 248(R1), F19
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FMOVD 256(R1), F20
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FMOVD 264(R1), F21
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FMOVD 272(R1), F22
|
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FMOVD 280(R1), F23
|
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FMOVD 288(R1), F24
|
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FMOVD 292(R1), F25
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FMOVD 300(R1), F26
|
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FMOVD 308(R1), F27
|
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FMOVD 316(R1), F28
|
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FMOVD 328(R1), F29
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FMOVD 336(R1), F30
|
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FMOVD 344(R1), F31
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MOVD $352, R7
|
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LXVD2X (R7)(R1), VS52
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ADD $16, R7 // 368 V21
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LXVD2X (R7)(R1), VS53
|
||||
ADD $16, R7 // 384 V22
|
||||
LXVD2X (R7)(R1), VS54
|
||||
ADD $16, R7 // 400 V23
|
||||
LXVD2X (R7)(R1), VS55
|
||||
ADD $16, R7 // 416 V24
|
||||
LXVD2X (R7)(R1), VS56
|
||||
ADD $16, R7 // 432 V25
|
||||
LXVD2X (R7)(R1), VS57
|
||||
ADD $16, R7 // 448 V26
|
||||
LXVD2X (R7)(R1), VS58
|
||||
ADD $16, R8 // 464 V27
|
||||
LXVD2X (R7)(R1), VS59
|
||||
ADD $16, R7 // 480 V28
|
||||
LXVD2X (R7)(R1), VS60
|
||||
ADD $16, R7 // 496 V29
|
||||
LXVD2X (R7)(R1), VS61
|
||||
ADD $16, R7 // 512 V30
|
||||
LXVD2X (R7)(R1), VS62
|
||||
ADD $16, R7 // 528 V31
|
||||
LXVD2X (R7)(R1), VS63
|
||||
ADD $544, R1
|
||||
MOVD 8(R1), R0
|
||||
MOVFL R0, $0xff
|
||||
MOVD 16(R1), R0
|
||||
MOVD R0, LR
|
||||
|
||||
RET
|
||||
|
||||
#ifdef GOARCH_ppc64le
|
||||
@ -406,6 +575,7 @@ TEXT runtime·cgoSigtramp(SB),NOSPLIT|NOFRAME,$0
|
||||
|
||||
// Figure out if we are currently in a cgo call.
|
||||
// If not, just do usual sigtramp.
|
||||
// compared to ARM64 and others.
|
||||
CMP $0, g
|
||||
BEQ sigtrampnog // g == nil
|
||||
MOVD g_m(g), R6
|
||||
|
||||
Loading…
Reference in New Issue
Block a user