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[dev.ssa] cmd/compile: use 2-result divide op
We now allow Values to have 2 outputs. Use that ability for amd64. This allows x,y := a/b,a%b to use just a single divide instruction. Update #6815 Change-Id: Id70bcd20188a2dd8445e631a11d11f60991921e4 Reviewed-on: https://go-review.googlesource.com/25004 Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com> Reviewed-by: David Chase <drchase@google.com>
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@ -209,89 +209,87 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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}
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}
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opregreg(v.Op.Asm(), r, gc.SSARegNum(v.Args[1]))
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opregreg(v.Op.Asm(), r, gc.SSARegNum(v.Args[1]))
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case ssa.OpAMD64DIVQ, ssa.OpAMD64DIVL, ssa.OpAMD64DIVW,
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case ssa.OpAMD64DIVQU, ssa.OpAMD64DIVLU, ssa.OpAMD64DIVWU:
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ssa.OpAMD64DIVQU, ssa.OpAMD64DIVLU, ssa.OpAMD64DIVWU,
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// Arg[0] (the dividend) is in AX.
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ssa.OpAMD64MODQ, ssa.OpAMD64MODL, ssa.OpAMD64MODW,
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// Arg[1] (the divisor) can be in any other register.
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ssa.OpAMD64MODQU, ssa.OpAMD64MODLU, ssa.OpAMD64MODWU:
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// Result[0] (the quotient) is in AX.
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// Result[1] (the remainder) is in DX.
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r := gc.SSARegNum(v.Args[1])
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// Arg[0] is already in AX as it's the only register we allow
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// Zero extend dividend.
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// and AX is the only output
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c := gc.Prog(x86.AXORL)
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x := gc.SSARegNum(v.Args[1])
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c.From.Type = obj.TYPE_REG
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c.From.Reg = x86.REG_DX
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// CPU faults upon signed overflow, which occurs when most
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c.To.Type = obj.TYPE_REG
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// negative int is divided by -1.
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c.To.Reg = x86.REG_DX
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var j *obj.Prog
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if v.Op == ssa.OpAMD64DIVQ || v.Op == ssa.OpAMD64DIVL ||
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v.Op == ssa.OpAMD64DIVW || v.Op == ssa.OpAMD64MODQ ||
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v.Op == ssa.OpAMD64MODL || v.Op == ssa.OpAMD64MODW {
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var c *obj.Prog
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switch v.Op {
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case ssa.OpAMD64DIVQ, ssa.OpAMD64MODQ:
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c = gc.Prog(x86.ACMPQ)
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j = gc.Prog(x86.AJEQ)
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// go ahead and sign extend to save doing it later
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gc.Prog(x86.ACQO)
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case ssa.OpAMD64DIVL, ssa.OpAMD64MODL:
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c = gc.Prog(x86.ACMPL)
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j = gc.Prog(x86.AJEQ)
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gc.Prog(x86.ACDQ)
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case ssa.OpAMD64DIVW, ssa.OpAMD64MODW:
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c = gc.Prog(x86.ACMPW)
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j = gc.Prog(x86.AJEQ)
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gc.Prog(x86.ACWD)
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}
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c.From.Type = obj.TYPE_REG
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c.From.Reg = x
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c.To.Type = obj.TYPE_CONST
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c.To.Offset = -1
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j.To.Type = obj.TYPE_BRANCH
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}
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// for unsigned ints, we sign extend by setting DX = 0
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// signed ints were sign extended above
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if v.Op == ssa.OpAMD64DIVQU || v.Op == ssa.OpAMD64MODQU ||
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v.Op == ssa.OpAMD64DIVLU || v.Op == ssa.OpAMD64MODLU ||
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v.Op == ssa.OpAMD64DIVWU || v.Op == ssa.OpAMD64MODWU {
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c := gc.Prog(x86.AXORQ)
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c.From.Type = obj.TYPE_REG
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c.From.Reg = x86.REG_DX
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c.To.Type = obj.TYPE_REG
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c.To.Reg = x86.REG_DX
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}
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// Issue divide.
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p := gc.Prog(v.Op.Asm())
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Type = obj.TYPE_REG
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p.From.Reg = x
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p.From.Reg = r
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// signed division, rest of the check for -1 case
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case ssa.OpAMD64DIVQ, ssa.OpAMD64DIVL, ssa.OpAMD64DIVW:
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if j != nil {
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// Arg[0] (the dividend) is in AX.
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j2 := gc.Prog(obj.AJMP)
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// Arg[1] (the divisor) can be in any other register.
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j2.To.Type = obj.TYPE_BRANCH
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// Result[0] (the quotient) is in AX.
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// Result[1] (the remainder) is in DX.
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r := gc.SSARegNum(v.Args[1])
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var n *obj.Prog
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// CPU faults upon signed overflow, which occurs when the most
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if v.Op == ssa.OpAMD64DIVQ || v.Op == ssa.OpAMD64DIVL ||
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// negative int is divided by -1. Handle divide by -1 as a special case.
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v.Op == ssa.OpAMD64DIVW {
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var c *obj.Prog
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// n * -1 = -n
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switch v.Op {
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n = gc.Prog(x86.ANEGQ)
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case ssa.OpAMD64DIVQ:
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n.To.Type = obj.TYPE_REG
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c = gc.Prog(x86.ACMPQ)
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n.To.Reg = x86.REG_AX
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case ssa.OpAMD64DIVL:
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} else {
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c = gc.Prog(x86.ACMPL)
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// n % -1 == 0
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case ssa.OpAMD64DIVW:
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n = gc.Prog(x86.AXORQ)
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c = gc.Prog(x86.ACMPW)
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n.From.Type = obj.TYPE_REG
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n.From.Reg = x86.REG_DX
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n.To.Type = obj.TYPE_REG
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n.To.Reg = x86.REG_DX
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}
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j.To.Val = n
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j2.To.Val = s.Pc()
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}
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}
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c.From.Type = obj.TYPE_REG
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c.From.Reg = r
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c.To.Type = obj.TYPE_CONST
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c.To.Offset = -1
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j1 := gc.Prog(x86.AJEQ)
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j1.To.Type = obj.TYPE_BRANCH
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// Sign extend dividend.
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switch v.Op {
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case ssa.OpAMD64DIVQ:
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gc.Prog(x86.ACQO)
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case ssa.OpAMD64DIVL:
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gc.Prog(x86.ACDQ)
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case ssa.OpAMD64DIVW:
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gc.Prog(x86.ACWD)
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}
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// Issue divide.
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = r
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// Skip over -1 fixup code.
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j2 := gc.Prog(obj.AJMP)
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j2.To.Type = obj.TYPE_BRANCH
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// Issue -1 fixup code.
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// n / -1 = -n
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n1 := gc.Prog(x86.ANEGQ)
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n1.To.Type = obj.TYPE_REG
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n1.To.Reg = x86.REG_AX
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// n % -1 == 0
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n2 := gc.Prog(x86.AXORL)
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n2.From.Type = obj.TYPE_REG
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n2.From.Reg = x86.REG_DX
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n2.To.Type = obj.TYPE_REG
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n2.To.Reg = x86.REG_DX
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// TODO(khr): issue only the -1 fixup code we need.
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// For instance, if only the quotient is used, no point in zeroing the remainder.
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j1.To.Val = n1
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j2.To.Val = s.Pc()
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case ssa.OpAMD64HMULQ, ssa.OpAMD64HMULL, ssa.OpAMD64HMULW, ssa.OpAMD64HMULB,
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case ssa.OpAMD64HMULQ, ssa.OpAMD64HMULL, ssa.OpAMD64HMULW, ssa.OpAMD64HMULB,
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ssa.OpAMD64HMULQU, ssa.OpAMD64HMULLU, ssa.OpAMD64HMULWU, ssa.OpAMD64HMULBU:
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ssa.OpAMD64HMULQU, ssa.OpAMD64HMULLU, ssa.OpAMD64HMULWU, ssa.OpAMD64HMULBU:
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@ -818,6 +816,8 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.To.Reg = gc.SSARegNum(v)
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p.To.Reg = gc.SSARegNum(v)
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case ssa.OpSP, ssa.OpSB:
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case ssa.OpSP, ssa.OpSB:
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// nothing to do
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// nothing to do
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case ssa.OpSelect0, ssa.OpSelect1:
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// nothing to do
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case ssa.OpAMD64SETEQ, ssa.OpAMD64SETNE,
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case ssa.OpAMD64SETEQ, ssa.OpAMD64SETNE,
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ssa.OpAMD64SETL, ssa.OpAMD64SETLE,
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ssa.OpAMD64SETL, ssa.OpAMD64SETLE,
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ssa.OpAMD64SETG, ssa.OpAMD64SETGE,
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ssa.OpAMD64SETG, ssa.OpAMD64SETGE,
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@ -29,14 +29,14 @@
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(Div32F x y) -> (DIVSS x y)
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(Div32F x y) -> (DIVSS x y)
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(Div64F x y) -> (DIVSD x y)
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(Div64F x y) -> (DIVSD x y)
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(Div64 x y) -> (DIVQ x y)
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(Div64 x y) -> (Select0 (DIVQ x y <&TupleType{config.Frontend().TypeInt64(), config.Frontend().TypeInt64()}>))
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(Div64u x y) -> (DIVQU x y)
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(Div64u x y) -> (Select0 (DIVQU x y <&TupleType{config.Frontend().TypeUInt64(), config.Frontend().TypeUInt64()}>))
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(Div32 x y) -> (DIVL x y)
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(Div32 x y) -> (Select0 (DIVL x y <&TupleType{config.Frontend().TypeInt32(), config.Frontend().TypeInt32()}>))
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(Div32u x y) -> (DIVLU x y)
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(Div32u x y) -> (Select0 (DIVLU x y <&TupleType{config.Frontend().TypeUInt32(), config.Frontend().TypeUInt32()}>))
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(Div16 x y) -> (DIVW x y)
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(Div16 x y) -> (Select0 (DIVW x y <&TupleType{config.Frontend().TypeInt16(), config.Frontend().TypeInt16()}>))
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(Div16u x y) -> (DIVWU x y)
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(Div16u x y) -> (Select0 (DIVWU x y <&TupleType{config.Frontend().TypeUInt16(), config.Frontend().TypeUInt16()}>))
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(Div8 x y) -> (DIVW (SignExt8to16 x) (SignExt8to16 y))
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(Div8 x y) -> (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y) <&TupleType{config.Frontend().TypeInt8(), config.Frontend().TypeInt8()}>))
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(Div8u x y) -> (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))
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(Div8u x y) -> (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y) <&TupleType{config.Frontend().TypeUInt8(), config.Frontend().TypeUInt8()}>))
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(Hmul64 x y) -> (HMULQ x y)
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(Hmul64 x y) -> (HMULQ x y)
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(Hmul64u x y) -> (HMULQU x y)
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(Hmul64u x y) -> (HMULQU x y)
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@ -49,14 +49,14 @@
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(Avg64u x y) -> (AVGQU x y)
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(Avg64u x y) -> (AVGQU x y)
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(Mod64 x y) -> (MODQ x y)
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(Mod64 x y) -> (Select1 (DIVQ x y <&TupleType{config.Frontend().TypeInt64(), config.Frontend().TypeInt64()}>))
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(Mod64u x y) -> (MODQU x y)
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(Mod64u x y) -> (Select1 (DIVQU x y <&TupleType{config.Frontend().TypeUInt64(), config.Frontend().TypeUInt64()}>))
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(Mod32 x y) -> (MODL x y)
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(Mod32 x y) -> (Select1 (DIVL x y <&TupleType{config.Frontend().TypeInt32(), config.Frontend().TypeInt32()}>))
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(Mod32u x y) -> (MODLU x y)
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(Mod32u x y) -> (Select1 (DIVLU x y <&TupleType{config.Frontend().TypeUInt32(), config.Frontend().TypeUInt32()}>))
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(Mod16 x y) -> (MODW x y)
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(Mod16 x y) -> (Select1 (DIVW x y <&TupleType{config.Frontend().TypeInt16(), config.Frontend().TypeInt16()}>))
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(Mod16u x y) -> (MODWU x y)
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(Mod16u x y) -> (Select1 (DIVWU x y <&TupleType{config.Frontend().TypeUInt16(), config.Frontend().TypeUInt16()}>))
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(Mod8 x y) -> (MODW (SignExt8to16 x) (SignExt8to16 y))
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(Mod8 x y) -> (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y) <&TupleType{config.Frontend().TypeInt8(), config.Frontend().TypeInt8()}>))
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(Mod8u x y) -> (MODWU (ZeroExt8to16 x) (ZeroExt8to16 y))
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(Mod8u x y) -> (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y) <&TupleType{config.Frontend().TypeUInt8(), config.Frontend().TypeUInt8()}>))
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(And64 x y) -> (ANDQ x y)
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(And64 x y) -> (ANDQ x y)
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(And32 x y) -> (ANDL x y)
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(And32 x y) -> (ANDL x y)
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@ -119,12 +119,10 @@ func init() {
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gp21sp = regInfo{inputs: []regMask{gpsp, gp}, outputs: gponly, clobbers: flags}
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gp21sp = regInfo{inputs: []regMask{gpsp, gp}, outputs: gponly, clobbers: flags}
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gp21sb = regInfo{inputs: []regMask{gpspsb, gpsp}, outputs: gponly}
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gp21sb = regInfo{inputs: []regMask{gpspsb, gpsp}, outputs: gponly}
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gp21shift = regInfo{inputs: []regMask{gp, cx}, outputs: []regMask{gp}, clobbers: flags}
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gp21shift = regInfo{inputs: []regMask{gp, cx}, outputs: []regMask{gp}, clobbers: flags}
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gp11div = regInfo{inputs: []regMask{ax, gpsp &^ dx}, outputs: []regMask{ax},
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gp11div = regInfo{inputs: []regMask{ax, gpsp &^ dx}, outputs: []regMask{ax, dx},
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clobbers: dx | flags}
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clobbers: flags}
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gp11hmul = regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx},
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gp11hmul = regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx},
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clobbers: ax | flags}
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clobbers: ax | flags}
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gp11mod = regInfo{inputs: []regMask{ax, gpsp &^ dx}, outputs: []regMask{dx},
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clobbers: ax | flags}
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gp2flags = regInfo{inputs: []regMask{gpsp, gpsp}, outputs: flagsonly}
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gp2flags = regInfo{inputs: []regMask{gpsp, gpsp}, outputs: flagsonly}
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gp1flags = regInfo{inputs: []regMask{gpsp}, outputs: flagsonly}
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gp1flags = regInfo{inputs: []regMask{gpsp}, outputs: flagsonly}
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@ -214,19 +212,12 @@ func init() {
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{name: "AVGQU", argLength: 2, reg: gp21, commutative: true, resultInArg0: true}, // (arg0 + arg1) / 2 as unsigned, all 64 result bits
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{name: "AVGQU", argLength: 2, reg: gp21, commutative: true, resultInArg0: true}, // (arg0 + arg1) / 2 as unsigned, all 64 result bits
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{name: "DIVQ", argLength: 2, reg: gp11div, asm: "IDIVQ"}, // arg0 / arg1
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{name: "DIVQ", argLength: 2, reg: gp11div, asm: "IDIVQ"}, // [arg0 / arg1, arg0 % arg1]
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{name: "DIVL", argLength: 2, reg: gp11div, asm: "IDIVL"}, // arg0 / arg1
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{name: "DIVL", argLength: 2, reg: gp11div, asm: "IDIVL"}, // [arg0 / arg1, arg0 % arg1]
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{name: "DIVW", argLength: 2, reg: gp11div, asm: "IDIVW"}, // arg0 / arg1
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{name: "DIVW", argLength: 2, reg: gp11div, asm: "IDIVW"}, // [arg0 / arg1, arg0 % arg1]
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{name: "DIVQU", argLength: 2, reg: gp11div, asm: "DIVQ"}, // arg0 / arg1
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{name: "DIVQU", argLength: 2, reg: gp11div, asm: "DIVQ"}, // [arg0 / arg1, arg0 % arg1]
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{name: "DIVLU", argLength: 2, reg: gp11div, asm: "DIVL"}, // arg0 / arg1
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{name: "DIVLU", argLength: 2, reg: gp11div, asm: "DIVL"}, // [arg0 / arg1, arg0 % arg1]
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{name: "DIVWU", argLength: 2, reg: gp11div, asm: "DIVW"}, // arg0 / arg1
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{name: "DIVWU", argLength: 2, reg: gp11div, asm: "DIVW"}, // [arg0 / arg1, arg0 % arg1]
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{name: "MODQ", argLength: 2, reg: gp11mod, asm: "IDIVQ"}, // arg0 % arg1
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{name: "MODL", argLength: 2, reg: gp11mod, asm: "IDIVL"}, // arg0 % arg1
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{name: "MODW", argLength: 2, reg: gp11mod, asm: "IDIVW"}, // arg0 % arg1
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{name: "MODQU", argLength: 2, reg: gp11mod, asm: "DIVQ"}, // arg0 % arg1
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{name: "MODLU", argLength: 2, reg: gp11mod, asm: "DIVL"}, // arg0 % arg1
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{name: "MODWU", argLength: 2, reg: gp11mod, asm: "DIVW"}, // arg0 % arg1
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{name: "ANDQ", argLength: 2, reg: gp21, asm: "ANDQ", commutative: true, resultInArg0: true}, // arg0 & arg1
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{name: "ANDQ", argLength: 2, reg: gp21, asm: "ANDQ", commutative: true, resultInArg0: true}, // arg0 & arg1
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{name: "ANDL", argLength: 2, reg: gp21, asm: "ANDL", commutative: true, resultInArg0: true}, // arg0 & arg1
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{name: "ANDL", argLength: 2, reg: gp21, asm: "ANDL", commutative: true, resultInArg0: true}, // arg0 & arg1
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@ -368,12 +368,6 @@ const (
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OpAMD64DIVQU
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OpAMD64DIVQU
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OpAMD64DIVLU
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OpAMD64DIVLU
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OpAMD64DIVWU
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OpAMD64DIVWU
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OpAMD64MODQ
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OpAMD64MODL
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OpAMD64MODW
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OpAMD64MODQU
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OpAMD64MODLU
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OpAMD64MODWU
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OpAMD64ANDQ
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OpAMD64ANDQ
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OpAMD64ANDL
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OpAMD64ANDL
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OpAMD64ANDQconst
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OpAMD64ANDQconst
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@ -4129,9 +4123,10 @@ var opcodeTable = [...]opInfo{
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{0, 1}, // AX
|
{0, 1}, // AX
|
||||||
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||||
},
|
},
|
||||||
clobbers: 8589934596, // DX FLAGS
|
clobbers: 8589934592, // FLAGS
|
||||||
outputs: []outputInfo{
|
outputs: []outputInfo{
|
||||||
{0, 1}, // AX
|
{0, 1}, // AX
|
||||||
|
{1, 4}, // DX
|
||||||
},
|
},
|
||||||
},
|
},
|
||||||
},
|
},
|
||||||
@ -4144,9 +4139,10 @@ var opcodeTable = [...]opInfo{
|
|||||||
{0, 1}, // AX
|
{0, 1}, // AX
|
||||||
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||||
},
|
},
|
||||||
clobbers: 8589934596, // DX FLAGS
|
clobbers: 8589934592, // FLAGS
|
||||||
outputs: []outputInfo{
|
outputs: []outputInfo{
|
||||||
{0, 1}, // AX
|
{0, 1}, // AX
|
||||||
|
{1, 4}, // DX
|
||||||
},
|
},
|
||||||
},
|
},
|
||||||
},
|
},
|
||||||
@ -4159,9 +4155,10 @@ var opcodeTable = [...]opInfo{
|
|||||||
{0, 1}, // AX
|
{0, 1}, // AX
|
||||||
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||||
},
|
},
|
||||||
clobbers: 8589934596, // DX FLAGS
|
clobbers: 8589934592, // FLAGS
|
||||||
outputs: []outputInfo{
|
outputs: []outputInfo{
|
||||||
{0, 1}, // AX
|
{0, 1}, // AX
|
||||||
|
{1, 4}, // DX
|
||||||
},
|
},
|
||||||
},
|
},
|
||||||
},
|
},
|
||||||
@ -4174,9 +4171,10 @@ var opcodeTable = [...]opInfo{
|
|||||||
{0, 1}, // AX
|
{0, 1}, // AX
|
||||||
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||||
},
|
},
|
||||||
clobbers: 8589934596, // DX FLAGS
|
clobbers: 8589934592, // FLAGS
|
||||||
outputs: []outputInfo{
|
outputs: []outputInfo{
|
||||||
{0, 1}, // AX
|
{0, 1}, // AX
|
||||||
|
{1, 4}, // DX
|
||||||
},
|
},
|
||||||
},
|
},
|
||||||
},
|
},
|
||||||
@ -4189,9 +4187,10 @@ var opcodeTable = [...]opInfo{
|
|||||||
{0, 1}, // AX
|
{0, 1}, // AX
|
||||||
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||||
},
|
},
|
||||||
clobbers: 8589934596, // DX FLAGS
|
clobbers: 8589934592, // FLAGS
|
||||||
outputs: []outputInfo{
|
outputs: []outputInfo{
|
||||||
{0, 1}, // AX
|
{0, 1}, // AX
|
||||||
|
{1, 4}, // DX
|
||||||
},
|
},
|
||||||
},
|
},
|
||||||
},
|
},
|
||||||
@ -4204,99 +4203,10 @@ var opcodeTable = [...]opInfo{
|
|||||||
{0, 1}, // AX
|
{0, 1}, // AX
|
||||||
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
||||||
},
|
},
|
||||||
clobbers: 8589934596, // DX FLAGS
|
clobbers: 8589934592, // FLAGS
|
||||||
outputs: []outputInfo{
|
outputs: []outputInfo{
|
||||||
{0, 1}, // AX
|
{0, 1}, // AX
|
||||||
},
|
{1, 4}, // DX
|
||||||
},
|
|
||||||
},
|
|
||||||
{
|
|
||||||
name: "MODQ",
|
|
||||||
argLen: 2,
|
|
||||||
asm: x86.AIDIVQ,
|
|
||||||
reg: regInfo{
|
|
||||||
inputs: []inputInfo{
|
|
||||||
{0, 1}, // AX
|
|
||||||
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
||||||
},
|
|
||||||
clobbers: 8589934593, // AX FLAGS
|
|
||||||
outputs: []outputInfo{
|
|
||||||
{0, 4}, // DX
|
|
||||||
},
|
|
||||||
},
|
|
||||||
},
|
|
||||||
{
|
|
||||||
name: "MODL",
|
|
||||||
argLen: 2,
|
|
||||||
asm: x86.AIDIVL,
|
|
||||||
reg: regInfo{
|
|
||||||
inputs: []inputInfo{
|
|
||||||
{0, 1}, // AX
|
|
||||||
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
||||||
},
|
|
||||||
clobbers: 8589934593, // AX FLAGS
|
|
||||||
outputs: []outputInfo{
|
|
||||||
{0, 4}, // DX
|
|
||||||
},
|
|
||||||
},
|
|
||||||
},
|
|
||||||
{
|
|
||||||
name: "MODW",
|
|
||||||
argLen: 2,
|
|
||||||
asm: x86.AIDIVW,
|
|
||||||
reg: regInfo{
|
|
||||||
inputs: []inputInfo{
|
|
||||||
{0, 1}, // AX
|
|
||||||
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
||||||
},
|
|
||||||
clobbers: 8589934593, // AX FLAGS
|
|
||||||
outputs: []outputInfo{
|
|
||||||
{0, 4}, // DX
|
|
||||||
},
|
|
||||||
},
|
|
||||||
},
|
|
||||||
{
|
|
||||||
name: "MODQU",
|
|
||||||
argLen: 2,
|
|
||||||
asm: x86.ADIVQ,
|
|
||||||
reg: regInfo{
|
|
||||||
inputs: []inputInfo{
|
|
||||||
{0, 1}, // AX
|
|
||||||
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
||||||
},
|
|
||||||
clobbers: 8589934593, // AX FLAGS
|
|
||||||
outputs: []outputInfo{
|
|
||||||
{0, 4}, // DX
|
|
||||||
},
|
|
||||||
},
|
|
||||||
},
|
|
||||||
{
|
|
||||||
name: "MODLU",
|
|
||||||
argLen: 2,
|
|
||||||
asm: x86.ADIVL,
|
|
||||||
reg: regInfo{
|
|
||||||
inputs: []inputInfo{
|
|
||||||
{0, 1}, // AX
|
|
||||||
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
||||||
},
|
|
||||||
clobbers: 8589934593, // AX FLAGS
|
|
||||||
outputs: []outputInfo{
|
|
||||||
{0, 4}, // DX
|
|
||||||
},
|
|
||||||
},
|
|
||||||
},
|
|
||||||
{
|
|
||||||
name: "MODWU",
|
|
||||||
argLen: 2,
|
|
||||||
asm: x86.ADIVW,
|
|
||||||
reg: regInfo{
|
|
||||||
inputs: []inputInfo{
|
|
||||||
{0, 1}, // AX
|
|
||||||
{1, 65531}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
|
|
||||||
},
|
|
||||||
clobbers: 8589934593, // AX FLAGS
|
|
||||||
outputs: []outputInfo{
|
|
||||||
{0, 4}, // DX
|
|
||||||
},
|
},
|
||||||
},
|
},
|
||||||
},
|
},
|
||||||
@ -8909,8 +8819,8 @@ var opcodeTable = [...]opInfo{
|
|||||||
inputs: []inputInfo{
|
inputs: []inputInfo{
|
||||||
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
||||||
},
|
},
|
||||||
outputs: []regMask{
|
outputs: []outputInfo{
|
||||||
4294967296, // FLAGS
|
{0, 4294967296}, // FLAGS
|
||||||
},
|
},
|
||||||
},
|
},
|
||||||
},
|
},
|
||||||
@ -8922,8 +8832,8 @@ var opcodeTable = [...]opInfo{
|
|||||||
inputs: []inputInfo{
|
inputs: []inputInfo{
|
||||||
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
|
||||||
},
|
},
|
||||||
outputs: []regMask{
|
outputs: []outputInfo{
|
||||||
4294967296, // FLAGS
|
{0, 4294967296}, // FLAGS
|
||||||
},
|
},
|
||||||
},
|
},
|
||||||
},
|
},
|
||||||
|
@ -3275,13 +3275,15 @@ func rewriteValueAMD64_OpDiv16(v *Value, config *Config) bool {
|
|||||||
_ = b
|
_ = b
|
||||||
// match: (Div16 x y)
|
// match: (Div16 x y)
|
||||||
// cond:
|
// cond:
|
||||||
// result: (DIVW x y)
|
// result: (Select0 (DIVW x y <&TupleType{config.Frontend().TypeInt16(), config.Frontend().TypeInt16()}>))
|
||||||
for {
|
for {
|
||||||
x := v.Args[0]
|
x := v.Args[0]
|
||||||
y := v.Args[1]
|
y := v.Args[1]
|
||||||
v.reset(OpAMD64DIVW)
|
v.reset(OpSelect0)
|
||||||
v.AddArg(x)
|
v0 := b.NewValue0(v.Line, OpAMD64DIVW, &TupleType{config.Frontend().TypeInt16(), config.Frontend().TypeInt16()})
|
||||||
v.AddArg(y)
|
v0.AddArg(x)
|
||||||
|
v0.AddArg(y)
|
||||||
|
v.AddArg(v0)
|
||||||
return true
|
return true
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -3290,13 +3292,15 @@ func rewriteValueAMD64_OpDiv16u(v *Value, config *Config) bool {
|
|||||||
_ = b
|
_ = b
|
||||||
// match: (Div16u x y)
|
// match: (Div16u x y)
|
||||||
// cond:
|
// cond:
|
||||||
// result: (DIVWU x y)
|
// result: (Select0 (DIVWU x y <&TupleType{config.Frontend().TypeUInt16(), config.Frontend().TypeUInt16()}>))
|
||||||
for {
|
for {
|
||||||
x := v.Args[0]
|
x := v.Args[0]
|
||||||
y := v.Args[1]
|
y := v.Args[1]
|
||||||
v.reset(OpAMD64DIVWU)
|
v.reset(OpSelect0)
|
||||||
v.AddArg(x)
|
v0 := b.NewValue0(v.Line, OpAMD64DIVWU, &TupleType{config.Frontend().TypeUInt16(), config.Frontend().TypeUInt16()})
|
||||||
v.AddArg(y)
|
v0.AddArg(x)
|
||||||
|
v0.AddArg(y)
|
||||||
|
v.AddArg(v0)
|
||||||
return true
|
return true
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -3305,13 +3309,15 @@ func rewriteValueAMD64_OpDiv32(v *Value, config *Config) bool {
|
|||||||
_ = b
|
_ = b
|
||||||
// match: (Div32 x y)
|
// match: (Div32 x y)
|
||||||
// cond:
|
// cond:
|
||||||
// result: (DIVL x y)
|
// result: (Select0 (DIVL x y <&TupleType{config.Frontend().TypeInt32(), config.Frontend().TypeInt32()}>))
|
||||||
for {
|
for {
|
||||||
x := v.Args[0]
|
x := v.Args[0]
|
||||||
y := v.Args[1]
|
y := v.Args[1]
|
||||||
v.reset(OpAMD64DIVL)
|
v.reset(OpSelect0)
|
||||||
v.AddArg(x)
|
v0 := b.NewValue0(v.Line, OpAMD64DIVL, &TupleType{config.Frontend().TypeInt32(), config.Frontend().TypeInt32()})
|
||||||
v.AddArg(y)
|
v0.AddArg(x)
|
||||||
|
v0.AddArg(y)
|
||||||
|
v.AddArg(v0)
|
||||||
return true
|
return true
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -3335,13 +3341,15 @@ func rewriteValueAMD64_OpDiv32u(v *Value, config *Config) bool {
|
|||||||
_ = b
|
_ = b
|
||||||
// match: (Div32u x y)
|
// match: (Div32u x y)
|
||||||
// cond:
|
// cond:
|
||||||
// result: (DIVLU x y)
|
// result: (Select0 (DIVLU x y <&TupleType{config.Frontend().TypeUInt32(), config.Frontend().TypeUInt32()}>))
|
||||||
for {
|
for {
|
||||||
x := v.Args[0]
|
x := v.Args[0]
|
||||||
y := v.Args[1]
|
y := v.Args[1]
|
||||||
v.reset(OpAMD64DIVLU)
|
v.reset(OpSelect0)
|
||||||
v.AddArg(x)
|
v0 := b.NewValue0(v.Line, OpAMD64DIVLU, &TupleType{config.Frontend().TypeUInt32(), config.Frontend().TypeUInt32()})
|
||||||
v.AddArg(y)
|
v0.AddArg(x)
|
||||||
|
v0.AddArg(y)
|
||||||
|
v.AddArg(v0)
|
||||||
return true
|
return true
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -3350,13 +3358,15 @@ func rewriteValueAMD64_OpDiv64(v *Value, config *Config) bool {
|
|||||||
_ = b
|
_ = b
|
||||||
// match: (Div64 x y)
|
// match: (Div64 x y)
|
||||||
// cond:
|
// cond:
|
||||||
// result: (DIVQ x y)
|
// result: (Select0 (DIVQ x y <&TupleType{config.Frontend().TypeInt64(), config.Frontend().TypeInt64()}>))
|
||||||
for {
|
for {
|
||||||
x := v.Args[0]
|
x := v.Args[0]
|
||||||
y := v.Args[1]
|
y := v.Args[1]
|
||||||
v.reset(OpAMD64DIVQ)
|
v.reset(OpSelect0)
|
||||||
v.AddArg(x)
|
v0 := b.NewValue0(v.Line, OpAMD64DIVQ, &TupleType{config.Frontend().TypeInt64(), config.Frontend().TypeInt64()})
|
||||||
v.AddArg(y)
|
v0.AddArg(x)
|
||||||
|
v0.AddArg(y)
|
||||||
|
v.AddArg(v0)
|
||||||
return true
|
return true
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -3380,13 +3390,15 @@ func rewriteValueAMD64_OpDiv64u(v *Value, config *Config) bool {
|
|||||||
_ = b
|
_ = b
|
||||||
// match: (Div64u x y)
|
// match: (Div64u x y)
|
||||||
// cond:
|
// cond:
|
||||||
// result: (DIVQU x y)
|
// result: (Select0 (DIVQU x y <&TupleType{config.Frontend().TypeUInt64(), config.Frontend().TypeUInt64()}>))
|
||||||
for {
|
for {
|
||||||
x := v.Args[0]
|
x := v.Args[0]
|
||||||
y := v.Args[1]
|
y := v.Args[1]
|
||||||
v.reset(OpAMD64DIVQU)
|
v.reset(OpSelect0)
|
||||||
v.AddArg(x)
|
v0 := b.NewValue0(v.Line, OpAMD64DIVQU, &TupleType{config.Frontend().TypeUInt64(), config.Frontend().TypeUInt64()})
|
||||||
v.AddArg(y)
|
v0.AddArg(x)
|
||||||
|
v0.AddArg(y)
|
||||||
|
v.AddArg(v0)
|
||||||
return true
|
return true
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -3395,17 +3407,19 @@ func rewriteValueAMD64_OpDiv8(v *Value, config *Config) bool {
|
|||||||
_ = b
|
_ = b
|
||||||
// match: (Div8 x y)
|
// match: (Div8 x y)
|
||||||
// cond:
|
// cond:
|
||||||
// result: (DIVW (SignExt8to16 x) (SignExt8to16 y))
|
// result: (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y) <&TupleType{config.Frontend().TypeInt8(), config.Frontend().TypeInt8()}>))
|
||||||
for {
|
for {
|
||||||
x := v.Args[0]
|
x := v.Args[0]
|
||||||
y := v.Args[1]
|
y := v.Args[1]
|
||||||
v.reset(OpAMD64DIVW)
|
v.reset(OpSelect0)
|
||||||
v0 := b.NewValue0(v.Line, OpSignExt8to16, config.fe.TypeInt16())
|
v0 := b.NewValue0(v.Line, OpAMD64DIVW, &TupleType{config.Frontend().TypeInt8(), config.Frontend().TypeInt8()})
|
||||||
v0.AddArg(x)
|
|
||||||
v.AddArg(v0)
|
|
||||||
v1 := b.NewValue0(v.Line, OpSignExt8to16, config.fe.TypeInt16())
|
v1 := b.NewValue0(v.Line, OpSignExt8to16, config.fe.TypeInt16())
|
||||||
v1.AddArg(y)
|
v1.AddArg(x)
|
||||||
v.AddArg(v1)
|
v0.AddArg(v1)
|
||||||
|
v2 := b.NewValue0(v.Line, OpSignExt8to16, config.fe.TypeInt16())
|
||||||
|
v2.AddArg(y)
|
||||||
|
v0.AddArg(v2)
|
||||||
|
v.AddArg(v0)
|
||||||
return true
|
return true
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -3414,17 +3428,19 @@ func rewriteValueAMD64_OpDiv8u(v *Value, config *Config) bool {
|
|||||||
_ = b
|
_ = b
|
||||||
// match: (Div8u x y)
|
// match: (Div8u x y)
|
||||||
// cond:
|
// cond:
|
||||||
// result: (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y))
|
// result: (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y) <&TupleType{config.Frontend().TypeUInt8(), config.Frontend().TypeUInt8()}>))
|
||||||
for {
|
for {
|
||||||
x := v.Args[0]
|
x := v.Args[0]
|
||||||
y := v.Args[1]
|
y := v.Args[1]
|
||||||
v.reset(OpAMD64DIVWU)
|
v.reset(OpSelect0)
|
||||||
v0 := b.NewValue0(v.Line, OpZeroExt8to16, config.fe.TypeUInt16())
|
v0 := b.NewValue0(v.Line, OpAMD64DIVWU, &TupleType{config.Frontend().TypeUInt8(), config.Frontend().TypeUInt8()})
|
||||||
v0.AddArg(x)
|
|
||||||
v.AddArg(v0)
|
|
||||||
v1 := b.NewValue0(v.Line, OpZeroExt8to16, config.fe.TypeUInt16())
|
v1 := b.NewValue0(v.Line, OpZeroExt8to16, config.fe.TypeUInt16())
|
||||||
v1.AddArg(y)
|
v1.AddArg(x)
|
||||||
v.AddArg(v1)
|
v0.AddArg(v1)
|
||||||
|
v2 := b.NewValue0(v.Line, OpZeroExt8to16, config.fe.TypeUInt16())
|
||||||
|
v2.AddArg(y)
|
||||||
|
v0.AddArg(v2)
|
||||||
|
v.AddArg(v0)
|
||||||
return true
|
return true
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -11892,13 +11908,15 @@ func rewriteValueAMD64_OpMod16(v *Value, config *Config) bool {
|
|||||||
_ = b
|
_ = b
|
||||||
// match: (Mod16 x y)
|
// match: (Mod16 x y)
|
||||||
// cond:
|
// cond:
|
||||||
// result: (MODW x y)
|
// result: (Select1 (DIVW x y <&TupleType{config.Frontend().TypeInt16(), config.Frontend().TypeInt16()}>))
|
||||||
for {
|
for {
|
||||||
x := v.Args[0]
|
x := v.Args[0]
|
||||||
y := v.Args[1]
|
y := v.Args[1]
|
||||||
v.reset(OpAMD64MODW)
|
v.reset(OpSelect1)
|
||||||
v.AddArg(x)
|
v0 := b.NewValue0(v.Line, OpAMD64DIVW, &TupleType{config.Frontend().TypeInt16(), config.Frontend().TypeInt16()})
|
||||||
v.AddArg(y)
|
v0.AddArg(x)
|
||||||
|
v0.AddArg(y)
|
||||||
|
v.AddArg(v0)
|
||||||
return true
|
return true
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -11907,13 +11925,15 @@ func rewriteValueAMD64_OpMod16u(v *Value, config *Config) bool {
|
|||||||
_ = b
|
_ = b
|
||||||
// match: (Mod16u x y)
|
// match: (Mod16u x y)
|
||||||
// cond:
|
// cond:
|
||||||
// result: (MODWU x y)
|
// result: (Select1 (DIVWU x y <&TupleType{config.Frontend().TypeUInt16(), config.Frontend().TypeUInt16()}>))
|
||||||
for {
|
for {
|
||||||
x := v.Args[0]
|
x := v.Args[0]
|
||||||
y := v.Args[1]
|
y := v.Args[1]
|
||||||
v.reset(OpAMD64MODWU)
|
v.reset(OpSelect1)
|
||||||
v.AddArg(x)
|
v0 := b.NewValue0(v.Line, OpAMD64DIVWU, &TupleType{config.Frontend().TypeUInt16(), config.Frontend().TypeUInt16()})
|
||||||
v.AddArg(y)
|
v0.AddArg(x)
|
||||||
|
v0.AddArg(y)
|
||||||
|
v.AddArg(v0)
|
||||||
return true
|
return true
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -11922,13 +11942,15 @@ func rewriteValueAMD64_OpMod32(v *Value, config *Config) bool {
|
|||||||
_ = b
|
_ = b
|
||||||
// match: (Mod32 x y)
|
// match: (Mod32 x y)
|
||||||
// cond:
|
// cond:
|
||||||
// result: (MODL x y)
|
// result: (Select1 (DIVL x y <&TupleType{config.Frontend().TypeInt32(), config.Frontend().TypeInt32()}>))
|
||||||
for {
|
for {
|
||||||
x := v.Args[0]
|
x := v.Args[0]
|
||||||
y := v.Args[1]
|
y := v.Args[1]
|
||||||
v.reset(OpAMD64MODL)
|
v.reset(OpSelect1)
|
||||||
v.AddArg(x)
|
v0 := b.NewValue0(v.Line, OpAMD64DIVL, &TupleType{config.Frontend().TypeInt32(), config.Frontend().TypeInt32()})
|
||||||
v.AddArg(y)
|
v0.AddArg(x)
|
||||||
|
v0.AddArg(y)
|
||||||
|
v.AddArg(v0)
|
||||||
return true
|
return true
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -11937,13 +11959,15 @@ func rewriteValueAMD64_OpMod32u(v *Value, config *Config) bool {
|
|||||||
_ = b
|
_ = b
|
||||||
// match: (Mod32u x y)
|
// match: (Mod32u x y)
|
||||||
// cond:
|
// cond:
|
||||||
// result: (MODLU x y)
|
// result: (Select1 (DIVLU x y <&TupleType{config.Frontend().TypeUInt32(), config.Frontend().TypeUInt32()}>))
|
||||||
for {
|
for {
|
||||||
x := v.Args[0]
|
x := v.Args[0]
|
||||||
y := v.Args[1]
|
y := v.Args[1]
|
||||||
v.reset(OpAMD64MODLU)
|
v.reset(OpSelect1)
|
||||||
v.AddArg(x)
|
v0 := b.NewValue0(v.Line, OpAMD64DIVLU, &TupleType{config.Frontend().TypeUInt32(), config.Frontend().TypeUInt32()})
|
||||||
v.AddArg(y)
|
v0.AddArg(x)
|
||||||
|
v0.AddArg(y)
|
||||||
|
v.AddArg(v0)
|
||||||
return true
|
return true
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -11952,13 +11976,15 @@ func rewriteValueAMD64_OpMod64(v *Value, config *Config) bool {
|
|||||||
_ = b
|
_ = b
|
||||||
// match: (Mod64 x y)
|
// match: (Mod64 x y)
|
||||||
// cond:
|
// cond:
|
||||||
// result: (MODQ x y)
|
// result: (Select1 (DIVQ x y <&TupleType{config.Frontend().TypeInt64(), config.Frontend().TypeInt64()}>))
|
||||||
for {
|
for {
|
||||||
x := v.Args[0]
|
x := v.Args[0]
|
||||||
y := v.Args[1]
|
y := v.Args[1]
|
||||||
v.reset(OpAMD64MODQ)
|
v.reset(OpSelect1)
|
||||||
v.AddArg(x)
|
v0 := b.NewValue0(v.Line, OpAMD64DIVQ, &TupleType{config.Frontend().TypeInt64(), config.Frontend().TypeInt64()})
|
||||||
v.AddArg(y)
|
v0.AddArg(x)
|
||||||
|
v0.AddArg(y)
|
||||||
|
v.AddArg(v0)
|
||||||
return true
|
return true
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -11967,13 +11993,15 @@ func rewriteValueAMD64_OpMod64u(v *Value, config *Config) bool {
|
|||||||
_ = b
|
_ = b
|
||||||
// match: (Mod64u x y)
|
// match: (Mod64u x y)
|
||||||
// cond:
|
// cond:
|
||||||
// result: (MODQU x y)
|
// result: (Select1 (DIVQU x y <&TupleType{config.Frontend().TypeUInt64(), config.Frontend().TypeUInt64()}>))
|
||||||
for {
|
for {
|
||||||
x := v.Args[0]
|
x := v.Args[0]
|
||||||
y := v.Args[1]
|
y := v.Args[1]
|
||||||
v.reset(OpAMD64MODQU)
|
v.reset(OpSelect1)
|
||||||
v.AddArg(x)
|
v0 := b.NewValue0(v.Line, OpAMD64DIVQU, &TupleType{config.Frontend().TypeUInt64(), config.Frontend().TypeUInt64()})
|
||||||
v.AddArg(y)
|
v0.AddArg(x)
|
||||||
|
v0.AddArg(y)
|
||||||
|
v.AddArg(v0)
|
||||||
return true
|
return true
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -11982,17 +12010,19 @@ func rewriteValueAMD64_OpMod8(v *Value, config *Config) bool {
|
|||||||
_ = b
|
_ = b
|
||||||
// match: (Mod8 x y)
|
// match: (Mod8 x y)
|
||||||
// cond:
|
// cond:
|
||||||
// result: (MODW (SignExt8to16 x) (SignExt8to16 y))
|
// result: (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y) <&TupleType{config.Frontend().TypeInt8(), config.Frontend().TypeInt8()}>))
|
||||||
for {
|
for {
|
||||||
x := v.Args[0]
|
x := v.Args[0]
|
||||||
y := v.Args[1]
|
y := v.Args[1]
|
||||||
v.reset(OpAMD64MODW)
|
v.reset(OpSelect1)
|
||||||
v0 := b.NewValue0(v.Line, OpSignExt8to16, config.fe.TypeInt16())
|
v0 := b.NewValue0(v.Line, OpAMD64DIVW, &TupleType{config.Frontend().TypeInt8(), config.Frontend().TypeInt8()})
|
||||||
v0.AddArg(x)
|
|
||||||
v.AddArg(v0)
|
|
||||||
v1 := b.NewValue0(v.Line, OpSignExt8to16, config.fe.TypeInt16())
|
v1 := b.NewValue0(v.Line, OpSignExt8to16, config.fe.TypeInt16())
|
||||||
v1.AddArg(y)
|
v1.AddArg(x)
|
||||||
v.AddArg(v1)
|
v0.AddArg(v1)
|
||||||
|
v2 := b.NewValue0(v.Line, OpSignExt8to16, config.fe.TypeInt16())
|
||||||
|
v2.AddArg(y)
|
||||||
|
v0.AddArg(v2)
|
||||||
|
v.AddArg(v0)
|
||||||
return true
|
return true
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -12001,17 +12031,19 @@ func rewriteValueAMD64_OpMod8u(v *Value, config *Config) bool {
|
|||||||
_ = b
|
_ = b
|
||||||
// match: (Mod8u x y)
|
// match: (Mod8u x y)
|
||||||
// cond:
|
// cond:
|
||||||
// result: (MODWU (ZeroExt8to16 x) (ZeroExt8to16 y))
|
// result: (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y) <&TupleType{config.Frontend().TypeUInt8(), config.Frontend().TypeUInt8()}>))
|
||||||
for {
|
for {
|
||||||
x := v.Args[0]
|
x := v.Args[0]
|
||||||
y := v.Args[1]
|
y := v.Args[1]
|
||||||
v.reset(OpAMD64MODWU)
|
v.reset(OpSelect1)
|
||||||
v0 := b.NewValue0(v.Line, OpZeroExt8to16, config.fe.TypeUInt16())
|
v0 := b.NewValue0(v.Line, OpAMD64DIVWU, &TupleType{config.Frontend().TypeUInt8(), config.Frontend().TypeUInt8()})
|
||||||
v0.AddArg(x)
|
|
||||||
v.AddArg(v0)
|
|
||||||
v1 := b.NewValue0(v.Line, OpZeroExt8to16, config.fe.TypeUInt16())
|
v1 := b.NewValue0(v.Line, OpZeroExt8to16, config.fe.TypeUInt16())
|
||||||
v1.AddArg(y)
|
v1.AddArg(x)
|
||||||
v.AddArg(v1)
|
v0.AddArg(v1)
|
||||||
|
v2 := b.NewValue0(v.Line, OpZeroExt8to16, config.fe.TypeUInt16())
|
||||||
|
v2.AddArg(y)
|
||||||
|
v0.AddArg(v2)
|
||||||
|
v.AddArg(v0)
|
||||||
return true
|
return true
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
Loading…
Reference in New Issue
Block a user