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cmd/compile: missing float indexed loads/stores on amd64
Update #16141 Change-Id: I7d32c5cdc197d86491a67ea579fa16cb3d675b51 Reviewed-on: https://go-review.googlesource.com/28273 Run-TryBot: Keith Randall <khr@golang.org> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: David Chase <drchase@google.com>
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@ -938,9 +938,13 @@
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(MOVWloadidx1 [c] {sym} ptr (SHLQconst [1] idx) mem) -> (MOVWloadidx2 [c] {sym} ptr idx mem)
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(MOVLloadidx1 [c] {sym} ptr (SHLQconst [2] idx) mem) -> (MOVLloadidx4 [c] {sym} ptr idx mem)
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(MOVQloadidx1 [c] {sym} ptr (SHLQconst [3] idx) mem) -> (MOVQloadidx8 [c] {sym} ptr idx mem)
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(MOVSSloadidx1 [c] {sym} ptr (SHLQconst [2] idx) mem) -> (MOVSSloadidx4 [c] {sym} ptr idx mem)
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(MOVSDloadidx1 [c] {sym} ptr (SHLQconst [3] idx) mem) -> (MOVSDloadidx8 [c] {sym} ptr idx mem)
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(MOVWstoreidx1 [c] {sym} ptr (SHLQconst [1] idx) val mem) -> (MOVWstoreidx2 [c] {sym} ptr idx val mem)
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(MOVLstoreidx1 [c] {sym} ptr (SHLQconst [2] idx) val mem) -> (MOVLstoreidx4 [c] {sym} ptr idx val mem)
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(MOVQstoreidx1 [c] {sym} ptr (SHLQconst [3] idx) val mem) -> (MOVQstoreidx8 [c] {sym} ptr idx val mem)
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(MOVSSstoreidx1 [c] {sym} ptr (SHLQconst [2] idx) val mem) -> (MOVSSstoreidx4 [c] {sym} ptr idx val mem)
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(MOVSDstoreidx1 [c] {sym} ptr (SHLQconst [3] idx) val mem) -> (MOVSDstoreidx8 [c] {sym} ptr idx val mem)
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(MOVWstoreconstidx1 [c] {sym} ptr (SHLQconst [1] idx) mem) -> (MOVWstoreconstidx2 [c] {sym} ptr idx mem)
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(MOVLstoreconstidx1 [c] {sym} ptr (SHLQconst [2] idx) mem) -> (MOVLstoreconstidx4 [c] {sym} ptr idx mem)
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(MOVQstoreconstidx1 [c] {sym} ptr (SHLQconst [3] idx) mem) -> (MOVQstoreconstidx8 [c] {sym} ptr idx mem)
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@ -7189,6 +7189,30 @@ func rewriteValueAMD64_OpAMD64MOVSDload(v *Value, config *Config) bool {
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func rewriteValueAMD64_OpAMD64MOVSDloadidx1(v *Value, config *Config) bool {
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b := v.Block
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_ = b
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// match: (MOVSDloadidx1 [c] {sym} ptr (SHLQconst [3] idx) mem)
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// cond:
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// result: (MOVSDloadidx8 [c] {sym} ptr idx mem)
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for {
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c := v.AuxInt
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sym := v.Aux
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ptr := v.Args[0]
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v_1 := v.Args[1]
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if v_1.Op != OpAMD64SHLQconst {
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break
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}
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if v_1.AuxInt != 3 {
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break
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}
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idx := v_1.Args[0]
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mem := v.Args[2]
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v.reset(OpAMD64MOVSDloadidx8)
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v.AuxInt = c
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v.Aux = sym
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v.AddArg(ptr)
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v.AddArg(idx)
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v.AddArg(mem)
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return true
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}
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// match: (MOVSDloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem)
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// cond:
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// result: (MOVSDloadidx1 [c+d] {sym} ptr idx mem)
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@ -7425,6 +7449,32 @@ func rewriteValueAMD64_OpAMD64MOVSDstore(v *Value, config *Config) bool {
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func rewriteValueAMD64_OpAMD64MOVSDstoreidx1(v *Value, config *Config) bool {
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b := v.Block
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_ = b
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// match: (MOVSDstoreidx1 [c] {sym} ptr (SHLQconst [3] idx) val mem)
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// cond:
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// result: (MOVSDstoreidx8 [c] {sym} ptr idx val mem)
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for {
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c := v.AuxInt
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sym := v.Aux
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ptr := v.Args[0]
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v_1 := v.Args[1]
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if v_1.Op != OpAMD64SHLQconst {
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break
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}
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if v_1.AuxInt != 3 {
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break
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}
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idx := v_1.Args[0]
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val := v.Args[2]
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mem := v.Args[3]
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v.reset(OpAMD64MOVSDstoreidx8)
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v.AuxInt = c
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v.Aux = sym
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v.AddArg(ptr)
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v.AddArg(idx)
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v.AddArg(val)
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v.AddArg(mem)
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return true
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}
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// match: (MOVSDstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem)
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// cond:
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// result: (MOVSDstoreidx1 [c+d] {sym} ptr idx val mem)
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@ -7659,6 +7709,30 @@ func rewriteValueAMD64_OpAMD64MOVSSload(v *Value, config *Config) bool {
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func rewriteValueAMD64_OpAMD64MOVSSloadidx1(v *Value, config *Config) bool {
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b := v.Block
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_ = b
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// match: (MOVSSloadidx1 [c] {sym} ptr (SHLQconst [2] idx) mem)
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// cond:
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// result: (MOVSSloadidx4 [c] {sym} ptr idx mem)
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for {
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c := v.AuxInt
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sym := v.Aux
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ptr := v.Args[0]
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v_1 := v.Args[1]
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if v_1.Op != OpAMD64SHLQconst {
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break
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}
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if v_1.AuxInt != 2 {
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break
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}
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idx := v_1.Args[0]
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mem := v.Args[2]
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v.reset(OpAMD64MOVSSloadidx4)
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v.AuxInt = c
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v.Aux = sym
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v.AddArg(ptr)
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v.AddArg(idx)
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v.AddArg(mem)
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return true
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}
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// match: (MOVSSloadidx1 [c] {sym} (ADDQconst [d] ptr) idx mem)
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// cond:
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// result: (MOVSSloadidx1 [c+d] {sym} ptr idx mem)
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@ -7895,6 +7969,32 @@ func rewriteValueAMD64_OpAMD64MOVSSstore(v *Value, config *Config) bool {
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func rewriteValueAMD64_OpAMD64MOVSSstoreidx1(v *Value, config *Config) bool {
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b := v.Block
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_ = b
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// match: (MOVSSstoreidx1 [c] {sym} ptr (SHLQconst [2] idx) val mem)
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// cond:
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// result: (MOVSSstoreidx4 [c] {sym} ptr idx val mem)
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for {
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c := v.AuxInt
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sym := v.Aux
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ptr := v.Args[0]
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v_1 := v.Args[1]
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if v_1.Op != OpAMD64SHLQconst {
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break
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}
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if v_1.AuxInt != 2 {
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break
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}
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idx := v_1.Args[0]
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val := v.Args[2]
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mem := v.Args[3]
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v.reset(OpAMD64MOVSSstoreidx4)
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v.AuxInt = c
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v.Aux = sym
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v.AddArg(ptr)
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v.AddArg(idx)
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v.AddArg(val)
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v.AddArg(mem)
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return true
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}
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// match: (MOVSSstoreidx1 [c] {sym} (ADDQconst [d] ptr) idx val mem)
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// cond:
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// result: (MOVSSstoreidx1 [c+d] {sym} ptr idx val mem)
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