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cmd/asm, cmd/internal/obj/s390x, math: add "test under mask" instructions
Adds the following s390x test under mask (immediate) instructions: TMHH TMHL TMLH TMLL These are useful for testing bits and are already used in the math package. Change-Id: Idffb3f83b238dba76ac1e42ac6b0bf7f1d11bea2 Reviewed-on: https://go-review.googlesource.com/41092 Run-TryBot: Michael Munday <mike.munday@ibm.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Cherry Zhang <cherryyz@google.com>
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5
src/cmd/asm/internal/asm/testdata/s390x.s
vendored
5
src/cmd/asm/internal/asm/testdata/s390x.s
vendored
@ -213,6 +213,11 @@ TEXT main·foo(SB),DUPOK|NOSPLIT,$16-0 // TEXT main.foo(SB), DUPOK|NOSPLIT, $16-
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CMPWU R1, R2 // 1512
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CMPWU R3, $4294967295 // c23fffffffff
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TMHH R1, $65535 // a712ffff
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TMHL R2, $1 // a7230001
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TMLH R3, $0 // a7300000
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TMLL R4, $32768 // a7418000
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BNE 0(PC) // a7740000
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BEQ 0(PC) // a7840000
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BLT 0(PC) // a7440000
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@ -327,6 +327,12 @@ const (
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ACMPW
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ACMPWU
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// test under mask
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ATMHH
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ATMHL
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ATMLH
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ATMLL
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// compare and swap
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ACS
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ACSG
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@ -112,6 +112,10 @@ var Anames = []string{
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"CMPU",
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"CMPW",
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"CMPWU",
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"TMHH",
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"TMHL",
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"TMLH",
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"TMLL",
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"CS",
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"CSG",
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"SYNC",
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@ -252,6 +252,9 @@ var optab = []Optab{
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Optab{AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 0},
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Optab{AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 0},
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// test under mask
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Optab{ATMHH, C_REG, C_NONE, C_NONE, C_ANDCON, 91, 0},
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// 32-bit access registers
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Optab{AMOVW, C_AREG, C_NONE, C_NONE, C_REG, 68, 0},
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Optab{AMOVWZ, C_AREG, C_NONE, C_NONE, C_REG, 68, 0},
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@ -951,6 +954,10 @@ func buildop(ctxt *obj.Link) {
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opset(ACMPW, r)
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case ACMPU:
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opset(ACMPWU, r)
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case ATMHH:
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opset(ATMHL, r)
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opset(ATMLH, r)
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opset(ATMLL, r)
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case ACEFBRA:
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opset(ACDFBRA, r)
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opset(ACEGBRA, r)
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@ -3704,6 +3711,20 @@ func (c *ctxtz) asmout(p *obj.Prog, asm *[]byte) {
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zRIE(_c, opcode, uint32(p.From.Reg), mask, uint32(v), 0, 0, 0, uint32(c.regoff(p.GetFrom3())), asm)
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}
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case 91: // test under mask (immediate)
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var opcode uint32
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switch p.As {
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case ATMHH:
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opcode = op_TMHH
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case ATMHL:
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opcode = op_TMHL
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case ATMLH:
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opcode = op_TMLH
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case ATMLL:
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opcode = op_TMLL
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}
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zRI(opcode, uint32(p.From.Reg), uint32(c.vregoff(&p.To)), asm)
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case 93: // GOT lookup
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v := c.vregoff(&p.To)
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if v != 0 {
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@ -110,7 +110,7 @@ L2:
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WFMDB V1, V1, V2
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LGDR F3, R1
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MOVD $sincosxlim<>+0(SB), R2
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WORD $0xA7110001 //tmll %r1,1
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TMLL R1, $1
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BEQ L6
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FMOVD 0(R2), F0
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WFCHDBS V0, V5, V0
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@ -134,7 +134,7 @@ L2:
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WFMADB V2, V0, V3, V0
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FMOVD 0(R2), F6
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WFMADB V1, V4, V6, V4
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WORD $0xA7110002 //tmll %r1,2
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TMLL R1, $2
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WFMADB V2, V0, V4, V0
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MOVD $sincosc0<>+0(SB), R1
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FMOVD 0(R1), F2
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@ -170,7 +170,7 @@ L6:
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FNEG F6, F4
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WFMADB V2, V0, V3, V2
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WFMDB V4, V1, V0
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WORD $0xA7110002 //tmll %r1,2
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TMLL R1, $2
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WFMSDB V0, V2, V6, V0
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BNE L15
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FMOVD F0, ret+8(FP)
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@ -261,7 +261,7 @@ L21:
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FMOVD 0(R2), F5
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WFMDB V2, V2, V6
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MOVD $sincosxlim<>+0(SB), R2
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WORD $0xA7110001 //tmll %r1,1
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TMLL R1, $1
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BNE L25
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FMOVD 0(R2), F0
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WFCHDBS V0, V1, V0
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@ -285,7 +285,7 @@ L21:
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WFMADB V6, V0, V3, V0
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FMOVD 0(R2), F1
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WFMADB V2, V4, V1, V4
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WORD $0xA7110002 //tmll %r1,2
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TMLL R1, $2
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WFMADB V6, V0, V4, V0
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MOVD $sincosc0<>+0(SB), R1
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FMOVD 0(R1), F4
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@ -320,7 +320,7 @@ L25:
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FMADD F3, F2, F1
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FMUL F0, F2
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WFMADB V6, V4, V1, V6
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WORD $0xA7110002 //tmll %r1,2
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TMLL R1, $2
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FMADD F6, F2, F0
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BNE L34
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FMOVD F0, ret+8(FP)
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