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https://github.com/golang/go
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[dev.ssa] cmd/compile/internal/ssa: implement multiplies
Use width-and-signed-specific multiply opcodes. Implement OMUL. A few other cleanups. Fixes #11467 Change-Id: Ib0fe80a1a9b7208dbb8a2b6b652a478847f5d244 Reviewed-on: https://go-review.googlesource.com/12540 Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com>
This commit is contained in:
Keith Randall
parent
d5297f7261
commit
be1eb57a8b
@ -686,6 +686,15 @@ var opToSSA = map[opAndType]ssa.Op{
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opAndType{OMINUS, TINT64}: ssa.OpNeg64,
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opAndType{OMINUS, TUINT64}: ssa.OpNeg64U,
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opAndType{OMUL, TINT8}: ssa.OpMul8,
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opAndType{OMUL, TUINT8}: ssa.OpMul8U,
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opAndType{OMUL, TINT16}: ssa.OpMul16,
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opAndType{OMUL, TUINT16}: ssa.OpMul16U,
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opAndType{OMUL, TINT32}: ssa.OpMul32,
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opAndType{OMUL, TUINT32}: ssa.OpMul32U,
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opAndType{OMUL, TINT64}: ssa.OpMul64,
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opAndType{OMUL, TUINT64}: ssa.OpMul64U,
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opAndType{OLSH, TINT8}: ssa.OpLsh8,
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opAndType{OLSH, TUINT8}: ssa.OpLsh8,
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opAndType{OLSH, TINT16}: ssa.OpLsh16,
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@ -825,7 +834,7 @@ func (s *state) expr(n *Node) *ssa.Value {
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a := s.expr(n.Left)
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b := s.expr(n.Right)
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return s.newValue2(s.ssaOp(n.Op, n.Left.Type), ssa.TypeBool, a, b)
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case OADD, OSUB, OLSH, ORSH:
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case OADD, OSUB, OMUL, OLSH, ORSH:
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a := s.expr(n.Left)
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b := s.expr(n.Right)
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return s.newValue2(s.ssaOp(n.Op, n.Type), a.Type, a, b)
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@ -1387,7 +1396,7 @@ func genValue(v *ssa.Value) {
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p.From.Index = regnum(v.Args[1])
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p.To.Type = obj.TYPE_REG
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p.To.Reg = regnum(v)
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case ssa.OpAMD64ADDB, ssa.OpAMD64ANDQ:
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case ssa.OpAMD64ADDB, ssa.OpAMD64ANDQ, ssa.OpAMD64MULQ, ssa.OpAMD64MULL, ssa.OpAMD64MULW:
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r := regnum(v)
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x := regnum(v.Args[0])
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y := regnum(v.Args[1])
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@ -1417,18 +1426,25 @@ func genValue(v *ssa.Value) {
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p.To.Type = obj.TYPE_REG
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p.To.Reg = regnum(v)
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case ssa.OpAMD64MULQconst:
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v.Unimplementedf("IMULQ doasm")
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return
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// TODO: this isn't right. doasm fails on it. I don't think obj
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// has ever been taught to compile imul $c, r1, r2.
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r := regnum(v)
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x := regnum(v.Args[0])
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if r != x {
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p := Prog(x86.AMOVQ)
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p.From.Type = obj.TYPE_REG
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p.From.Reg = x
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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}
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p := Prog(x86.AIMULQ)
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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p.From3 = new(obj.Addr)
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p.From3.Type = obj.TYPE_REG
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p.From3.Reg = regnum(v.Args[0])
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p.To.Type = obj.TYPE_REG
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p.To.Reg = regnum(v)
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p.To.Reg = r
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// TODO: Teach doasm to compile the three-address multiply imul $c, r1, r2
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// instead of using the MOVQ above.
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//p.From3 = new(obj.Addr)
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//p.From3.Type = obj.TYPE_REG
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//p.From3.Reg = regnum(v.Args[0])
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case ssa.OpAMD64SUBQconst:
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// This code compensates for the fact that the register allocator
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// doesn't understand 2-address instructions yet. TODO: fix that.
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@ -41,11 +41,25 @@
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(Neg8U x) -> (NEGB x)
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(Neg8 x) -> (MOVBQSX (NEGB <v.Type> x))
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(Mul <t> x y) && is64BitInt(t) -> (MULQ x y)
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(Mul64 x y) -> (MULQ x y)
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(Mul64U x y) -> (MULQ x y)
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(MulPtr x y) -> (MULQ x y)
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(Mul32 x y) -> (MOVLQSX (MULL <v.Type> x y))
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(Mul32U x y) -> (MULL x y)
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(Mul16 x y) -> (MOVWQSX (MULW <v.Type> x y))
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(Mul16U x y) -> (MULW x y)
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// Note: we use 16-bit multiply instructions for 8-bit multiplies because
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// the 16-bit multiply instructions are more forgiving (they operate on
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// any register instead of just AX/DX).
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(Mul8 x y) -> (MOVBQSX (MULW <TypeInt16> x y))
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(Mul8U x y) -> (MOVBQZX (MULW <TypeUInt16> x y))
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(MOVLstore ptr (MOVLQSX x) mem) -> (MOVLstore ptr x mem)
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(MOVWstore ptr (MOVWQSX x) mem) -> (MOVWstore ptr x mem)
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(MOVBstore ptr (MOVBQSX x) mem) -> (MOVBstore ptr x mem)
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(MOVLstore ptr (MOVLQZX x) mem) -> (MOVLstore ptr x mem)
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(MOVWstore ptr (MOVWQZX x) mem) -> (MOVWstore ptr x mem)
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(MOVBstore ptr (MOVBQZX x) mem) -> (MOVBstore ptr x mem)
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(Convert <t> x) && t.IsInteger() && x.Type.IsInteger() -> (Copy x)
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(ConvNop <t> x) && t == x.Type -> (Copy x)
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@ -126,9 +126,12 @@ func init() {
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{name: "CMOVQCC", reg: cmov}, // carry clear
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{name: "MOVLQSX", reg: gp11, asm: "MOVLQSX"}, // extend arg0 from int32 to int64
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{name: "MOVWQSX", reg: gp11, asm: "MOVWQSX"}, // extend arg0 from int16 to int64
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{name: "MOVBQSX", reg: gp11, asm: "MOVBQSX"}, // extend arg0 from int8 to int64
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{name: "MOVBQSX", reg: gp11, asm: "MOVBQSX"}, // sign extend arg0 from int8 to int64
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{name: "MOVBQZX", reg: gp11, asm: "MOVBQZX"}, // zero extend arg0 from int8 to int64
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{name: "MOVWQSX", reg: gp11, asm: "MOVWQSX"}, // sign extend arg0 from int16 to int64
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{name: "MOVWQZX", reg: gp11, asm: "MOVWQZX"}, // zero extend arg0 from int16 to int64
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{name: "MOVLQSX", reg: gp11, asm: "MOVLQSX"}, // sign extend arg0 from int32 to int64
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{name: "MOVLQZX", reg: gp11, asm: "MOVLQZX"}, // zero extend arg0 from int32 to int64
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{name: "MOVQconst", reg: gp01}, // auxint
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{name: "LEAQ", reg: gp11sb}, // arg0 + auxint + offset encoded in aux
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@ -182,6 +185,9 @@ func init() {
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{name: "NEGW", reg: gp11, asm: "NEGW"}, // -arg0
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{name: "NEGB", reg: gp11, asm: "NEGB"}, // -arg0
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{name: "MULL", reg: gp21, asm: "IMULL"}, // arg0*arg1
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{name: "MULW", reg: gp21, asm: "IMULW"}, // arg0*arg1
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// (InvertFlags (CMPQ a b)) == (CMPQ b a)
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// So if we want (SETL (CMPQ a b)) but we can't do that because a is a constant,
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// then we do (SETL (InvertFlags (CMPQ b a))) instead.
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@ -22,7 +22,10 @@
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// constant folding
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(Add64 (Const [c]) (Const [d])) -> (Const [c+d])
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(Add64U (Const [c]) (Const [d])) -> (Const [c+d])
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(Mul <t> (Const [c]) (Const [d])) && is64BitInt(t) -> (Const [c*d])
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(AddPtr (Const [c]) (Const [d])) -> (Const [c+d])
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(Mul64 (Const [c]) (Const [d])) -> (Const [c*d])
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(Mul64U (Const [c]) (Const [d])) -> (Const [c*d])
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(MulPtr (Const [c]) (Const [d])) -> (Const [c*d])
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(IsInBounds (Const [c]) (Const [d])) -> (Const {inBounds(c,d)})
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// tear apart slices
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@ -34,7 +37,7 @@
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// indexing operations
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// Note: bounds check has already been done
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(ArrayIndex (Load ptr mem) idx) -> (Load (PtrIndex <v.Type.PtrTo()> ptr idx) mem)
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(PtrIndex <t> ptr idx) -> (AddPtr ptr (Mul <config.Uintptr> idx (Const <config.Uintptr> [t.Elem().Size()])))
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(PtrIndex <t> ptr idx) -> (AddPtr ptr (MulPtr <config.Uintptr> idx (Const <config.Uintptr> [t.Elem().Size()])))
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(StructSelect [idx] (Load ptr mem)) -> (Load (OffPtr <v.Type.PtrTo()> [idx] ptr) mem)
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// big-object moves
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@ -29,7 +29,15 @@ var genericOps = []opData{
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{name: "Sub64U"},
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// TODO: Sub32F, Sub64F, Sub64C, Sub128C
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{name: "Mul"}, // arg0 * arg1
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{name: "Mul8"}, // arg0 * arg1
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{name: "Mul16"},
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{name: "Mul32"},
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{name: "Mul64"},
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{name: "Mul8U"},
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{name: "Mul16U"},
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{name: "Mul32U"},
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{name: "Mul64U"},
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{name: "MulPtr"}, // MulPtr is used for address calculations
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{name: "Lsh8"}, // arg0 << arg1
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{name: "Lsh16"},
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@ -75,9 +75,12 @@ const (
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OpAMD64SETGE
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OpAMD64SETB
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OpAMD64CMOVQCC
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OpAMD64MOVLQSX
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OpAMD64MOVWQSX
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OpAMD64MOVBQSX
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OpAMD64MOVBQZX
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OpAMD64MOVWQSX
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OpAMD64MOVWQZX
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OpAMD64MOVLQSX
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OpAMD64MOVLQZX
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OpAMD64MOVQconst
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OpAMD64LEAQ
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OpAMD64LEAQ1
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@ -117,6 +120,8 @@ const (
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OpAMD64NEGL
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OpAMD64NEGW
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OpAMD64NEGB
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OpAMD64MULL
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OpAMD64MULW
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OpAMD64InvertFlags
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OpAdd8
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@ -136,7 +141,15 @@ const (
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OpSub16U
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OpSub32U
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OpSub64U
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OpMul
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OpMul8
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OpMul16
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OpMul32
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OpMul64
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OpMul8U
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OpMul16U
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OpMul32U
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OpMul64U
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OpMulPtr
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OpLsh8
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OpLsh16
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OpLsh32
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@ -533,8 +546,20 @@ var opcodeTable = [...]opInfo{
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},
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},
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{
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name: "MOVLQSX",
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asm: x86.AMOVLQSX,
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name: "MOVBQSX",
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asm: x86.AMOVBQSX,
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reg: regInfo{
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inputs: []regMask{
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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},
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{
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name: "MOVBQZX",
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asm: x86.AMOVBQZX,
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reg: regInfo{
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inputs: []regMask{
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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@ -557,8 +582,32 @@ var opcodeTable = [...]opInfo{
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},
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},
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{
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name: "MOVBQSX",
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asm: x86.AMOVBQSX,
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name: "MOVWQZX",
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asm: x86.AMOVWQZX,
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reg: regInfo{
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inputs: []regMask{
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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},
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{
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name: "MOVLQSX",
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asm: x86.AMOVLQSX,
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reg: regInfo{
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inputs: []regMask{
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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},
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{
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name: "MOVLQZX",
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asm: x86.AMOVLQZX,
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reg: regInfo{
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inputs: []regMask{
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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@ -1006,6 +1055,32 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "MULL",
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asm: x86.AIMULL,
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reg: regInfo{
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inputs: []regMask{
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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},
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{
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name: "MULW",
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asm: x86.AIMULW,
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reg: regInfo{
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inputs: []regMask{
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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},
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{
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name: "InvertFlags",
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reg: regInfo{},
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@ -1080,7 +1155,39 @@ var opcodeTable = [...]opInfo{
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generic: true,
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},
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{
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name: "Mul",
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name: "Mul8",
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generic: true,
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},
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{
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name: "Mul16",
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generic: true,
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},
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{
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name: "Mul32",
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generic: true,
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},
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{
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name: "Mul64",
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generic: true,
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},
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{
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name: "Mul8U",
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generic: true,
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},
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{
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name: "Mul16U",
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generic: true,
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},
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{
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name: "Mul32U",
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generic: true,
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},
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{
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name: "Mul64U",
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generic: true,
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},
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{
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name: "MulPtr",
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generic: true,
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},
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{
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@ -893,6 +893,28 @@ func rewriteValueAMD64(v *Value, config *Config) bool {
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goto endc356ef104095b9217b36b594f85171c6
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endc356ef104095b9217b36b594f85171c6:
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;
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// match: (MOVBstore ptr (MOVBQZX x) mem)
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// cond:
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// result: (MOVBstore ptr x mem)
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{
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ptr := v.Args[0]
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if v.Args[1].Op != OpAMD64MOVBQZX {
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goto end25841a70cce7ac32c6d5e561b992d3df
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}
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x := v.Args[1].Args[0]
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mem := v.Args[2]
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v.Op = OpAMD64MOVBstore
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AddArg(ptr)
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v.AddArg(x)
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v.AddArg(mem)
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return true
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}
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goto end25841a70cce7ac32c6d5e561b992d3df
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end25841a70cce7ac32c6d5e561b992d3df:
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;
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case OpAMD64MOVLstore:
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// match: (MOVLstore ptr (MOVLQSX x) mem)
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// cond:
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@ -916,6 +938,28 @@ func rewriteValueAMD64(v *Value, config *Config) bool {
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goto endf79c699f70cb356abb52dc28f4abf46b
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endf79c699f70cb356abb52dc28f4abf46b:
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;
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// match: (MOVLstore ptr (MOVLQZX x) mem)
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// cond:
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// result: (MOVLstore ptr x mem)
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{
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ptr := v.Args[0]
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if v.Args[1].Op != OpAMD64MOVLQZX {
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goto end67d1549d16d373e4ad6a89298866d1bc
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}
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x := v.Args[1].Args[0]
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mem := v.Args[2]
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v.Op = OpAMD64MOVLstore
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AddArg(ptr)
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v.AddArg(x)
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v.AddArg(mem)
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return true
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}
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goto end67d1549d16d373e4ad6a89298866d1bc
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end67d1549d16d373e4ad6a89298866d1bc:
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;
|
||||
case OpAMD64MOVQload:
|
||||
// match: (MOVQload [off1] (ADDQconst [off2] ptr) mem)
|
||||
// cond:
|
||||
@ -1155,6 +1199,28 @@ func rewriteValueAMD64(v *Value, config *Config) bool {
|
||||
goto endcc13af07a951a61fcfec3299342f7e1f
|
||||
endcc13af07a951a61fcfec3299342f7e1f:
|
||||
;
|
||||
// match: (MOVWstore ptr (MOVWQZX x) mem)
|
||||
// cond:
|
||||
// result: (MOVWstore ptr x mem)
|
||||
{
|
||||
ptr := v.Args[0]
|
||||
if v.Args[1].Op != OpAMD64MOVWQZX {
|
||||
goto end4e7df15ee55bdd73d8ecd61b759134d4
|
||||
}
|
||||
x := v.Args[1].Args[0]
|
||||
mem := v.Args[2]
|
||||
v.Op = OpAMD64MOVWstore
|
||||
v.AuxInt = 0
|
||||
v.Aux = nil
|
||||
v.resetArgs()
|
||||
v.AddArg(ptr)
|
||||
v.AddArg(x)
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
goto end4e7df15ee55bdd73d8ecd61b759134d4
|
||||
end4e7df15ee55bdd73d8ecd61b759134d4:
|
||||
;
|
||||
case OpAMD64MULQ:
|
||||
// match: (MULQ x (MOVQconst [c]))
|
||||
// cond: c == int64(int32(c))
|
||||
@ -1355,17 +1421,91 @@ func rewriteValueAMD64(v *Value, config *Config) bool {
|
||||
goto end1b2d226705fd31dbbe74e3286af178ea
|
||||
end1b2d226705fd31dbbe74e3286af178ea:
|
||||
;
|
||||
case OpMul:
|
||||
// match: (Mul <t> x y)
|
||||
// cond: is64BitInt(t)
|
||||
// result: (MULQ x y)
|
||||
case OpMul16:
|
||||
// match: (Mul16 x y)
|
||||
// cond:
|
||||
// result: (MOVWQSX (MULW <v.Type> x y))
|
||||
{
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.Op = OpAMD64MOVWQSX
|
||||
v.AuxInt = 0
|
||||
v.Aux = nil
|
||||
v.resetArgs()
|
||||
v0 := v.Block.NewValue0(v.Line, OpAMD64MULW, TypeInvalid)
|
||||
v0.Type = v.Type
|
||||
v0.AddArg(x)
|
||||
v0.AddArg(y)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
goto end395fc5128ed3789326d04b4555ecfd16
|
||||
end395fc5128ed3789326d04b4555ecfd16:
|
||||
;
|
||||
case OpMul16U:
|
||||
// match: (Mul16U x y)
|
||||
// cond:
|
||||
// result: (MULW x y)
|
||||
{
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.Op = OpAMD64MULW
|
||||
v.AuxInt = 0
|
||||
v.Aux = nil
|
||||
v.resetArgs()
|
||||
v.AddArg(x)
|
||||
v.AddArg(y)
|
||||
return true
|
||||
}
|
||||
goto endec860875a3c61ac3738fa330a3857bb3
|
||||
endec860875a3c61ac3738fa330a3857bb3:
|
||||
;
|
||||
case OpMul32:
|
||||
// match: (Mul32 x y)
|
||||
// cond:
|
||||
// result: (MOVLQSX (MULL <v.Type> x y))
|
||||
{
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.Op = OpAMD64MOVLQSX
|
||||
v.AuxInt = 0
|
||||
v.Aux = nil
|
||||
v.resetArgs()
|
||||
v0 := v.Block.NewValue0(v.Line, OpAMD64MULL, TypeInvalid)
|
||||
v0.Type = v.Type
|
||||
v0.AddArg(x)
|
||||
v0.AddArg(y)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
goto endb756489a642e438ff6e89e55754334e2
|
||||
endb756489a642e438ff6e89e55754334e2:
|
||||
;
|
||||
case OpMul32U:
|
||||
// match: (Mul32U x y)
|
||||
// cond:
|
||||
// result: (MULL x y)
|
||||
{
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.Op = OpAMD64MULL
|
||||
v.AuxInt = 0
|
||||
v.Aux = nil
|
||||
v.resetArgs()
|
||||
v.AddArg(x)
|
||||
v.AddArg(y)
|
||||
return true
|
||||
}
|
||||
goto ende4c566176fb13075292de5ccb016c5fc
|
||||
ende4c566176fb13075292de5ccb016c5fc:
|
||||
;
|
||||
case OpMul64:
|
||||
// match: (Mul64 x y)
|
||||
// cond:
|
||||
// result: (MULQ x y)
|
||||
{
|
||||
t := v.Type
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
if !(is64BitInt(t)) {
|
||||
goto endfab0d598f376ecba45a22587d50f7aff
|
||||
}
|
||||
v.Op = OpAMD64MULQ
|
||||
v.AuxInt = 0
|
||||
v.Aux = nil
|
||||
@ -1374,8 +1514,86 @@ func rewriteValueAMD64(v *Value, config *Config) bool {
|
||||
v.AddArg(y)
|
||||
return true
|
||||
}
|
||||
goto endfab0d598f376ecba45a22587d50f7aff
|
||||
endfab0d598f376ecba45a22587d50f7aff:
|
||||
goto end38da21e77ac329eb643b20e7d97d5853
|
||||
end38da21e77ac329eb643b20e7d97d5853:
|
||||
;
|
||||
case OpMul64U:
|
||||
// match: (Mul64U x y)
|
||||
// cond:
|
||||
// result: (MULQ x y)
|
||||
{
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.Op = OpAMD64MULQ
|
||||
v.AuxInt = 0
|
||||
v.Aux = nil
|
||||
v.resetArgs()
|
||||
v.AddArg(x)
|
||||
v.AddArg(y)
|
||||
return true
|
||||
}
|
||||
goto end3da28ba90850e15f0ed2c37fbce90650
|
||||
end3da28ba90850e15f0ed2c37fbce90650:
|
||||
;
|
||||
case OpMul8:
|
||||
// match: (Mul8 x y)
|
||||
// cond:
|
||||
// result: (MOVBQSX (MULW <TypeInt16> x y))
|
||||
{
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.Op = OpAMD64MOVBQSX
|
||||
v.AuxInt = 0
|
||||
v.Aux = nil
|
||||
v.resetArgs()
|
||||
v0 := v.Block.NewValue0(v.Line, OpAMD64MULW, TypeInvalid)
|
||||
v0.Type = TypeInt16
|
||||
v0.AddArg(x)
|
||||
v0.AddArg(y)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
goto end418ba69107bb1e02d5015c73c9f9a5c9
|
||||
end418ba69107bb1e02d5015c73c9f9a5c9:
|
||||
;
|
||||
case OpMul8U:
|
||||
// match: (Mul8U x y)
|
||||
// cond:
|
||||
// result: (MOVBQZX (MULW <TypeUInt16> x y))
|
||||
{
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.Op = OpAMD64MOVBQZX
|
||||
v.AuxInt = 0
|
||||
v.Aux = nil
|
||||
v.resetArgs()
|
||||
v0 := v.Block.NewValue0(v.Line, OpAMD64MULW, TypeInvalid)
|
||||
v0.Type = TypeUInt16
|
||||
v0.AddArg(x)
|
||||
v0.AddArg(y)
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
goto end9d0a972d9b8a32b84ed38a32bfeb01b6
|
||||
end9d0a972d9b8a32b84ed38a32bfeb01b6:
|
||||
;
|
||||
case OpMulPtr:
|
||||
// match: (MulPtr x y)
|
||||
// cond:
|
||||
// result: (MULQ x y)
|
||||
{
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.Op = OpAMD64MULQ
|
||||
v.AuxInt = 0
|
||||
v.Aux = nil
|
||||
v.resetArgs()
|
||||
v.AddArg(x)
|
||||
v.AddArg(y)
|
||||
return true
|
||||
}
|
||||
goto endbbedad106c011a93243e2062afdcc75f
|
||||
endbbedad106c011a93243e2062afdcc75f:
|
||||
;
|
||||
case OpNeg16:
|
||||
// match: (Neg16 x)
|
||||
|
||||
@ -50,6 +50,29 @@ func rewriteValuegeneric(v *Value, config *Config) bool {
|
||||
goto endfedc373d8be0243cb5dbbc948996fe3a
|
||||
endfedc373d8be0243cb5dbbc948996fe3a:
|
||||
;
|
||||
case OpAddPtr:
|
||||
// match: (AddPtr (Const [c]) (Const [d]))
|
||||
// cond:
|
||||
// result: (Const [c+d])
|
||||
{
|
||||
if v.Args[0].Op != OpConst {
|
||||
goto end67284cb7ae441d6c763096b49a3569a3
|
||||
}
|
||||
c := v.Args[0].AuxInt
|
||||
if v.Args[1].Op != OpConst {
|
||||
goto end67284cb7ae441d6c763096b49a3569a3
|
||||
}
|
||||
d := v.Args[1].AuxInt
|
||||
v.Op = OpConst
|
||||
v.AuxInt = 0
|
||||
v.Aux = nil
|
||||
v.resetArgs()
|
||||
v.AuxInt = c + d
|
||||
return true
|
||||
}
|
||||
goto end67284cb7ae441d6c763096b49a3569a3
|
||||
end67284cb7ae441d6c763096b49a3569a3:
|
||||
;
|
||||
case OpArrayIndex:
|
||||
// match: (ArrayIndex (Load ptr mem) idx)
|
||||
// cond:
|
||||
@ -167,23 +190,19 @@ func rewriteValuegeneric(v *Value, config *Config) bool {
|
||||
goto endce3ba169a57b8a9f6b12751d49b4e23a
|
||||
endce3ba169a57b8a9f6b12751d49b4e23a:
|
||||
;
|
||||
case OpMul:
|
||||
// match: (Mul <t> (Const [c]) (Const [d]))
|
||||
// cond: is64BitInt(t)
|
||||
case OpMul64:
|
||||
// match: (Mul64 (Const [c]) (Const [d]))
|
||||
// cond:
|
||||
// result: (Const [c*d])
|
||||
{
|
||||
t := v.Type
|
||||
if v.Args[0].Op != OpConst {
|
||||
goto endd82095c6a872974522d33aaff1ee07be
|
||||
goto endf4ba5346dc8a624781afaa68a8096a9a
|
||||
}
|
||||
c := v.Args[0].AuxInt
|
||||
if v.Args[1].Op != OpConst {
|
||||
goto endd82095c6a872974522d33aaff1ee07be
|
||||
goto endf4ba5346dc8a624781afaa68a8096a9a
|
||||
}
|
||||
d := v.Args[1].AuxInt
|
||||
if !(is64BitInt(t)) {
|
||||
goto endd82095c6a872974522d33aaff1ee07be
|
||||
}
|
||||
v.Op = OpConst
|
||||
v.AuxInt = 0
|
||||
v.Aux = nil
|
||||
@ -191,13 +210,59 @@ func rewriteValuegeneric(v *Value, config *Config) bool {
|
||||
v.AuxInt = c * d
|
||||
return true
|
||||
}
|
||||
goto endd82095c6a872974522d33aaff1ee07be
|
||||
endd82095c6a872974522d33aaff1ee07be:
|
||||
goto endf4ba5346dc8a624781afaa68a8096a9a
|
||||
endf4ba5346dc8a624781afaa68a8096a9a:
|
||||
;
|
||||
case OpMul64U:
|
||||
// match: (Mul64U (Const [c]) (Const [d]))
|
||||
// cond:
|
||||
// result: (Const [c*d])
|
||||
{
|
||||
if v.Args[0].Op != OpConst {
|
||||
goto end88b6638d23b281a90172e80ab26549cb
|
||||
}
|
||||
c := v.Args[0].AuxInt
|
||||
if v.Args[1].Op != OpConst {
|
||||
goto end88b6638d23b281a90172e80ab26549cb
|
||||
}
|
||||
d := v.Args[1].AuxInt
|
||||
v.Op = OpConst
|
||||
v.AuxInt = 0
|
||||
v.Aux = nil
|
||||
v.resetArgs()
|
||||
v.AuxInt = c * d
|
||||
return true
|
||||
}
|
||||
goto end88b6638d23b281a90172e80ab26549cb
|
||||
end88b6638d23b281a90172e80ab26549cb:
|
||||
;
|
||||
case OpMulPtr:
|
||||
// match: (MulPtr (Const [c]) (Const [d]))
|
||||
// cond:
|
||||
// result: (Const [c*d])
|
||||
{
|
||||
if v.Args[0].Op != OpConst {
|
||||
goto end10541de7ea2bce703c1e372ac9a271e7
|
||||
}
|
||||
c := v.Args[0].AuxInt
|
||||
if v.Args[1].Op != OpConst {
|
||||
goto end10541de7ea2bce703c1e372ac9a271e7
|
||||
}
|
||||
d := v.Args[1].AuxInt
|
||||
v.Op = OpConst
|
||||
v.AuxInt = 0
|
||||
v.Aux = nil
|
||||
v.resetArgs()
|
||||
v.AuxInt = c * d
|
||||
return true
|
||||
}
|
||||
goto end10541de7ea2bce703c1e372ac9a271e7
|
||||
end10541de7ea2bce703c1e372ac9a271e7:
|
||||
;
|
||||
case OpPtrIndex:
|
||||
// match: (PtrIndex <t> ptr idx)
|
||||
// cond:
|
||||
// result: (AddPtr ptr (Mul <config.Uintptr> idx (Const <config.Uintptr> [t.Elem().Size()])))
|
||||
// result: (AddPtr ptr (MulPtr <config.Uintptr> idx (Const <config.Uintptr> [t.Elem().Size()])))
|
||||
{
|
||||
t := v.Type
|
||||
ptr := v.Args[0]
|
||||
@ -207,7 +272,7 @@ func rewriteValuegeneric(v *Value, config *Config) bool {
|
||||
v.Aux = nil
|
||||
v.resetArgs()
|
||||
v.AddArg(ptr)
|
||||
v0 := v.Block.NewValue0(v.Line, OpMul, TypeInvalid)
|
||||
v0 := v.Block.NewValue0(v.Line, OpMulPtr, TypeInvalid)
|
||||
v0.Type = config.Uintptr
|
||||
v0.AddArg(idx)
|
||||
v1 := v.Block.NewValue0(v.Line, OpConst, TypeInvalid)
|
||||
@ -217,8 +282,8 @@ func rewriteValuegeneric(v *Value, config *Config) bool {
|
||||
v.AddArg(v0)
|
||||
return true
|
||||
}
|
||||
goto endc181347cd3c740e2a1da431a981fdd7e
|
||||
endc181347cd3c740e2a1da431a981fdd7e:
|
||||
goto endb39bbe157d1791123f6083b2cfc59ddc
|
||||
endb39bbe157d1791123f6083b2cfc59ddc:
|
||||
;
|
||||
case OpSliceCap:
|
||||
// match: (SliceCap (Load ptr mem))
|
||||
|
||||
Loading…
Reference in New Issue
Block a user