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cmd/internal/obj/mips: fix encoding of FCR registers
The asm encoder generally assumes that the lowest 5 bits of the REG_XX constants match the machine instruction encoding, i.e. the lowest 5 bits is the register number. This was not true for FCR registers and M registers. Make it so. MOV Rx, FCRy was encoded as two machine instructions. The first is unnecessary. Remove. Change-Id: Ib988e6b109ba8f564337cdd31019c1a6f1881f5b Reviewed-on: https://go-review.googlesource.com/c/go/+/203717 Run-TryBot: Cherry Zhang <cherryyz@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Austin Clements <austin@google.com>
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13
src/cmd/asm/internal/asm/testdata/mips64.s
vendored
13
src/cmd/asm/internal/asm/testdata/mips64.s
vendored
@ -130,27 +130,27 @@ TEXT foo(SB),DUPOK|NOSPLIT,$0
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// {
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// outcode(int($1), &$2, 0, &$4);
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// }
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MOVW FCR0, R1
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MOVW FCR31, R1 // 4441f800
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// LMOVW freg ',' fpscr
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// {
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// outcode(int($1), &$2, 0, &$4);
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// }
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MOVW R1, FCR0
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MOVW R1, FCR31 // 44c1f800
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// LMOVW rreg ',' mreg
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// {
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// outcode(int($1), &$2, 0, &$4);
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// }
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MOVW R1, M1
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MOVV R1, M1
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MOVW R1, M1 // 40810800
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MOVV R1, M1 // 40a10800
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// LMOVW mreg ',' rreg
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// {
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// outcode(int($1), &$2, 0, &$4);
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// }
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MOVW M1, R1
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MOVV M1, R1
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MOVW M1, R1 // 40010800
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MOVV M1, R1 // 40210800
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//
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@ -406,6 +406,7 @@ label4:
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NEGW R1, R2 // 00011023
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NEGV R1, R2 // 0001102f
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RET
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// END
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//
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@ -46,7 +46,7 @@ const (
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)
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const (
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REG_R0 = obj.RBaseMIPS + iota
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REG_R0 = obj.RBaseMIPS + iota // must be a multiple of 32
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REG_R1
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REG_R2
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REG_R3
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@ -79,7 +79,7 @@ const (
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REG_R30
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REG_R31
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REG_F0
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REG_F0 // must be a multiple of 32
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REG_F1
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REG_F2
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REG_F3
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@ -112,11 +112,8 @@ const (
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REG_F30
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REG_F31
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REG_HI
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REG_LO
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// co-processor 0 control registers
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REG_M0
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REG_M0 // must be a multiple of 32
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REG_M1
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REG_M2
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REG_M3
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@ -150,7 +147,7 @@ const (
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REG_M31
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// FPU control registers
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REG_FCR0
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REG_FCR0 // must be a multiple of 32
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REG_FCR1
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REG_FCR2
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REG_FCR3
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@ -183,7 +180,10 @@ const (
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REG_FCR30
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REG_FCR31
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REG_LAST = REG_FCR31 // the last defined register
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REG_HI
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REG_LO
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REG_LAST = REG_LO // the last defined register
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REG_SPECIAL = REG_M0
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@ -412,3 +412,22 @@ const (
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AJAL = obj.ACALL
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ARET = obj.ARET
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)
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func init() {
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// The asm encoder generally assumes that the lowest 5 bits of the
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// REG_XX constants match the machine instruction encoding, i.e.
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// the lowest 5 bits is the register number.
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// Check this here.
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if REG_R0%32 != 0 {
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panic("REG_R0 is not a multiple of 32")
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}
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if REG_F0%32 != 0 {
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panic("REG_F0 is not a multiple of 32")
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}
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if REG_M0%32 != 0 {
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panic("REG_M0 is not a multiple of 32")
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}
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if REG_FCR0%32 != 0 {
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panic("REG_FCR0 is not a multiple of 32")
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}
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}
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@ -362,8 +362,8 @@ var optab = []Optab{
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{AWORD, C_LCON, C_NONE, C_NONE, 40, 4, 0, 0},
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{AMOVW, C_REG, C_NONE, C_FCREG, 41, 8, 0, 0},
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{AMOVV, C_REG, C_NONE, C_FCREG, 41, 8, 0, sys.MIPS64},
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{AMOVW, C_REG, C_NONE, C_FCREG, 41, 4, 0, 0},
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{AMOVV, C_REG, C_NONE, C_FCREG, 41, 4, 0, sys.MIPS64},
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{AMOVW, C_FCREG, C_NONE, C_REG, 42, 4, 0, 0},
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{AMOVV, C_FCREG, C_NONE, C_REG, 42, 4, 0, sys.MIPS64},
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@ -1476,8 +1476,7 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
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o1 = uint32(c.regoff(&p.From))
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case 41: /* movw f,fcr */
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o1 = OP_RRR(SP(2, 1)|(2<<21), uint32(REGZERO), uint32(0), uint32(p.To.Reg)) /* mfcc1 */
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o2 = OP_RRR(SP(2, 1)|(6<<21), uint32(p.From.Reg), uint32(0), uint32(p.To.Reg)) /* mtcc1 */
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o1 = OP_RRR(SP(2, 1)|(6<<21), uint32(p.From.Reg), uint32(0), uint32(p.To.Reg)) /* mtcc1 */
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case 42: /* movw fcr,r */
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o1 = OP_RRR(SP(2, 1)|(2<<21), uint32(p.To.Reg), uint32(0), uint32(p.From.Reg)) /* mfcc1 */
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