mirror of
https://github.com/golang/go
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cmd/compile: adopt strong aux typing for some s390x rules
Apply strong aux typing to lowering rules that do not require modification beyond substituting -> for =>. Other lowering rules and all the optimization rules will follow. I'm breaking it up to allow toolstash-check to pass on the big CLs. Passes toolstash-check -all. Change-Id: I6f1340058a8eb5a1390411e59fcbea9d7f777e58 Reviewed-on: https://go-review.googlesource.com/c/go/+/229400 Run-TryBot: Michael Munday <mike.munday@ibm.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Keith Randall <khr@golang.org>
This commit is contained in:
Michael Munday
parent
925d6b31b0
commit
b7a5e7ae92
@ -3,77 +3,77 @@
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// license that can be found in the LICENSE file.
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// Lowering arithmetic
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(Add(64|Ptr) ...) -> (ADD ...)
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(Add(32|16|8) ...) -> (ADDW ...)
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(Add32F x y) -> (Select0 (FADDS x y))
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(Add64F x y) -> (Select0 (FADD x y))
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(Add(64|Ptr) ...) => (ADD ...)
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(Add(32|16|8) ...) => (ADDW ...)
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(Add32F x y) => (Select0 (FADDS x y))
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(Add64F x y) => (Select0 (FADD x y))
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(Sub(64|Ptr) ...) -> (SUB ...)
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(Sub(32|16|8) ...) -> (SUBW ...)
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(Sub32F x y) -> (Select0 (FSUBS x y))
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(Sub64F x y) -> (Select0 (FSUB x y))
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(Sub(64|Ptr) ...) => (SUB ...)
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(Sub(32|16|8) ...) => (SUBW ...)
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(Sub32F x y) => (Select0 (FSUBS x y))
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(Sub64F x y) => (Select0 (FSUB x y))
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(Mul64 ...) -> (MULLD ...)
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(Mul(32|16|8) ...) -> (MULLW ...)
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(Mul32F ...) -> (FMULS ...)
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(Mul64F ...) -> (FMUL ...)
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(Mul64uhilo ...) -> (MLGR ...)
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(Mul64 ...) => (MULLD ...)
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(Mul(32|16|8) ...) => (MULLW ...)
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(Mul32F ...) => (FMULS ...)
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(Mul64F ...) => (FMUL ...)
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(Mul64uhilo ...) => (MLGR ...)
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(Div32F ...) -> (FDIVS ...)
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(Div64F ...) -> (FDIV ...)
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(Div32F ...) => (FDIVS ...)
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(Div64F ...) => (FDIV ...)
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(Div64 ...) -> (DIVD ...)
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(Div64u ...) -> (DIVDU ...)
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(Div64u ...) => (DIVDU ...)
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// DIVW/DIVWU has a 64-bit dividend and a 32-bit divisor,
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// so a sign/zero extension of the dividend is required.
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(Div32 x y) -> (DIVW (MOVWreg x) y)
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(Div32u x y) -> (DIVWU (MOVWZreg x) y)
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(Div16 x y) -> (DIVW (MOVHreg x) (MOVHreg y))
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(Div16u x y) -> (DIVWU (MOVHZreg x) (MOVHZreg y))
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(Div8 x y) -> (DIVW (MOVBreg x) (MOVBreg y))
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(Div8u x y) -> (DIVWU (MOVBZreg x) (MOVBZreg y))
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(Div32 x y) => (DIVW (MOVWreg x) y)
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(Div32u x y) => (DIVWU (MOVWZreg x) y)
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(Div16 x y) => (DIVW (MOVHreg x) (MOVHreg y))
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(Div16u x y) => (DIVWU (MOVHZreg x) (MOVHZreg y))
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(Div8 x y) => (DIVW (MOVBreg x) (MOVBreg y))
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(Div8u x y) => (DIVWU (MOVBZreg x) (MOVBZreg y))
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(Hmul(64|64u) ...) -> (MULH(D|DU) ...)
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(Hmul32 x y) -> (SRDconst [32] (MULLD (MOVWreg x) (MOVWreg y)))
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(Hmul32u x y) -> (SRDconst [32] (MULLD (MOVWZreg x) (MOVWZreg y)))
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(Hmul(64|64u) ...) => (MULH(D|DU) ...)
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(Hmul32 x y) => (SRDconst [32] (MULLD (MOVWreg x) (MOVWreg y)))
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(Hmul32u x y) => (SRDconst [32] (MULLD (MOVWZreg x) (MOVWZreg y)))
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(Mod64 ...) -> (MODD ...)
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(Mod64u ...) -> (MODDU ...)
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(Mod64u ...) => (MODDU ...)
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// MODW/MODWU has a 64-bit dividend and a 32-bit divisor,
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// so a sign/zero extension of the dividend is required.
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(Mod32 x y) -> (MODW (MOVWreg x) y)
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(Mod32u x y) -> (MODWU (MOVWZreg x) y)
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(Mod16 x y) -> (MODW (MOVHreg x) (MOVHreg y))
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(Mod16u x y) -> (MODWU (MOVHZreg x) (MOVHZreg y))
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(Mod8 x y) -> (MODW (MOVBreg x) (MOVBreg y))
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(Mod8u x y) -> (MODWU (MOVBZreg x) (MOVBZreg y))
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(Mod32 x y) => (MODW (MOVWreg x) y)
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(Mod32u x y) => (MODWU (MOVWZreg x) y)
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(Mod16 x y) => (MODW (MOVHreg x) (MOVHreg y))
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(Mod16u x y) => (MODWU (MOVHZreg x) (MOVHZreg y))
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(Mod8 x y) => (MODW (MOVBreg x) (MOVBreg y))
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(Mod8u x y) => (MODWU (MOVBZreg x) (MOVBZreg y))
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// (x + y) / 2 with x>=y -> (x - y) / 2 + y
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(Avg64u <t> x y) -> (ADD (SRDconst <t> (SUB <t> x y) [1]) y)
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(Avg64u <t> x y) => (ADD (SRDconst <t> (SUB <t> x y) [1]) y)
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(And64 ...) -> (AND ...)
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(And(32|16|8) ...) -> (ANDW ...)
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(And64 ...) => (AND ...)
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(And(32|16|8) ...) => (ANDW ...)
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(Or64 ...) -> (OR ...)
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(Or(32|16|8) ...) -> (ORW ...)
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(Or64 ...) => (OR ...)
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(Or(32|16|8) ...) => (ORW ...)
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(Xor64 ...) -> (XOR ...)
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(Xor(32|16|8) ...) -> (XORW ...)
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(Xor64 ...) => (XOR ...)
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(Xor(32|16|8) ...) => (XORW ...)
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(Neg64 ...) -> (NEG ...)
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(Neg(32|16|8) ...) -> (NEGW ...)
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(Neg32F ...) -> (FNEGS ...)
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(Neg64F ...) -> (FNEG ...)
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(Neg64 ...) => (NEG ...)
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(Neg(32|16|8) ...) => (NEGW ...)
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(Neg32F ...) => (FNEGS ...)
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(Neg64F ...) => (FNEG ...)
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(Com64 ...) -> (NOT ...)
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(Com(32|16|8) ...) -> (NOTW ...)
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(NOT x) -> (XOR (MOVDconst [-1]) x)
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(NOTW x) -> (XORWconst [-1] x)
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(Com64 ...) => (NOT ...)
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(Com(32|16|8) ...) => (NOTW ...)
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(NOT x) => (XOR (MOVDconst [-1]) x)
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(NOTW x) => (XORWconst [-1] x)
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// Lowering boolean ops
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(AndB ...) -> (ANDW ...)
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(OrB ...) -> (ORW ...)
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(Not x) -> (XORWconst [1] x)
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(AndB ...) => (ANDW ...)
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(OrB ...) => (ORW ...)
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(Not x) => (XORWconst [1] x)
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// Lowering pointer arithmetic
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(OffPtr [off] ptr:(SP)) -> (MOVDaddr [off] ptr)
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@ -81,14 +81,14 @@
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(OffPtr [off] ptr) -> (ADD (MOVDconst [off]) ptr)
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// TODO: optimize these cases?
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(Ctz64NonZero ...) -> (Ctz64 ...)
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(Ctz32NonZero ...) -> (Ctz32 ...)
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(Ctz64NonZero ...) => (Ctz64 ...)
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(Ctz32NonZero ...) => (Ctz32 ...)
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// Ctz(x) = 64 - findLeftmostOne((x-1)&^x)
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(Ctz64 <t> x) -> (SUB (MOVDconst [64]) (FLOGR (AND <t> (SUBconst <t> [1] x) (NOT <t> x))))
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(Ctz32 <t> x) -> (SUB (MOVDconst [64]) (FLOGR (MOVWZreg (ANDW <t> (SUBWconst <t> [1] x) (NOTW <t> x)))))
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(Ctz64 <t> x) => (SUB (MOVDconst [64]) (FLOGR (AND <t> (SUBconst <t> [1] x) (NOT <t> x))))
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(Ctz32 <t> x) => (SUB (MOVDconst [64]) (FLOGR (MOVWZreg (ANDW <t> (SUBWconst <t> [1] x) (NOTW <t> x)))))
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(BitLen64 x) -> (SUB (MOVDconst [64]) (FLOGR x))
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(BitLen64 x) => (SUB (MOVDconst [64]) (FLOGR x))
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// POPCNT treats the input register as a vector of 8 bytes, producing
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// a population count for each individual byte. For inputs larger than
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@ -105,60 +105,60 @@
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// ADDW R4, R5, R6 // R6=0x0205090d
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// MOVBZ R6, R7 // R7=0x0000000d <-- result is 13
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//
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(PopCount8 x) -> (POPCNT (MOVBZreg x))
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(PopCount16 x) -> (MOVBZreg (SumBytes2 (POPCNT <typ.UInt16> x)))
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(PopCount32 x) -> (MOVBZreg (SumBytes4 (POPCNT <typ.UInt32> x)))
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(PopCount64 x) -> (MOVBZreg (SumBytes8 (POPCNT <typ.UInt64> x)))
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(PopCount8 x) => (POPCNT (MOVBZreg x))
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(PopCount16 x) => (MOVBZreg (SumBytes2 (POPCNT <typ.UInt16> x)))
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(PopCount32 x) => (MOVBZreg (SumBytes4 (POPCNT <typ.UInt32> x)))
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(PopCount64 x) => (MOVBZreg (SumBytes8 (POPCNT <typ.UInt64> x)))
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// SumBytes{2,4,8} pseudo operations sum the values of the rightmost
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// 2, 4 or 8 bytes respectively. The result is a single byte however
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// other bytes might contain junk so a zero extension is required if
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// the desired output type is larger than 1 byte.
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(SumBytes2 x) -> (ADDW (SRWconst <typ.UInt8> x [8]) x)
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(SumBytes4 x) -> (SumBytes2 (ADDW <typ.UInt16> (SRWconst <typ.UInt16> x [16]) x))
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(SumBytes8 x) -> (SumBytes4 (ADDW <typ.UInt32> (SRDconst <typ.UInt32> x [32]) x))
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(SumBytes2 x) => (ADDW (SRWconst <typ.UInt8> x [8]) x)
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(SumBytes4 x) => (SumBytes2 (ADDW <typ.UInt16> (SRWconst <typ.UInt16> x [16]) x))
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(SumBytes8 x) => (SumBytes4 (ADDW <typ.UInt32> (SRDconst <typ.UInt32> x [32]) x))
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(Bswap64 ...) -> (MOVDBR ...)
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(Bswap32 ...) -> (MOVWBR ...)
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(Bswap64 ...) => (MOVDBR ...)
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(Bswap32 ...) => (MOVWBR ...)
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// add with carry
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(Select0 (Add64carry x y c))
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-> (Select0 <typ.UInt64> (ADDE x y (Select1 <types.TypeFlags> (ADDCconst c [-1]))))
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=> (Select0 <typ.UInt64> (ADDE x y (Select1 <types.TypeFlags> (ADDCconst c [-1]))))
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(Select1 (Add64carry x y c))
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-> (Select0 <typ.UInt64> (ADDE (MOVDconst [0]) (MOVDconst [0]) (Select1 <types.TypeFlags> (ADDE x y (Select1 <types.TypeFlags> (ADDCconst c [-1]))))))
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=> (Select0 <typ.UInt64> (ADDE (MOVDconst [0]) (MOVDconst [0]) (Select1 <types.TypeFlags> (ADDE x y (Select1 <types.TypeFlags> (ADDCconst c [-1]))))))
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// subtract with borrow
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(Select0 (Sub64borrow x y c))
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-> (Select0 <typ.UInt64> (SUBE x y (Select1 <types.TypeFlags> (SUBC (MOVDconst [0]) c))))
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=> (Select0 <typ.UInt64> (SUBE x y (Select1 <types.TypeFlags> (SUBC (MOVDconst [0]) c))))
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(Select1 (Sub64borrow x y c))
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-> (NEG (Select0 <typ.UInt64> (SUBE (MOVDconst [0]) (MOVDconst [0]) (Select1 <types.TypeFlags> (SUBE x y (Select1 <types.TypeFlags> (SUBC (MOVDconst [0]) c)))))))
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=> (NEG (Select0 <typ.UInt64> (SUBE (MOVDconst [0]) (MOVDconst [0]) (Select1 <types.TypeFlags> (SUBE x y (Select1 <types.TypeFlags> (SUBC (MOVDconst [0]) c)))))))
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// math package intrinsics
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(Sqrt ...) -> (FSQRT ...)
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(Floor x) -> (FIDBR [7] x)
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(Ceil x) -> (FIDBR [6] x)
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(Trunc x) -> (FIDBR [5] x)
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(RoundToEven x) -> (FIDBR [4] x)
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(Round x) -> (FIDBR [1] x)
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(FMA x y z) -> (FMADD z x y)
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(Sqrt ...) => (FSQRT ...)
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(Floor x) => (FIDBR [7] x)
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(Ceil x) => (FIDBR [6] x)
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(Trunc x) => (FIDBR [5] x)
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(RoundToEven x) => (FIDBR [4] x)
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(Round x) => (FIDBR [1] x)
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(FMA x y z) => (FMADD z x y)
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// Atomic loads and stores.
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// The SYNC instruction (fast-BCR-serialization) prevents store-load
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// reordering. Other sequences of memory operations (load-load,
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// store-store and load-store) are already guaranteed not to be reordered.
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(AtomicLoad(8|32|Acq32|64|Ptr) ...) -> (MOV(BZ|WZ|WZ|D|D)atomicload ...)
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(AtomicStore(8|32|64|PtrNoWB) ptr val mem) -> (SYNC (MOV(B|W|D|D)atomicstore ptr val mem))
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(AtomicStore(8|32|64|PtrNoWB) ptr val mem) => (SYNC (MOV(B|W|D|D)atomicstore ptr val mem))
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// Store-release doesn't require store-load ordering.
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(AtomicStoreRel32 ...) -> (MOVWatomicstore ...)
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// Atomic adds.
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(AtomicAdd32 ptr val mem) -> (AddTupleFirst32 val (LAA ptr val mem))
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(AtomicAdd64 ptr val mem) -> (AddTupleFirst64 val (LAAG ptr val mem))
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(Select0 <t> (AddTupleFirst32 val tuple)) -> (ADDW val (Select0 <t> tuple))
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(Select1 (AddTupleFirst32 _ tuple)) -> (Select1 tuple)
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(Select0 <t> (AddTupleFirst64 val tuple)) -> (ADD val (Select0 <t> tuple))
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(Select1 (AddTupleFirst64 _ tuple)) -> (Select1 tuple)
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(AtomicAdd32 ptr val mem) => (AddTupleFirst32 val (LAA ptr val mem))
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(AtomicAdd64 ptr val mem) => (AddTupleFirst64 val (LAAG ptr val mem))
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(Select0 <t> (AddTupleFirst32 val tuple)) => (ADDW val (Select0 <t> tuple))
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(Select1 (AddTupleFirst32 _ tuple)) => (Select1 tuple)
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(Select0 <t> (AddTupleFirst64 val tuple)) => (ADD val (Select0 <t> tuple))
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(Select1 (AddTupleFirst64 _ tuple)) => (Select1 tuple)
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// Atomic exchanges.
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(AtomicExchange32 ...) -> (LoweredAtomicExchange32 ...)
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@ -176,7 +176,7 @@
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// *(*uint32)(ptr &^ 3) &= rotateleft(uint32(val) | 0xffffff00, ((3 << 3) ^ ((ptr & 3) << 3))
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//
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(AtomicAnd8 ptr val mem)
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-> (LANfloor
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=> (LANfloor
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ptr
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(RLL <typ.UInt32>
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(ORWconst <typ.UInt32> val [-1<<8])
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@ -191,7 +191,7 @@
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// *(*uint32)(ptr &^ 3) |= uint32(val) << ((3 << 3) ^ ((ptr & 3) << 3))
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//
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(AtomicOr8 ptr val mem)
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-> (LAOfloor
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=> (LAOfloor
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ptr
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(SLW <typ.UInt32>
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(MOVBZreg <typ.UInt32> val)
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@ -200,145 +200,145 @@
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// Lowering extension
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// Note: we always extend to 64 bits even though some ops don't need that many result bits.
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(SignExt8to(16|32|64) ...) -> (MOVBreg ...)
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(SignExt16to(32|64) ...) -> (MOVHreg ...)
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(SignExt32to64 ...) -> (MOVWreg ...)
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(SignExt8to(16|32|64) ...) => (MOVBreg ...)
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(SignExt16to(32|64) ...) => (MOVHreg ...)
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(SignExt32to64 ...) => (MOVWreg ...)
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(ZeroExt8to(16|32|64) ...) -> (MOVBZreg ...)
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(ZeroExt16to(32|64) ...) -> (MOVHZreg ...)
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(ZeroExt32to64 ...) -> (MOVWZreg ...)
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(ZeroExt8to(16|32|64) ...) => (MOVBZreg ...)
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(ZeroExt16to(32|64) ...) => (MOVHZreg ...)
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(ZeroExt32to64 ...) => (MOVWZreg ...)
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(Slicemask <t> x) -> (SRADconst (NEG <t> x) [63])
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(Slicemask <t> x) => (SRADconst (NEG <t> x) [63])
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// Lowering truncation
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// Because we ignore high parts of registers, truncates are just copies.
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(Trunc(16|32|64)to8 ...) -> (Copy ...)
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(Trunc(32|64)to16 ...) -> (Copy ...)
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(Trunc64to32 ...) -> (Copy ...)
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(Trunc(16|32|64)to8 ...) => (Copy ...)
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(Trunc(32|64)to16 ...) => (Copy ...)
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(Trunc64to32 ...) => (Copy ...)
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// Lowering float <-> int
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(Cvt32to32F ...) -> (CEFBRA ...)
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(Cvt32to64F ...) -> (CDFBRA ...)
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(Cvt64to32F ...) -> (CEGBRA ...)
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(Cvt64to64F ...) -> (CDGBRA ...)
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(Cvt32to32F ...) => (CEFBRA ...)
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(Cvt32to64F ...) => (CDFBRA ...)
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(Cvt64to32F ...) => (CEGBRA ...)
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(Cvt64to64F ...) => (CDGBRA ...)
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(Cvt32Fto32 ...) -> (CFEBRA ...)
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(Cvt32Fto64 ...) -> (CGEBRA ...)
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(Cvt64Fto32 ...) -> (CFDBRA ...)
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(Cvt64Fto64 ...) -> (CGDBRA ...)
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(Cvt32Fto32 ...) => (CFEBRA ...)
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(Cvt32Fto64 ...) => (CGEBRA ...)
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(Cvt64Fto32 ...) => (CFDBRA ...)
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(Cvt64Fto64 ...) => (CGDBRA ...)
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// Lowering float <-> uint
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(Cvt32Uto32F ...) -> (CELFBR ...)
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(Cvt32Uto64F ...) -> (CDLFBR ...)
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(Cvt64Uto32F ...) -> (CELGBR ...)
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(Cvt64Uto64F ...) -> (CDLGBR ...)
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(Cvt32Uto32F ...) => (CELFBR ...)
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(Cvt32Uto64F ...) => (CDLFBR ...)
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(Cvt64Uto32F ...) => (CELGBR ...)
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(Cvt64Uto64F ...) => (CDLGBR ...)
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(Cvt32Fto32U ...) -> (CLFEBR ...)
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(Cvt32Fto64U ...) -> (CLGEBR ...)
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(Cvt64Fto32U ...) -> (CLFDBR ...)
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(Cvt64Fto64U ...) -> (CLGDBR ...)
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(Cvt32Fto32U ...) => (CLFEBR ...)
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(Cvt32Fto64U ...) => (CLGEBR ...)
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(Cvt64Fto32U ...) => (CLFDBR ...)
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(Cvt64Fto64U ...) => (CLGDBR ...)
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// Lowering float32 <-> float64
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(Cvt32Fto64F ...) -> (LDEBR ...)
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(Cvt64Fto32F ...) -> (LEDBR ...)
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(Cvt32Fto64F ...) => (LDEBR ...)
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(Cvt64Fto32F ...) => (LEDBR ...)
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(CvtBoolToUint8 ...) -> (Copy ...)
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||||
(CvtBoolToUint8 ...) => (Copy ...)
|
||||
|
||||
(Round(32|64)F ...) -> (LoweredRound(32|64)F ...)
|
||||
(Round(32|64)F ...) => (LoweredRound(32|64)F ...)
|
||||
|
||||
// Lowering shifts
|
||||
|
||||
// Lower bounded shifts first. No need to check shift value.
|
||||
(Lsh64x(64|32|16|8) x y) && shiftIsBounded(v) -> (SLD x y)
|
||||
(Lsh32x(64|32|16|8) x y) && shiftIsBounded(v) -> (SLW x y)
|
||||
(Lsh16x(64|32|16|8) x y) && shiftIsBounded(v) -> (SLW x y)
|
||||
(Lsh8x(64|32|16|8) x y) && shiftIsBounded(v) -> (SLW x y)
|
||||
(Rsh64Ux(64|32|16|8) x y) && shiftIsBounded(v) -> (SRD x y)
|
||||
(Rsh32Ux(64|32|16|8) x y) && shiftIsBounded(v) -> (SRW x y)
|
||||
(Rsh16Ux(64|32|16|8) x y) && shiftIsBounded(v) -> (SRW (MOVHZreg x) y)
|
||||
(Rsh8Ux(64|32|16|8) x y) && shiftIsBounded(v) -> (SRW (MOVBZreg x) y)
|
||||
(Rsh64x(64|32|16|8) x y) && shiftIsBounded(v) -> (SRAD x y)
|
||||
(Rsh32x(64|32|16|8) x y) && shiftIsBounded(v) -> (SRAW x y)
|
||||
(Rsh16x(64|32|16|8) x y) && shiftIsBounded(v) -> (SRAW (MOVHreg x) y)
|
||||
(Rsh8x(64|32|16|8) x y) && shiftIsBounded(v) -> (SRAW (MOVBreg x) y)
|
||||
(Lsh64x(64|32|16|8) x y) && shiftIsBounded(v) => (SLD x y)
|
||||
(Lsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SLW x y)
|
||||
(Lsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SLW x y)
|
||||
(Lsh8x(64|32|16|8) x y) && shiftIsBounded(v) => (SLW x y)
|
||||
(Rsh64Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRD x y)
|
||||
(Rsh32Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRW x y)
|
||||
(Rsh16Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRW (MOVHZreg x) y)
|
||||
(Rsh8Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRW (MOVBZreg x) y)
|
||||
(Rsh64x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAD x y)
|
||||
(Rsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAW x y)
|
||||
(Rsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAW (MOVHreg x) y)
|
||||
(Rsh8x(64|32|16|8) x y) && shiftIsBounded(v) => (SRAW (MOVBreg x) y)
|
||||
|
||||
// Unsigned shifts need to return 0 if shift amount is >= width of shifted value.
|
||||
// result = shift >= 64 ? 0 : arg << shift
|
||||
(Lsh(64|32|16|8)x64 <t> x y) -> (LOCGR {s390x.GreaterOrEqual} <t> (SL(D|W|W|W) <t> x y) (MOVDconst [0]) (CMPUconst y [64]))
|
||||
(Lsh(64|32|16|8)x32 <t> x y) -> (LOCGR {s390x.GreaterOrEqual} <t> (SL(D|W|W|W) <t> x y) (MOVDconst [0]) (CMPWUconst y [64]))
|
||||
(Lsh(64|32|16|8)x16 <t> x y) -> (LOCGR {s390x.GreaterOrEqual} <t> (SL(D|W|W|W) <t> x y) (MOVDconst [0]) (CMPWUconst (MOVHZreg y) [64]))
|
||||
(Lsh(64|32|16|8)x8 <t> x y) -> (LOCGR {s390x.GreaterOrEqual} <t> (SL(D|W|W|W) <t> x y) (MOVDconst [0]) (CMPWUconst (MOVBZreg y) [64]))
|
||||
(Lsh(64|32|16|8)x64 <t> x y) => (LOCGR {s390x.GreaterOrEqual} <t> (SL(D|W|W|W) <t> x y) (MOVDconst [0]) (CMPUconst y [64]))
|
||||
(Lsh(64|32|16|8)x32 <t> x y) => (LOCGR {s390x.GreaterOrEqual} <t> (SL(D|W|W|W) <t> x y) (MOVDconst [0]) (CMPWUconst y [64]))
|
||||
(Lsh(64|32|16|8)x16 <t> x y) => (LOCGR {s390x.GreaterOrEqual} <t> (SL(D|W|W|W) <t> x y) (MOVDconst [0]) (CMPWUconst (MOVHZreg y) [64]))
|
||||
(Lsh(64|32|16|8)x8 <t> x y) => (LOCGR {s390x.GreaterOrEqual} <t> (SL(D|W|W|W) <t> x y) (MOVDconst [0]) (CMPWUconst (MOVBZreg y) [64]))
|
||||
|
||||
(Rsh(64|32)Ux64 <t> x y) -> (LOCGR {s390x.GreaterOrEqual} <t> (SR(D|W) <t> x y) (MOVDconst [0]) (CMPUconst y [64]))
|
||||
(Rsh(64|32)Ux32 <t> x y) -> (LOCGR {s390x.GreaterOrEqual} <t> (SR(D|W) <t> x y) (MOVDconst [0]) (CMPWUconst y [64]))
|
||||
(Rsh(64|32)Ux16 <t> x y) -> (LOCGR {s390x.GreaterOrEqual} <t> (SR(D|W) <t> x y) (MOVDconst [0]) (CMPWUconst (MOVHZreg y) [64]))
|
||||
(Rsh(64|32)Ux8 <t> x y) -> (LOCGR {s390x.GreaterOrEqual} <t> (SR(D|W) <t> x y) (MOVDconst [0]) (CMPWUconst (MOVBZreg y) [64]))
|
||||
(Rsh(64|32)Ux64 <t> x y) => (LOCGR {s390x.GreaterOrEqual} <t> (SR(D|W) <t> x y) (MOVDconst [0]) (CMPUconst y [64]))
|
||||
(Rsh(64|32)Ux32 <t> x y) => (LOCGR {s390x.GreaterOrEqual} <t> (SR(D|W) <t> x y) (MOVDconst [0]) (CMPWUconst y [64]))
|
||||
(Rsh(64|32)Ux16 <t> x y) => (LOCGR {s390x.GreaterOrEqual} <t> (SR(D|W) <t> x y) (MOVDconst [0]) (CMPWUconst (MOVHZreg y) [64]))
|
||||
(Rsh(64|32)Ux8 <t> x y) => (LOCGR {s390x.GreaterOrEqual} <t> (SR(D|W) <t> x y) (MOVDconst [0]) (CMPWUconst (MOVBZreg y) [64]))
|
||||
|
||||
(Rsh(16|8)Ux64 <t> x y) -> (LOCGR {s390x.GreaterOrEqual} <t> (SRW <t> (MOV(H|B)Zreg x) y) (MOVDconst [0]) (CMPUconst y [64]))
|
||||
(Rsh(16|8)Ux32 <t> x y) -> (LOCGR {s390x.GreaterOrEqual} <t> (SRW <t> (MOV(H|B)Zreg x) y) (MOVDconst [0]) (CMPWUconst y [64]))
|
||||
(Rsh(16|8)Ux16 <t> x y) -> (LOCGR {s390x.GreaterOrEqual} <t> (SRW <t> (MOV(H|B)Zreg x) y) (MOVDconst [0]) (CMPWUconst (MOVHZreg y) [64]))
|
||||
(Rsh(16|8)Ux8 <t> x y) -> (LOCGR {s390x.GreaterOrEqual} <t> (SRW <t> (MOV(H|B)Zreg x) y) (MOVDconst [0]) (CMPWUconst (MOVBZreg y) [64]))
|
||||
(Rsh(16|8)Ux64 <t> x y) => (LOCGR {s390x.GreaterOrEqual} <t> (SRW <t> (MOV(H|B)Zreg x) y) (MOVDconst [0]) (CMPUconst y [64]))
|
||||
(Rsh(16|8)Ux32 <t> x y) => (LOCGR {s390x.GreaterOrEqual} <t> (SRW <t> (MOV(H|B)Zreg x) y) (MOVDconst [0]) (CMPWUconst y [64]))
|
||||
(Rsh(16|8)Ux16 <t> x y) => (LOCGR {s390x.GreaterOrEqual} <t> (SRW <t> (MOV(H|B)Zreg x) y) (MOVDconst [0]) (CMPWUconst (MOVHZreg y) [64]))
|
||||
(Rsh(16|8)Ux8 <t> x y) => (LOCGR {s390x.GreaterOrEqual} <t> (SRW <t> (MOV(H|B)Zreg x) y) (MOVDconst [0]) (CMPWUconst (MOVBZreg y) [64]))
|
||||
|
||||
// Signed right shift needs to return 0/-1 if shift amount is >= width of shifted value.
|
||||
// We implement this by setting the shift value to 63 (all ones) if the shift value is more than 63.
|
||||
// result = arg >> (shift >= 64 ? 63 : shift)
|
||||
(Rsh(64|32)x64 x y) -> (SRA(D|W) x (LOCGR {s390x.GreaterOrEqual} <y.Type> y (MOVDconst <y.Type> [63]) (CMPUconst y [64])))
|
||||
(Rsh(64|32)x32 x y) -> (SRA(D|W) x (LOCGR {s390x.GreaterOrEqual} <y.Type> y (MOVDconst <y.Type> [63]) (CMPWUconst y [64])))
|
||||
(Rsh(64|32)x16 x y) -> (SRA(D|W) x (LOCGR {s390x.GreaterOrEqual} <y.Type> y (MOVDconst <y.Type> [63]) (CMPWUconst (MOVHZreg y) [64])))
|
||||
(Rsh(64|32)x8 x y) -> (SRA(D|W) x (LOCGR {s390x.GreaterOrEqual} <y.Type> y (MOVDconst <y.Type> [63]) (CMPWUconst (MOVBZreg y) [64])))
|
||||
(Rsh(64|32)x64 x y) => (SRA(D|W) x (LOCGR {s390x.GreaterOrEqual} <y.Type> y (MOVDconst <y.Type> [63]) (CMPUconst y [64])))
|
||||
(Rsh(64|32)x32 x y) => (SRA(D|W) x (LOCGR {s390x.GreaterOrEqual} <y.Type> y (MOVDconst <y.Type> [63]) (CMPWUconst y [64])))
|
||||
(Rsh(64|32)x16 x y) => (SRA(D|W) x (LOCGR {s390x.GreaterOrEqual} <y.Type> y (MOVDconst <y.Type> [63]) (CMPWUconst (MOVHZreg y) [64])))
|
||||
(Rsh(64|32)x8 x y) => (SRA(D|W) x (LOCGR {s390x.GreaterOrEqual} <y.Type> y (MOVDconst <y.Type> [63]) (CMPWUconst (MOVBZreg y) [64])))
|
||||
|
||||
(Rsh(16|8)x64 x y) -> (SRAW (MOV(H|B)reg x) (LOCGR {s390x.GreaterOrEqual} <y.Type> y (MOVDconst <y.Type> [63]) (CMPUconst y [64])))
|
||||
(Rsh(16|8)x32 x y) -> (SRAW (MOV(H|B)reg x) (LOCGR {s390x.GreaterOrEqual} <y.Type> y (MOVDconst <y.Type> [63]) (CMPWUconst y [64])))
|
||||
(Rsh(16|8)x16 x y) -> (SRAW (MOV(H|B)reg x) (LOCGR {s390x.GreaterOrEqual} <y.Type> y (MOVDconst <y.Type> [63]) (CMPWUconst (MOVHZreg y) [64])))
|
||||
(Rsh(16|8)x8 x y) -> (SRAW (MOV(H|B)reg x) (LOCGR {s390x.GreaterOrEqual} <y.Type> y (MOVDconst <y.Type> [63]) (CMPWUconst (MOVBZreg y) [64])))
|
||||
(Rsh(16|8)x64 x y) => (SRAW (MOV(H|B)reg x) (LOCGR {s390x.GreaterOrEqual} <y.Type> y (MOVDconst <y.Type> [63]) (CMPUconst y [64])))
|
||||
(Rsh(16|8)x32 x y) => (SRAW (MOV(H|B)reg x) (LOCGR {s390x.GreaterOrEqual} <y.Type> y (MOVDconst <y.Type> [63]) (CMPWUconst y [64])))
|
||||
(Rsh(16|8)x16 x y) => (SRAW (MOV(H|B)reg x) (LOCGR {s390x.GreaterOrEqual} <y.Type> y (MOVDconst <y.Type> [63]) (CMPWUconst (MOVHZreg y) [64])))
|
||||
(Rsh(16|8)x8 x y) => (SRAW (MOV(H|B)reg x) (LOCGR {s390x.GreaterOrEqual} <y.Type> y (MOVDconst <y.Type> [63]) (CMPWUconst (MOVBZreg y) [64])))
|
||||
|
||||
// Lowering rotates
|
||||
(RotateLeft8 <t> x (MOVDconst [c])) -> (Or8 (Lsh8x64 <t> x (MOVDconst [c&7])) (Rsh8Ux64 <t> x (MOVDconst [-c&7])))
|
||||
(RotateLeft16 <t> x (MOVDconst [c])) -> (Or16 (Lsh16x64 <t> x (MOVDconst [c&15])) (Rsh16Ux64 <t> x (MOVDconst [-c&15])))
|
||||
(RotateLeft32 ...) -> (RLL ...)
|
||||
(RotateLeft64 ...) -> (RLLG ...)
|
||||
(RotateLeft8 <t> x (MOVDconst [c])) => (Or8 (Lsh8x64 <t> x (MOVDconst [c&7])) (Rsh8Ux64 <t> x (MOVDconst [-c&7])))
|
||||
(RotateLeft16 <t> x (MOVDconst [c])) => (Or16 (Lsh16x64 <t> x (MOVDconst [c&15])) (Rsh16Ux64 <t> x (MOVDconst [-c&15])))
|
||||
(RotateLeft32 ...) => (RLL ...)
|
||||
(RotateLeft64 ...) => (RLLG ...)
|
||||
|
||||
// Lowering comparisons
|
||||
(Less64 x y) -> (LOCGR {s390x.Less} (MOVDconst [0]) (MOVDconst [1]) (CMP x y))
|
||||
(Less32 x y) -> (LOCGR {s390x.Less} (MOVDconst [0]) (MOVDconst [1]) (CMPW x y))
|
||||
(Less(16|8) x y) -> (LOCGR {s390x.Less} (MOVDconst [0]) (MOVDconst [1]) (CMPW (MOV(H|B)reg x) (MOV(H|B)reg y)))
|
||||
(Less64U x y) -> (LOCGR {s390x.Less} (MOVDconst [0]) (MOVDconst [1]) (CMPU x y))
|
||||
(Less32U x y) -> (LOCGR {s390x.Less} (MOVDconst [0]) (MOVDconst [1]) (CMPWU x y))
|
||||
(Less(16|8)U x y) -> (LOCGR {s390x.Less} (MOVDconst [0]) (MOVDconst [1]) (CMPWU (MOV(H|B)Zreg x) (MOV(H|B)Zreg y)))
|
||||
(Less64F x y) -> (LOCGR {s390x.Less} (MOVDconst [0]) (MOVDconst [1]) (FCMP x y))
|
||||
(Less32F x y) -> (LOCGR {s390x.Less} (MOVDconst [0]) (MOVDconst [1]) (FCMPS x y))
|
||||
(Less64 x y) => (LOCGR {s390x.Less} (MOVDconst [0]) (MOVDconst [1]) (CMP x y))
|
||||
(Less32 x y) => (LOCGR {s390x.Less} (MOVDconst [0]) (MOVDconst [1]) (CMPW x y))
|
||||
(Less(16|8) x y) => (LOCGR {s390x.Less} (MOVDconst [0]) (MOVDconst [1]) (CMPW (MOV(H|B)reg x) (MOV(H|B)reg y)))
|
||||
(Less64U x y) => (LOCGR {s390x.Less} (MOVDconst [0]) (MOVDconst [1]) (CMPU x y))
|
||||
(Less32U x y) => (LOCGR {s390x.Less} (MOVDconst [0]) (MOVDconst [1]) (CMPWU x y))
|
||||
(Less(16|8)U x y) => (LOCGR {s390x.Less} (MOVDconst [0]) (MOVDconst [1]) (CMPWU (MOV(H|B)Zreg x) (MOV(H|B)Zreg y)))
|
||||
(Less64F x y) => (LOCGR {s390x.Less} (MOVDconst [0]) (MOVDconst [1]) (FCMP x y))
|
||||
(Less32F x y) => (LOCGR {s390x.Less} (MOVDconst [0]) (MOVDconst [1]) (FCMPS x y))
|
||||
|
||||
(Leq64 x y) -> (LOCGR {s390x.LessOrEqual} (MOVDconst [0]) (MOVDconst [1]) (CMP x y))
|
||||
(Leq32 x y) -> (LOCGR {s390x.LessOrEqual} (MOVDconst [0]) (MOVDconst [1]) (CMPW x y))
|
||||
(Leq(16|8) x y) -> (LOCGR {s390x.LessOrEqual} (MOVDconst [0]) (MOVDconst [1]) (CMPW (MOV(H|B)reg x) (MOV(H|B)reg y)))
|
||||
(Leq64U x y) -> (LOCGR {s390x.LessOrEqual} (MOVDconst [0]) (MOVDconst [1]) (CMPU x y))
|
||||
(Leq32U x y) -> (LOCGR {s390x.LessOrEqual} (MOVDconst [0]) (MOVDconst [1]) (CMPWU x y))
|
||||
(Leq(16|8)U x y) -> (LOCGR {s390x.LessOrEqual} (MOVDconst [0]) (MOVDconst [1]) (CMPWU (MOV(H|B)Zreg x) (MOV(H|B)Zreg y)))
|
||||
(Leq64F x y) -> (LOCGR {s390x.LessOrEqual} (MOVDconst [0]) (MOVDconst [1]) (FCMP x y))
|
||||
(Leq32F x y) -> (LOCGR {s390x.LessOrEqual} (MOVDconst [0]) (MOVDconst [1]) (FCMPS x y))
|
||||
(Leq64 x y) => (LOCGR {s390x.LessOrEqual} (MOVDconst [0]) (MOVDconst [1]) (CMP x y))
|
||||
(Leq32 x y) => (LOCGR {s390x.LessOrEqual} (MOVDconst [0]) (MOVDconst [1]) (CMPW x y))
|
||||
(Leq(16|8) x y) => (LOCGR {s390x.LessOrEqual} (MOVDconst [0]) (MOVDconst [1]) (CMPW (MOV(H|B)reg x) (MOV(H|B)reg y)))
|
||||
(Leq64U x y) => (LOCGR {s390x.LessOrEqual} (MOVDconst [0]) (MOVDconst [1]) (CMPU x y))
|
||||
(Leq32U x y) => (LOCGR {s390x.LessOrEqual} (MOVDconst [0]) (MOVDconst [1]) (CMPWU x y))
|
||||
(Leq(16|8)U x y) => (LOCGR {s390x.LessOrEqual} (MOVDconst [0]) (MOVDconst [1]) (CMPWU (MOV(H|B)Zreg x) (MOV(H|B)Zreg y)))
|
||||
(Leq64F x y) => (LOCGR {s390x.LessOrEqual} (MOVDconst [0]) (MOVDconst [1]) (FCMP x y))
|
||||
(Leq32F x y) => (LOCGR {s390x.LessOrEqual} (MOVDconst [0]) (MOVDconst [1]) (FCMPS x y))
|
||||
|
||||
(Eq(64|Ptr) x y) -> (LOCGR {s390x.Equal} (MOVDconst [0]) (MOVDconst [1]) (CMP x y))
|
||||
(Eq32 x y) -> (LOCGR {s390x.Equal} (MOVDconst [0]) (MOVDconst [1]) (CMPW x y))
|
||||
(Eq(16|8|B) x y) -> (LOCGR {s390x.Equal} (MOVDconst [0]) (MOVDconst [1]) (CMPW (MOV(H|B|B)reg x) (MOV(H|B|B)reg y)))
|
||||
(Eq64F x y) -> (LOCGR {s390x.Equal} (MOVDconst [0]) (MOVDconst [1]) (FCMP x y))
|
||||
(Eq32F x y) -> (LOCGR {s390x.Equal} (MOVDconst [0]) (MOVDconst [1]) (FCMPS x y))
|
||||
(Eq(64|Ptr) x y) => (LOCGR {s390x.Equal} (MOVDconst [0]) (MOVDconst [1]) (CMP x y))
|
||||
(Eq32 x y) => (LOCGR {s390x.Equal} (MOVDconst [0]) (MOVDconst [1]) (CMPW x y))
|
||||
(Eq(16|8|B) x y) => (LOCGR {s390x.Equal} (MOVDconst [0]) (MOVDconst [1]) (CMPW (MOV(H|B|B)reg x) (MOV(H|B|B)reg y)))
|
||||
(Eq64F x y) => (LOCGR {s390x.Equal} (MOVDconst [0]) (MOVDconst [1]) (FCMP x y))
|
||||
(Eq32F x y) => (LOCGR {s390x.Equal} (MOVDconst [0]) (MOVDconst [1]) (FCMPS x y))
|
||||
|
||||
(Neq(64|Ptr) x y) -> (LOCGR {s390x.NotEqual} (MOVDconst [0]) (MOVDconst [1]) (CMP x y))
|
||||
(Neq32 x y) -> (LOCGR {s390x.NotEqual} (MOVDconst [0]) (MOVDconst [1]) (CMPW x y))
|
||||
(Neq(16|8|B) x y) -> (LOCGR {s390x.NotEqual} (MOVDconst [0]) (MOVDconst [1]) (CMPW (MOV(H|B|B)reg x) (MOV(H|B|B)reg y)))
|
||||
(Neq64F x y) -> (LOCGR {s390x.NotEqual} (MOVDconst [0]) (MOVDconst [1]) (FCMP x y))
|
||||
(Neq32F x y) -> (LOCGR {s390x.NotEqual} (MOVDconst [0]) (MOVDconst [1]) (FCMPS x y))
|
||||
(Neq(64|Ptr) x y) => (LOCGR {s390x.NotEqual} (MOVDconst [0]) (MOVDconst [1]) (CMP x y))
|
||||
(Neq32 x y) => (LOCGR {s390x.NotEqual} (MOVDconst [0]) (MOVDconst [1]) (CMPW x y))
|
||||
(Neq(16|8|B) x y) => (LOCGR {s390x.NotEqual} (MOVDconst [0]) (MOVDconst [1]) (CMPW (MOV(H|B|B)reg x) (MOV(H|B|B)reg y)))
|
||||
(Neq64F x y) => (LOCGR {s390x.NotEqual} (MOVDconst [0]) (MOVDconst [1]) (FCMP x y))
|
||||
(Neq32F x y) => (LOCGR {s390x.NotEqual} (MOVDconst [0]) (MOVDconst [1]) (FCMPS x y))
|
||||
|
||||
// Lowering loads
|
||||
(Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) -> (MOVDload ptr mem)
|
||||
(Load <t> ptr mem) && is32BitInt(t) && isSigned(t) -> (MOVWload ptr mem)
|
||||
(Load <t> ptr mem) && is32BitInt(t) && !isSigned(t) -> (MOVWZload ptr mem)
|
||||
(Load <t> ptr mem) && is16BitInt(t) && isSigned(t) -> (MOVHload ptr mem)
|
||||
(Load <t> ptr mem) && is16BitInt(t) && !isSigned(t) -> (MOVHZload ptr mem)
|
||||
(Load <t> ptr mem) && is8BitInt(t) && isSigned(t) -> (MOVBload ptr mem)
|
||||
(Load <t> ptr mem) && (t.IsBoolean() || (is8BitInt(t) && !isSigned(t))) -> (MOVBZload ptr mem)
|
||||
(Load <t> ptr mem) && is32BitFloat(t) -> (FMOVSload ptr mem)
|
||||
(Load <t> ptr mem) && is64BitFloat(t) -> (FMOVDload ptr mem)
|
||||
(Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVDload ptr mem)
|
||||
(Load <t> ptr mem) && is32BitInt(t) && isSigned(t) => (MOVWload ptr mem)
|
||||
(Load <t> ptr mem) && is32BitInt(t) && !isSigned(t) => (MOVWZload ptr mem)
|
||||
(Load <t> ptr mem) && is16BitInt(t) && isSigned(t) => (MOVHload ptr mem)
|
||||
(Load <t> ptr mem) && is16BitInt(t) && !isSigned(t) => (MOVHZload ptr mem)
|
||||
(Load <t> ptr mem) && is8BitInt(t) && isSigned(t) => (MOVBload ptr mem)
|
||||
(Load <t> ptr mem) && (t.IsBoolean() || (is8BitInt(t) && !isSigned(t))) => (MOVBZload ptr mem)
|
||||
(Load <t> ptr mem) && is32BitFloat(t) => (FMOVSload ptr mem)
|
||||
(Load <t> ptr mem) && is64BitFloat(t) => (FMOVDload ptr mem)
|
||||
|
||||
// Lowering stores
|
||||
// These more-specific FP versions of Store pattern should come first.
|
||||
@ -353,28 +353,28 @@
|
||||
// Lowering moves
|
||||
|
||||
// Load and store for small copies.
|
||||
(Move [0] _ _ mem) -> mem
|
||||
(Move [1] dst src mem) -> (MOVBstore dst (MOVBZload src mem) mem)
|
||||
(Move [2] dst src mem) -> (MOVHstore dst (MOVHZload src mem) mem)
|
||||
(Move [4] dst src mem) -> (MOVWstore dst (MOVWZload src mem) mem)
|
||||
(Move [8] dst src mem) -> (MOVDstore dst (MOVDload src mem) mem)
|
||||
(Move [16] dst src mem) ->
|
||||
(Move [0] _ _ mem) => mem
|
||||
(Move [1] dst src mem) => (MOVBstore dst (MOVBZload src mem) mem)
|
||||
(Move [2] dst src mem) => (MOVHstore dst (MOVHZload src mem) mem)
|
||||
(Move [4] dst src mem) => (MOVWstore dst (MOVWZload src mem) mem)
|
||||
(Move [8] dst src mem) => (MOVDstore dst (MOVDload src mem) mem)
|
||||
(Move [16] dst src mem) =>
|
||||
(MOVDstore [8] dst (MOVDload [8] src mem)
|
||||
(MOVDstore dst (MOVDload src mem) mem))
|
||||
(Move [24] dst src mem) ->
|
||||
(Move [24] dst src mem) =>
|
||||
(MOVDstore [16] dst (MOVDload [16] src mem)
|
||||
(MOVDstore [8] dst (MOVDload [8] src mem)
|
||||
(MOVDstore dst (MOVDload src mem) mem)))
|
||||
(Move [3] dst src mem) ->
|
||||
(Move [3] dst src mem) =>
|
||||
(MOVBstore [2] dst (MOVBZload [2] src mem)
|
||||
(MOVHstore dst (MOVHZload src mem) mem))
|
||||
(Move [5] dst src mem) ->
|
||||
(Move [5] dst src mem) =>
|
||||
(MOVBstore [4] dst (MOVBZload [4] src mem)
|
||||
(MOVWstore dst (MOVWZload src mem) mem))
|
||||
(Move [6] dst src mem) ->
|
||||
(Move [6] dst src mem) =>
|
||||
(MOVHstore [4] dst (MOVHZload [4] src mem)
|
||||
(MOVWstore dst (MOVWZload src mem) mem))
|
||||
(Move [7] dst src mem) ->
|
||||
(Move [7] dst src mem) =>
|
||||
(MOVBstore [6] dst (MOVBZload [6] src mem)
|
||||
(MOVHstore [4] dst (MOVHZload [4] src mem)
|
||||
(MOVWstore dst (MOVWZload src mem) mem)))
|
||||
@ -394,11 +394,11 @@
|
||||
(LoweredMove [s%256] dst src (ADD <src.Type> src (MOVDconst [(s/256)*256])) mem)
|
||||
|
||||
// Lowering Zero instructions
|
||||
(Zero [0] _ mem) -> mem
|
||||
(Zero [1] destptr mem) -> (MOVBstoreconst [0] destptr mem)
|
||||
(Zero [2] destptr mem) -> (MOVHstoreconst [0] destptr mem)
|
||||
(Zero [4] destptr mem) -> (MOVWstoreconst [0] destptr mem)
|
||||
(Zero [8] destptr mem) -> (MOVDstoreconst [0] destptr mem)
|
||||
(Zero [0] _ mem) => mem
|
||||
(Zero [1] destptr mem) => (MOVBstoreconst [0] destptr mem)
|
||||
(Zero [2] destptr mem) => (MOVHstoreconst [0] destptr mem)
|
||||
(Zero [4] destptr mem) => (MOVWstoreconst [0] destptr mem)
|
||||
(Zero [8] destptr mem) => (MOVDstoreconst [0] destptr mem)
|
||||
(Zero [3] destptr mem) =>
|
||||
(MOVBstoreconst [makeValAndOff32(0,2)] destptr
|
||||
(MOVHstoreconst [0] destptr mem))
|
||||
@ -421,37 +421,37 @@
|
||||
|
||||
// Lowering constants
|
||||
(Const(64|32|16|8) ...) -> (MOVDconst ...)
|
||||
(Const(32|64)F ...) -> (FMOV(S|D)const ...)
|
||||
(ConstNil) -> (MOVDconst [0])
|
||||
(Const(32|64)F ...) => (FMOV(S|D)const ...)
|
||||
(ConstNil) => (MOVDconst [0])
|
||||
(ConstBool ...) -> (MOVDconst ...)
|
||||
|
||||
// Lowering calls
|
||||
(StaticCall ...) -> (CALLstatic ...)
|
||||
(ClosureCall ...) -> (CALLclosure ...)
|
||||
(InterCall ...) -> (CALLinter ...)
|
||||
(StaticCall ...) => (CALLstatic ...)
|
||||
(ClosureCall ...) => (CALLclosure ...)
|
||||
(InterCall ...) => (CALLinter ...)
|
||||
|
||||
// Miscellaneous
|
||||
(IsNonNil p) -> (LOCGR {s390x.NotEqual} (MOVDconst [0]) (MOVDconst [1]) (CMPconst p [0]))
|
||||
(IsInBounds idx len) -> (LOCGR {s390x.Less} (MOVDconst [0]) (MOVDconst [1]) (CMPU idx len))
|
||||
(IsSliceInBounds idx len) -> (LOCGR {s390x.LessOrEqual} (MOVDconst [0]) (MOVDconst [1]) (CMPU idx len))
|
||||
(NilCheck ...) -> (LoweredNilCheck ...)
|
||||
(GetG ...) -> (LoweredGetG ...)
|
||||
(GetClosurePtr ...) -> (LoweredGetClosurePtr ...)
|
||||
(GetCallerSP ...) -> (LoweredGetCallerSP ...)
|
||||
(GetCallerPC ...) -> (LoweredGetCallerPC ...)
|
||||
(IsNonNil p) => (LOCGR {s390x.NotEqual} (MOVDconst [0]) (MOVDconst [1]) (CMPconst p [0]))
|
||||
(IsInBounds idx len) => (LOCGR {s390x.Less} (MOVDconst [0]) (MOVDconst [1]) (CMPU idx len))
|
||||
(IsSliceInBounds idx len) => (LOCGR {s390x.LessOrEqual} (MOVDconst [0]) (MOVDconst [1]) (CMPU idx len))
|
||||
(NilCheck ...) => (LoweredNilCheck ...)
|
||||
(GetG ...) => (LoweredGetG ...)
|
||||
(GetClosurePtr ...) => (LoweredGetClosurePtr ...)
|
||||
(GetCallerSP ...) => (LoweredGetCallerSP ...)
|
||||
(GetCallerPC ...) => (LoweredGetCallerPC ...)
|
||||
(Addr ...) -> (MOVDaddr ...)
|
||||
(LocalAddr {sym} base _) -> (MOVDaddr {sym} base)
|
||||
(ITab (Load ptr mem)) -> (MOVDload ptr mem)
|
||||
(ITab (Load ptr mem)) => (MOVDload ptr mem)
|
||||
|
||||
// block rewrites
|
||||
(If cond yes no) -> (CLIJ {s390x.LessOrGreater} (MOVBZreg <typ.Bool> cond) [0] yes no)
|
||||
(If cond yes no) => (CLIJ {s390x.LessOrGreater} (MOVBZreg <typ.Bool> cond) [0] yes no)
|
||||
|
||||
// Write barrier.
|
||||
(WB ...) -> (LoweredWB ...)
|
||||
(WB ...) => (LoweredWB ...)
|
||||
|
||||
(PanicBounds [kind] x y mem) && boundsABI(kind) == 0 -> (LoweredPanicBoundsA [kind] x y mem)
|
||||
(PanicBounds [kind] x y mem) && boundsABI(kind) == 1 -> (LoweredPanicBoundsB [kind] x y mem)
|
||||
(PanicBounds [kind] x y mem) && boundsABI(kind) == 2 -> (LoweredPanicBoundsC [kind] x y mem)
|
||||
(PanicBounds [kind] x y mem) && boundsABI(kind) == 0 => (LoweredPanicBoundsA [kind] x y mem)
|
||||
(PanicBounds [kind] x y mem) && boundsABI(kind) == 1 => (LoweredPanicBoundsB [kind] x y mem)
|
||||
(PanicBounds [kind] x y mem) && boundsABI(kind) == 2 => (LoweredPanicBoundsC [kind] x y mem)
|
||||
|
||||
// ***************************
|
||||
// Above: lowering rules
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user