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https://github.com/golang/go
synced 2024-11-24 02:00:20 -07:00
[dev.ssa] cmd/compile: implement more 64-bit ops on 386
add/sub/mul, plus constant input variants. Change-Id: I1c8006727c4fdf73558da0e646e7d1fa130ed773 Reviewed-on: https://go-review.googlesource.com/25006 Reviewed-by: David Chase <drchase@google.com> Reviewed-by: Cherry Zhang <cherryyz@google.com>
This commit is contained in:
Keith Randall
parent
cf92e3845f
commit
aee8d8b9dd
@ -20,12 +20,17 @@
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(Sub32F x y) -> (SUBSS x y)
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(Sub64F x y) -> (SUBSD x y)
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(Sub32carry x y) -> (SUBLcarry x y)
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(Sub32withcarry x y c) -> (SBBL x y c)
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(Mul32 x y) -> (MULL x y)
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(Mul16 x y) -> (MULL x y)
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(Mul8 x y) -> (MULL x y)
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(Mul32F x y) -> (MULSS x y)
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(Mul64F x y) -> (MULSD x y)
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(Mul32uhilo x y) -> (MULLQU x y)
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(Div32F x y) -> (DIVSS x y)
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(Div64F x y) -> (DIVSD x y)
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@ -216,7 +221,7 @@
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(Neq32F x y) -> (SETNEF (UCOMISS x y))
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// Lowering loads
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(Load <t> ptr mem) && is32BitInt(t) -> (MOVLload ptr mem)
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(Load <t> ptr mem) && (is32BitInt(t) || isPtr(t)) -> (MOVLload ptr mem)
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(Load <t> ptr mem) && is16BitInt(t) -> (MOVWload ptr mem)
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(Load <t> ptr mem) && (t.IsBoolean() || is8BitInt(t)) -> (MOVBload ptr mem)
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(Load <t> ptr mem) && is32BitFloat(t) -> (MOVSSload ptr mem)
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@ -383,9 +388,15 @@
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// fold constants into instructions
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(ADDL x (MOVLconst [c])) -> (ADDLconst [c] x)
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(ADDL (MOVLconst [c]) x) -> (ADDLconst [c] x)
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(ADDLcarry x (MOVLconst [c])) -> (ADDLconstcarry [c] x)
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(ADDLcarry (MOVLconst [c]) x) -> (ADDLconstcarry [c] x)
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(ADCL x (MOVLconst [c]) f) -> (ADCLconst [c] x f)
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(ADCL (MOVLconst [c]) x f) -> (ADCLconst [c] x f)
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(SUBL x (MOVLconst [c])) -> (SUBLconst x [c])
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(SUBL (MOVLconst [c]) x) -> (NEGL (SUBLconst <v.Type> x [c]))
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(SUBLcarry x (MOVLconst [c])) -> (SUBLconstcarry [c] x)
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(SBBL x (MOVLconst [c]) f) -> (SBBLconst [c] x f)
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(MULL x (MOVLconst [c])) -> (MULLconst [c] x)
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(MULL (MOVLconst [c]) x) -> (MULLconst [c] x)
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@ -99,17 +99,20 @@ func init() {
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gp11nf = regInfo{inputs: []regMask{gpsp}, outputs: gponly} // nf: no flags clobbered
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gp11sb = regInfo{inputs: []regMask{gpspsb}, outputs: gponly}
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gp21 = regInfo{inputs: []regMask{gp, gp}, outputs: gponly, clobbers: flags}
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gp11carry = regInfo{inputs: []regMask{gp}, outputs: []regMask{flags, gp}}
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gp21carry = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{flags, gp}}
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gp1carry1 = regInfo{inputs: []regMask{gp, flags}, outputs: gponly}
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gp2carry1 = regInfo{inputs: []regMask{gp, gp, flags}, outputs: gponly}
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gp21sp = regInfo{inputs: []regMask{gpsp, gp}, outputs: gponly, clobbers: flags}
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gp21sb = regInfo{inputs: []regMask{gpspsb, gpsp}, outputs: gponly}
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gp21shift = regInfo{inputs: []regMask{gp, cx}, outputs: []regMask{gp}, clobbers: flags}
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gp11div = regInfo{inputs: []regMask{ax, gpsp &^ dx}, outputs: []regMask{ax},
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clobbers: dx | flags}
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gp11hmul = regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx},
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gp21hmul = regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx},
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clobbers: ax | flags}
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gp11mod = regInfo{inputs: []regMask{ax, gpsp &^ dx}, outputs: []regMask{dx},
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clobbers: ax | flags}
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gp21mul = regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx, ax}, clobbers: flags}
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gp2flags = regInfo{inputs: []regMask{gpsp, gpsp}, outputs: flagsonly}
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gp1flags = regInfo{inputs: []regMask{gpsp}, outputs: flagsonly}
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@ -174,20 +177,29 @@ func init() {
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{name: "ADDLconst", argLength: 1, reg: gp11sp, asm: "ADDL", aux: "Int32", typ: "UInt32"}, // arg0 + auxint
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{name: "ADDLcarry", argLength: 2, reg: gp21carry, asm: "ADDL", commutative: true, resultInArg0: true}, // arg0 + arg1, generates <carry,result> pair
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{name: "ADDLconstcarry", argLength: 1, reg: gp11carry, asm: "ADDL", aux: "Int32", resultInArg0: true}, // arg0 + auxint, generates <carry,result> pair
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{name: "ADCL", argLength: 3, reg: gp2carry1, asm: "ADCL", commutative: true, resultInArg0: true}, // arg0+arg1+carry(arg2), where arg2 is flags
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{name: "ADCLconst", argLength: 2, reg: gp1carry1, asm: "ADCL", aux: "Int32", resultInArg0: true}, // arg0+auxint+carry(arg1), where arg1 is flags
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{name: "SUBL", argLength: 2, reg: gp21, asm: "SUBL", resultInArg0: true}, // arg0 - arg1
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{name: "SUBLconst", argLength: 1, reg: gp11, asm: "SUBL", aux: "Int32", resultInArg0: true}, // arg0 - auxint
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{name: "SUBLcarry", argLength: 2, reg: gp21carry, asm: "SUBL", resultInArg0: true}, // arg0-arg1, generates <borrow,result> pair
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{name: "SUBLconstcarry", argLength: 1, reg: gp11carry, asm: "SUBL", aux: "Int32", resultInArg0: true}, // arg0-auxint, generates <borrow,result> pair
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{name: "SBBL", argLength: 3, reg: gp2carry1, asm: "SBBL", resultInArg0: true}, // arg0-arg1-borrow(arg2), where arg2 is flags
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{name: "SBBLconst", argLength: 2, reg: gp1carry1, asm: "SBBL", aux: "Int32", resultInArg0: true}, // arg0-auxint-borrow(arg1), where arg1 is flags
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{name: "MULL", argLength: 2, reg: gp21, asm: "IMULL", commutative: true, resultInArg0: true}, // arg0 * arg1
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{name: "MULLconst", argLength: 1, reg: gp11, asm: "IMULL", aux: "Int32", resultInArg0: true}, // arg0 * auxint
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{name: "HMULL", argLength: 2, reg: gp11hmul, asm: "IMULL"}, // (arg0 * arg1) >> width
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{name: "HMULW", argLength: 2, reg: gp11hmul, asm: "IMULW"}, // (arg0 * arg1) >> width
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{name: "HMULB", argLength: 2, reg: gp11hmul, asm: "IMULB"}, // (arg0 * arg1) >> width
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{name: "HMULLU", argLength: 2, reg: gp11hmul, asm: "MULL"}, // (arg0 * arg1) >> width
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{name: "HMULWU", argLength: 2, reg: gp11hmul, asm: "MULW"}, // (arg0 * arg1) >> width
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{name: "HMULBU", argLength: 2, reg: gp11hmul, asm: "MULB"}, // (arg0 * arg1) >> width
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{name: "HMULL", argLength: 2, reg: gp21hmul, asm: "IMULL"}, // (arg0 * arg1) >> width
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{name: "HMULLU", argLength: 2, reg: gp21hmul, asm: "MULL"}, // (arg0 * arg1) >> width
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{name: "HMULW", argLength: 2, reg: gp21hmul, asm: "IMULW"}, // (arg0 * arg1) >> width
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{name: "HMULB", argLength: 2, reg: gp21hmul, asm: "IMULB"}, // (arg0 * arg1) >> width
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{name: "HMULWU", argLength: 2, reg: gp21hmul, asm: "MULW"}, // (arg0 * arg1) >> width
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{name: "HMULBU", argLength: 2, reg: gp21hmul, asm: "MULB"}, // (arg0 * arg1) >> width
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{name: "MULLQU", argLength: 2, reg: gp21mul, asm: "MULL"}, // arg0 * arg1, high 32 in result[0], low 32 in result[1]
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{name: "DIVL", argLength: 2, reg: gp11div, asm: "IDIVL"}, // arg0 / arg1
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{name: "DIVW", argLength: 2, reg: gp11div, asm: "IDIVW"}, // arg0 / arg1
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@ -121,7 +121,7 @@ func init() {
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gp21shift = regInfo{inputs: []regMask{gp, cx}, outputs: []regMask{gp}, clobbers: flags}
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gp11div = regInfo{inputs: []regMask{ax, gpsp &^ dx}, outputs: []regMask{ax, dx},
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clobbers: flags}
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gp11hmul = regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx},
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gp21hmul = regInfo{inputs: []regMask{ax, gpsp}, outputs: []regMask{dx},
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clobbers: ax | flags}
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gp2flags = regInfo{inputs: []regMask{gpsp, gpsp}, outputs: flagsonly}
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@ -201,14 +201,14 @@ func init() {
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{name: "MULQconst", argLength: 1, reg: gp11, asm: "IMULQ", aux: "Int64", resultInArg0: true}, // arg0 * auxint
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{name: "MULLconst", argLength: 1, reg: gp11, asm: "IMULL", aux: "Int32", resultInArg0: true}, // arg0 * auxint
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{name: "HMULQ", argLength: 2, reg: gp11hmul, asm: "IMULQ"}, // (arg0 * arg1) >> width
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{name: "HMULL", argLength: 2, reg: gp11hmul, asm: "IMULL"}, // (arg0 * arg1) >> width
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{name: "HMULW", argLength: 2, reg: gp11hmul, asm: "IMULW"}, // (arg0 * arg1) >> width
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{name: "HMULB", argLength: 2, reg: gp11hmul, asm: "IMULB"}, // (arg0 * arg1) >> width
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{name: "HMULQU", argLength: 2, reg: gp11hmul, asm: "MULQ"}, // (arg0 * arg1) >> width
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{name: "HMULLU", argLength: 2, reg: gp11hmul, asm: "MULL"}, // (arg0 * arg1) >> width
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{name: "HMULWU", argLength: 2, reg: gp11hmul, asm: "MULW"}, // (arg0 * arg1) >> width
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{name: "HMULBU", argLength: 2, reg: gp11hmul, asm: "MULB"}, // (arg0 * arg1) >> width
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{name: "HMULQ", argLength: 2, reg: gp21hmul, asm: "IMULQ"}, // (arg0 * arg1) >> width
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{name: "HMULL", argLength: 2, reg: gp21hmul, asm: "IMULL"}, // (arg0 * arg1) >> width
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{name: "HMULW", argLength: 2, reg: gp21hmul, asm: "IMULW"}, // (arg0 * arg1) >> width
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{name: "HMULB", argLength: 2, reg: gp21hmul, asm: "IMULB"}, // (arg0 * arg1) >> width
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{name: "HMULQU", argLength: 2, reg: gp21hmul, asm: "MULQ"}, // (arg0 * arg1) >> width
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{name: "HMULLU", argLength: 2, reg: gp21hmul, asm: "MULL"}, // (arg0 * arg1) >> width
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{name: "HMULWU", argLength: 2, reg: gp21hmul, asm: "MULW"}, // (arg0 * arg1) >> width
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{name: "HMULBU", argLength: 2, reg: gp21hmul, asm: "MULB"}, // (arg0 * arg1) >> width
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{name: "AVGQU", argLength: 2, reg: gp21, commutative: true, resultInArg0: true}, // (arg0 + arg1) / 2 as unsigned, all 64 result bits
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@ -172,17 +172,24 @@ const (
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Op386ADDL
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Op386ADDLconst
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Op386ADDLcarry
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Op386ADDLconstcarry
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Op386ADCL
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Op386ADCLconst
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Op386SUBL
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Op386SUBLconst
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Op386SUBLcarry
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Op386SUBLconstcarry
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Op386SBBL
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Op386SBBLconst
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Op386MULL
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Op386MULLconst
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Op386HMULL
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Op386HMULLU
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Op386HMULW
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Op386HMULB
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Op386HMULLU
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Op386HMULWU
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Op386HMULBU
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Op386MULLQU
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Op386DIVL
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Op386DIVW
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Op386DIVLU
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@ -1503,6 +1510,22 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "ADDLconstcarry",
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auxType: auxInt32,
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argLen: 1,
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resultInArg0: true,
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asm: x86.AADDL,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 239}, // AX CX DX BX BP SI DI
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},
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outputs: []outputInfo{
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{0, 131072}, // FLAGS
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{1, 239}, // AX CX DX BX BP SI DI
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},
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},
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},
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{
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name: "ADCL",
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argLen: 3,
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@ -1520,6 +1543,22 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "ADCLconst",
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auxType: auxInt32,
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argLen: 2,
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resultInArg0: true,
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asm: x86.AADCL,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 131072}, // FLAGS
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{0, 239}, // AX CX DX BX BP SI DI
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},
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outputs: []outputInfo{
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{0, 239}, // AX CX DX BX BP SI DI
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},
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},
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},
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{
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name: "SUBL",
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argLen: 2,
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@ -1552,6 +1591,70 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "SUBLcarry",
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argLen: 2,
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resultInArg0: true,
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asm: x86.ASUBL,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 239}, // AX CX DX BX BP SI DI
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{1, 239}, // AX CX DX BX BP SI DI
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},
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outputs: []outputInfo{
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{0, 131072}, // FLAGS
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{1, 239}, // AX CX DX BX BP SI DI
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},
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},
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},
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{
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name: "SUBLconstcarry",
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auxType: auxInt32,
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argLen: 1,
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resultInArg0: true,
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asm: x86.ASUBL,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 239}, // AX CX DX BX BP SI DI
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},
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outputs: []outputInfo{
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{0, 131072}, // FLAGS
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{1, 239}, // AX CX DX BX BP SI DI
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},
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},
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},
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{
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name: "SBBL",
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argLen: 3,
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resultInArg0: true,
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asm: x86.ASBBL,
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reg: regInfo{
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inputs: []inputInfo{
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{2, 131072}, // FLAGS
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{0, 239}, // AX CX DX BX BP SI DI
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{1, 239}, // AX CX DX BX BP SI DI
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},
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outputs: []outputInfo{
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{0, 239}, // AX CX DX BX BP SI DI
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},
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},
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},
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{
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name: "SBBLconst",
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auxType: auxInt32,
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argLen: 2,
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resultInArg0: true,
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asm: x86.ASBBL,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 131072}, // FLAGS
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{0, 239}, // AX CX DX BX BP SI DI
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},
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outputs: []outputInfo{
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{0, 239}, // AX CX DX BX BP SI DI
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},
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},
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},
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{
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name: "MULL",
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argLen: 2,
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@ -1600,6 +1703,21 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "HMULLU",
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argLen: 2,
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asm: x86.AMULL,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1}, // AX
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{1, 255}, // AX CX DX BX SP BP SI DI
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},
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clobbers: 131073, // AX FLAGS
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outputs: []outputInfo{
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{0, 4}, // DX
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},
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},
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},
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{
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name: "HMULW",
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argLen: 2,
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@ -1630,21 +1748,6 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "HMULLU",
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argLen: 2,
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asm: x86.AMULL,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1}, // AX
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{1, 255}, // AX CX DX BX SP BP SI DI
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},
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clobbers: 131073, // AX FLAGS
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outputs: []outputInfo{
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{0, 4}, // DX
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},
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},
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},
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{
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name: "HMULWU",
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argLen: 2,
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@ -1675,6 +1778,22 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "MULLQU",
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argLen: 2,
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asm: x86.AMULL,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1}, // AX
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{1, 255}, // AX CX DX BX SP BP SI DI
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},
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clobbers: 131072, // FLAGS
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outputs: []outputInfo{
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{0, 4}, // DX
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{1, 1}, // AX
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},
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},
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},
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{
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name: "DIVL",
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argLen: 2,
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@ -8,8 +8,12 @@ import "math"
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var _ = math.MinInt8 // in case not otherwise used
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func rewriteValue386(v *Value, config *Config) bool {
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switch v.Op {
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case Op386ADCL:
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return rewriteValue386_Op386ADCL(v, config)
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case Op386ADDL:
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return rewriteValue386_Op386ADDL(v, config)
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case Op386ADDLcarry:
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return rewriteValue386_Op386ADDLcarry(v, config)
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case Op386ADDLconst:
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return rewriteValue386_Op386ADDLconst(v, config)
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case Op386ANDL:
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@ -362,6 +366,8 @@ func rewriteValue386(v *Value, config *Config) bool {
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return rewriteValue386_OpMul32(v, config)
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case OpMul32F:
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return rewriteValue386_OpMul32F(v, config)
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case OpMul32uhilo:
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return rewriteValue386_OpMul32uhilo(v, config)
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case OpMul64F:
|
||||
return rewriteValue386_OpMul64F(v, config)
|
||||
case OpMul8:
|
||||
@ -466,6 +472,8 @@ func rewriteValue386(v *Value, config *Config) bool {
|
||||
return rewriteValue386_Op386SARW(v, config)
|
||||
case Op386SARWconst:
|
||||
return rewriteValue386_Op386SARWconst(v, config)
|
||||
case Op386SBBL:
|
||||
return rewriteValue386_Op386SBBL(v, config)
|
||||
case Op386SBBLcarrymask:
|
||||
return rewriteValue386_Op386SBBLcarrymask(v, config)
|
||||
case Op386SETA:
|
||||
@ -498,6 +506,8 @@ func rewriteValue386(v *Value, config *Config) bool {
|
||||
return rewriteValue386_Op386SHRW(v, config)
|
||||
case Op386SUBL:
|
||||
return rewriteValue386_Op386SUBL(v, config)
|
||||
case Op386SUBLcarry:
|
||||
return rewriteValue386_Op386SUBLcarry(v, config)
|
||||
case Op386SUBLconst:
|
||||
return rewriteValue386_Op386SUBLconst(v, config)
|
||||
case OpSignExt16to32:
|
||||
@ -518,6 +528,10 @@ func rewriteValue386(v *Value, config *Config) bool {
|
||||
return rewriteValue386_OpSub32(v, config)
|
||||
case OpSub32F:
|
||||
return rewriteValue386_OpSub32F(v, config)
|
||||
case OpSub32carry:
|
||||
return rewriteValue386_OpSub32carry(v, config)
|
||||
case OpSub32withcarry:
|
||||
return rewriteValue386_OpSub32withcarry(v, config)
|
||||
case OpSub64F:
|
||||
return rewriteValue386_OpSub64F(v, config)
|
||||
case OpSub8:
|
||||
@ -551,6 +565,45 @@ func rewriteValue386(v *Value, config *Config) bool {
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValue386_Op386ADCL(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (ADCL x (MOVLconst [c]) f)
|
||||
// cond:
|
||||
// result: (ADCLconst [c] x f)
|
||||
for {
|
||||
x := v.Args[0]
|
||||
v_1 := v.Args[1]
|
||||
if v_1.Op != Op386MOVLconst {
|
||||
break
|
||||
}
|
||||
c := v_1.AuxInt
|
||||
f := v.Args[2]
|
||||
v.reset(Op386ADCLconst)
|
||||
v.AuxInt = c
|
||||
v.AddArg(x)
|
||||
v.AddArg(f)
|
||||
return true
|
||||
}
|
||||
// match: (ADCL (MOVLconst [c]) x f)
|
||||
// cond:
|
||||
// result: (ADCLconst [c] x f)
|
||||
for {
|
||||
v_0 := v.Args[0]
|
||||
if v_0.Op != Op386MOVLconst {
|
||||
break
|
||||
}
|
||||
c := v_0.AuxInt
|
||||
x := v.Args[1]
|
||||
f := v.Args[2]
|
||||
v.reset(Op386ADCLconst)
|
||||
v.AuxInt = c
|
||||
v.AddArg(x)
|
||||
v.AddArg(f)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValue386_Op386ADDL(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
@ -787,6 +840,41 @@ func rewriteValue386_Op386ADDL(v *Value, config *Config) bool {
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValue386_Op386ADDLcarry(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (ADDLcarry x (MOVLconst [c]))
|
||||
// cond:
|
||||
// result: (ADDLconstcarry [c] x)
|
||||
for {
|
||||
x := v.Args[0]
|
||||
v_1 := v.Args[1]
|
||||
if v_1.Op != Op386MOVLconst {
|
||||
break
|
||||
}
|
||||
c := v_1.AuxInt
|
||||
v.reset(Op386ADDLconstcarry)
|
||||
v.AuxInt = c
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
// match: (ADDLcarry (MOVLconst [c]) x)
|
||||
// cond:
|
||||
// result: (ADDLconstcarry [c] x)
|
||||
for {
|
||||
v_0 := v.Args[0]
|
||||
if v_0.Op != Op386MOVLconst {
|
||||
break
|
||||
}
|
||||
c := v_0.AuxInt
|
||||
x := v.Args[1]
|
||||
v.reset(Op386ADDLconstcarry)
|
||||
v.AuxInt = c
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValue386_Op386ADDLconst(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
@ -3799,13 +3887,13 @@ func rewriteValue386_OpLoad(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Load <t> ptr mem)
|
||||
// cond: is32BitInt(t)
|
||||
// cond: (is32BitInt(t) || isPtr(t))
|
||||
// result: (MOVLload ptr mem)
|
||||
for {
|
||||
t := v.Type
|
||||
ptr := v.Args[0]
|
||||
mem := v.Args[1]
|
||||
if !(is32BitInt(t)) {
|
||||
if !(is32BitInt(t) || isPtr(t)) {
|
||||
break
|
||||
}
|
||||
v.reset(Op386MOVLload)
|
||||
@ -9205,6 +9293,21 @@ func rewriteValue386_OpMul32F(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValue386_OpMul32uhilo(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Mul32uhilo x y)
|
||||
// cond:
|
||||
// result: (MULLQU x y)
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(Op386MULLQU)
|
||||
v.AddArg(x)
|
||||
v.AddArg(y)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValue386_OpMul64F(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
@ -10731,6 +10834,28 @@ func rewriteValue386_Op386SARWconst(v *Value, config *Config) bool {
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValue386_Op386SBBL(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (SBBL x (MOVLconst [c]) f)
|
||||
// cond:
|
||||
// result: (SBBLconst [c] x f)
|
||||
for {
|
||||
x := v.Args[0]
|
||||
v_1 := v.Args[1]
|
||||
if v_1.Op != Op386MOVLconst {
|
||||
break
|
||||
}
|
||||
c := v_1.AuxInt
|
||||
f := v.Args[2]
|
||||
v.reset(Op386SBBLconst)
|
||||
v.AuxInt = c
|
||||
v.AddArg(x)
|
||||
v.AddArg(f)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValue386_Op386SBBLcarrymask(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
@ -11801,6 +11926,26 @@ func rewriteValue386_Op386SUBL(v *Value, config *Config) bool {
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValue386_Op386SUBLcarry(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (SUBLcarry x (MOVLconst [c]))
|
||||
// cond:
|
||||
// result: (SUBLconstcarry [c] x)
|
||||
for {
|
||||
x := v.Args[0]
|
||||
v_1 := v.Args[1]
|
||||
if v_1.Op != Op386MOVLconst {
|
||||
break
|
||||
}
|
||||
c := v_1.AuxInt
|
||||
v.reset(Op386SUBLconstcarry)
|
||||
v.AuxInt = c
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValue386_Op386SUBLconst(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
@ -12035,6 +12180,38 @@ func rewriteValue386_OpSub32F(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValue386_OpSub32carry(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Sub32carry x y)
|
||||
// cond:
|
||||
// result: (SUBLcarry x y)
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
v.reset(Op386SUBLcarry)
|
||||
v.AddArg(x)
|
||||
v.AddArg(y)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValue386_OpSub32withcarry(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (Sub32withcarry x y c)
|
||||
// cond:
|
||||
// result: (SBBL x y c)
|
||||
for {
|
||||
x := v.Args[0]
|
||||
y := v.Args[1]
|
||||
c := v.Args[2]
|
||||
v.reset(Op386SBBL)
|
||||
v.AddArg(x)
|
||||
v.AddArg(y)
|
||||
v.AddArg(c)
|
||||
return true
|
||||
}
|
||||
}
|
||||
func rewriteValue386_OpSub64F(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
|
||||
@ -178,21 +178,34 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
|
||||
ssa.Op386ADDSS, ssa.Op386ADDSD, ssa.Op386SUBSS, ssa.Op386SUBSD,
|
||||
ssa.Op386MULSS, ssa.Op386MULSD, ssa.Op386DIVSS, ssa.Op386DIVSD,
|
||||
ssa.Op386PXOR,
|
||||
ssa.Op386ADCL:
|
||||
ssa.Op386ADCL,
|
||||
ssa.Op386SBBL:
|
||||
r := gc.SSARegNum(v)
|
||||
if r != gc.SSARegNum(v.Args[0]) {
|
||||
v.Fatalf("input[0] and output not in same register %s", v.LongString())
|
||||
}
|
||||
opregreg(v.Op.Asm(), r, gc.SSARegNum(v.Args[1]))
|
||||
|
||||
case ssa.Op386ADDLcarry:
|
||||
// output 0 is carry, output 1 is the low 32 bits.
|
||||
case ssa.Op386ADDLcarry, ssa.Op386SUBLcarry:
|
||||
// output 0 is carry/borrow, output 1 is the low 32 bits.
|
||||
r := gc.SSARegNum1(v)
|
||||
if r != gc.SSARegNum(v.Args[0]) {
|
||||
v.Fatalf("input[0] and output[1] not in same register %s", v.LongString())
|
||||
}
|
||||
opregreg(v.Op.Asm(), r, gc.SSARegNum(v.Args[1]))
|
||||
|
||||
case ssa.Op386ADDLconstcarry, ssa.Op386SUBLconstcarry:
|
||||
// output 0 is carry/borrow, output 1 is the low 32 bits.
|
||||
r := gc.SSARegNum1(v)
|
||||
if r != gc.SSARegNum(v.Args[0]) {
|
||||
v.Fatalf("input[0] and output[1] not in same register %s", v.LongString())
|
||||
}
|
||||
p := gc.Prog(v.Op.Asm())
|
||||
p.From.Type = obj.TYPE_CONST
|
||||
p.From.Offset = v.AuxInt
|
||||
p.To.Type = obj.TYPE_REG
|
||||
p.To.Reg = r
|
||||
|
||||
case ssa.Op386DIVL, ssa.Op386DIVW,
|
||||
ssa.Op386DIVLU, ssa.Op386DIVWU,
|
||||
ssa.Op386MODL, ssa.Op386MODW,
|
||||
@ -289,6 +302,12 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
|
||||
m.To.Reg = x86.REG_DX
|
||||
}
|
||||
|
||||
case ssa.Op386MULLQU:
|
||||
// AX * args[1], high 32 bits in DX (result[0]), low 32 bits in AX (result[1]).
|
||||
p := gc.Prog(v.Op.Asm())
|
||||
p.From.Type = obj.TYPE_REG
|
||||
p.From.Reg = gc.SSARegNum(v.Args[1])
|
||||
|
||||
case ssa.Op386ADDLconst:
|
||||
r := gc.SSARegNum(v)
|
||||
a := gc.SSARegNum(v.Args[0])
|
||||
@ -336,6 +355,8 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
|
||||
//p.From3.Reg = gc.SSARegNum(v.Args[0])
|
||||
|
||||
case ssa.Op386SUBLconst,
|
||||
ssa.Op386ADCLconst,
|
||||
ssa.Op386SBBLconst,
|
||||
ssa.Op386ANDLconst,
|
||||
ssa.Op386ORLconst,
|
||||
ssa.Op386XORLconst,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user