qbit/go
1
0
Fork 0
mirror of https://github.com/golang/go synced 2024-11-19 15:05:00 -07:00
Code Releases Activity

cmd/internal/obj/arm64: fix assemble fcsels/fcseld bug

Browse Source 
The current code treats the type of SIMD&FP register as C_REG incorrectly.

The fix code converts C_REG type into C_FREG type.

Uncomment fcsels/fcseld test cases.

Fixes #21582
Change-Id: I754c51f72a0418bd352cbc0f7740f14cc599c72d
Reviewed-on: https://go-review.googlesource.com/58350
Reviewed-by: Cherry Zhang <cherryyz@google.com>
Run-TryBot: Cherry Zhang <cherryyz@google.com>
TryBot-Result: Gobot Gobot <gobot@golang.org>
This commit is contained in:
fanzha02 2017-06-14 06:44:43 +00:00 committed by Cherry Zhang
parent 38bd725bf1
commit aea286b449
2 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/cmd/asm/internal/asm/testdata/arm64enc.s vendored
View File

@ -406,8 +406,8 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$-8
FCMPES $(0.0), F29 // b823201e FCMPES $(0.0), F29 // b823201e
FCMPED F13, F10 // 50216d1e FCMPED F13, F10 // 50216d1e
FCMPED $(0.0), F25 // 3823601e FCMPED $(0.0), F25 // 3823601e
// FCSELS EQ, F26, F27, F25 // 590f3b1e FCSELS EQ, F26, F27, F25 // 590f3b1e
// FCSELD PL, F8, F22, F7 // 075d761e FCSELD PL, F8, F22, F7 // 075d761e
//TODO FCVTASW F21, R15 // af02241e //TODO FCVTASW F21, R15 // af02241e
//TODO FCVTAS F20, ZR // 9f02249e //TODO FCVTAS F20, ZR // 9f02249e
//TODO FCVTASW F6, R11 // cb00641e //TODO FCVTASW F6, R11 // cb00641e

2
src/cmd/internal/obj/arm64/asm7.go
View File

@ -536,7 +536,7 @@ var optab = []Optab{
{AFCMPS, C_FREG, C_FREG, C_NONE, 56, 4, 0, 0, 0}, {AFCMPS, C_FREG, C_FREG, C_NONE, 56, 4, 0, 0, 0},
{AFCMPS, C_FCON, C_FREG, C_NONE, 56, 4, 0, 0, 0}, {AFCMPS, C_FCON, C_FREG, C_NONE, 56, 4, 0, 0, 0},
{AFCCMPS, C_COND, C_FREG, C_VCON, 57, 4, 0, 0, 0}, {AFCCMPS, C_COND, C_FREG, C_VCON, 57, 4, 0, 0, 0},
{AFCSELD, C_COND, C_REG, C_FREG, 18, 4, 0, 0, 0}, {AFCSELD, C_COND, C_FREG, C_FREG, 18, 4, 0, 0, 0},
{AFCVTSD, C_FREG, C_NONE, C_FREG, 29, 4, 0, 0, 0}, {AFCVTSD, C_FREG, C_NONE, C_FREG, 29, 4, 0, 0, 0},
{ACLREX, C_NONE, C_NONE, C_VCON, 38, 4, 0, 0, 0}, {ACLREX, C_NONE, C_NONE, C_VCON, 38, 4, 0, 0, 0},
{ACLREX, C_NONE, C_NONE, C_NONE, 38, 4, 0, 0, 0}, {ACLREX, C_NONE, C_NONE, C_NONE, 38, 4, 0, 0, 0},