mirror of
https://github.com/golang/go
synced 2024-11-22 01:04:40 -07:00
arm floating point simulation
R=rsc CC=golang-dev https://golang.org/cl/3565041
This commit is contained in:
Ken Thompson
parent
aa9c213e56
commit
ae60526848
@ -29,6 +29,11 @@ softfloat(void)
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p->cond->mark |= LABEL;
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for(p = cursym->text; p != P; p = p->link) {
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switch(p->as) {
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case AMOVW:
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if(p->to.type == D_FREG || p->from.type == D_FREG)
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goto soft;
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goto notsoft;
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case AMOVWD:
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case AMOVWF:
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case AMOVDW:
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@ -37,6 +42,7 @@ softfloat(void)
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case AMOVDF:
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case AMOVF:
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case AMOVD:
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case ACMPF:
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case ACMPD:
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case AADDF:
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@ -47,6 +53,12 @@ softfloat(void)
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case AMULD:
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case ADIVF:
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case ADIVD:
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goto soft;
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default:
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goto notsoft;
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soft:
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if (psfloat == P)
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diag("floats used with _sfloat not defined");
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if (!wasfloat || (p->mark&LABEL)) {
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@ -65,7 +77,8 @@ softfloat(void)
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wasfloat = 1;
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}
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break;
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default:
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notsoft:
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wasfloat = 0;
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}
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}
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@ -8,7 +8,15 @@
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#include "runtime.h"
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void abort(void);
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#define CPSR 14
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#define FLAGS_N (1 << 31)
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#define FLAGS_Z (1 << 30)
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#define FLAGS_C (1 << 29)
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#define FLAGS_V (1 << 28)
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void runtime·abort(void);
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static uint32 trace = 0;
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static void
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fabort(void)
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@ -19,101 +27,36 @@ fabort(void)
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}
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}
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static uint32 doabort = 0;
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static uint32 trace = 0;
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static const int8* opnames[] = {
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// binary
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"adf",
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"muf",
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"suf",
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"rsf",
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"dvf",
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"rdf",
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"pow",
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"rpw",
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"rmf",
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"fml",
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"fdv",
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"frd",
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"pol",
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"UNDEFINED",
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"UNDEFINED",
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"UNDEFINED",
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// unary
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"mvf",
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"mnf",
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"abs",
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"rnd",
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"sqt",
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"log",
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"lgn",
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"exp",
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"sin",
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"cos",
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"tan",
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"asn",
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"acs",
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"atn",
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"urd",
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"nrm"
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};
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static const int8* fpconst[] = {
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"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0",
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};
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static const uint64 fpdconst[] = {
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0x0000000000000000ll,
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0x3ff0000000000000ll,
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0x4000000000000000ll,
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0x4008000000000000ll,
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0x4010000000000000ll,
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0x4014000000000000ll,
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0x3fe0000000000000ll,
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0x4024000000000000ll
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};
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static const int8* fpprec[] = {
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"s", "d", "e", "?"
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};
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static uint32
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precision(uint32 i)
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static void
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putf(uint32 reg, uint32 val)
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{
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switch (i&0x00080080) {
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case 0:
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return 0;
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case 0x80:
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return 1;
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default:
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fabort();
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}
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return 0;
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m->freglo[reg] = val;
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}
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static void
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putd(uint32 reg, uint64 val)
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{
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m->freglo[reg] = (uint32)val;
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m->freghi[reg] = (uint32)(val>>32);
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}
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static uint64
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frhs(uint32 rhs)
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getd(uint32 reg)
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{
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if (rhs & 0x8) {
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return fpdconst[rhs&0x7];
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} else {
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return m->freg[rhs&0x7];
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}
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return (uint64)m->freglo[reg] | ((uint64)m->freghi[reg]<<32);
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}
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static void
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fprint(void)
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{
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uint32 i;
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for (i = 0; i < 8; i++) {
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runtime·printf("\tf%d:\t%X\n", i, m->freg[i]);
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for (i = 0; i < 16; i++) {
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runtime·printf("\tf%d:\t%X %X\n", i, m->freghi[i], m->freglo[i]);
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}
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}
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static uint32
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d2s(uint64 d)
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d2f(uint64 d)
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{
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uint32 x;
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@ -122,289 +65,420 @@ d2s(uint64 d)
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}
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static uint64
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s2d(uint32 s)
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f2d(uint32 f)
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{
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uint64 x;
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runtime·f32to64c(s, &x);
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runtime·f32to64c(f, &x);
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return x;
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}
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// cdp, data processing instructions
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static void
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dataprocess(uint32* pc)
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static uint32
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fstatus(bool nan, int32 cmp)
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{
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uint32 i, opcode, unary, dest, lhs, rhs, prec;
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uint64 l, r;
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uint64 fd;
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i = *pc;
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// data processing
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opcode = i>>20 & 15;
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unary = i>>15 & 1;
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dest = i>>12 & 7;
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lhs = i>>16 & 7;
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rhs = i & 15;
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prec = precision(i);
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// if (prec != 1)
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// goto undef;
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if (unary) {
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switch (opcode) {
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case 0: // mvf
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fd = frhs(rhs);
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if(prec == 0)
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fd = s2d(d2s(fd));
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m->freg[dest] = fd;
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goto ret;
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default:
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goto undef;
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}
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} else {
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l = m->freg[lhs];
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r = frhs(rhs);
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switch (opcode) {
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default:
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goto undef;
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case 0:
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runtime·fadd64c(l, r, &m->freg[dest]);
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break;
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case 1:
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runtime·fmul64c(l, r, &m->freg[dest]);
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break;
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case 2:
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runtime·fsub64c(l, r, &m->freg[dest]);
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break;
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case 4:
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runtime·fdiv64c(l, r, &m->freg[dest]);
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break;
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}
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goto ret;
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}
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undef:
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doabort = 1;
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ret:
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if (trace || doabort) {
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runtime·printf(" %p %x\t%s%s\tf%d, ", pc, *pc, opnames[opcode | unary<<4],
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fpprec[prec], dest);
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if (!unary)
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runtime·printf("f%d, ", lhs);
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if (rhs & 0x8)
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runtime·printf("#%s\n", fpconst[rhs&0x7]);
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else
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runtime·printf("f%d\n", rhs&0x7);
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fprint();
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}
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if (doabort)
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fabort();
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if(nan)
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return FLAGS_C | FLAGS_V;
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if(cmp == 0)
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return FLAGS_Z | FLAGS_C;
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if(cmp < 0)
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return FLAGS_N;
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return FLAGS_C;
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}
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#define CPSR 14
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#define FLAGS_N (1 << 31)
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#define FLAGS_Z (1 << 30)
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#define FLAGS_C (1 << 29)
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#define FLAGS_V (1 << 28)
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// cmf, compare floating point
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static void
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compare(uint32 *pc, uint32 *regs)
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{
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uint32 i, flags, lhs, rhs;
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uint64 l, r;
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int32 cmp;
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bool nan;
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i = *pc;
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flags = 0;
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lhs = i>>16 & 0x7;
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rhs = i & 0xf;
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l = m->freg[lhs];
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r = frhs(rhs);
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runtime·fcmp64c(l, r, &cmp, &nan);
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if (nan)
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flags = FLAGS_C | FLAGS_V;
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else if (cmp == 0)
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flags = FLAGS_Z | FLAGS_C;
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else if (cmp < 0)
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flags = FLAGS_N;
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else
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flags = FLAGS_C;
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if (trace) {
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runtime·printf(" %p %x\tcmf\tf%d, ", pc, *pc, lhs);
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if (rhs & 0x8)
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runtime·printf("#%s\n", fpconst[rhs&0x7]);
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else
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runtime·printf("f%d\n", rhs&0x7);
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}
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regs[CPSR] = regs[CPSR] & 0x0fffffff | flags;
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}
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// ldf/stf, load/store floating
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static void
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loadstore(uint32 *pc, uint32 *regs)
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{
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uint32 i, isload, coproc, ud, wb, tlen, p, reg, freg, offset;
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uint32 addr;
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i = *pc;
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coproc = i>>8&0xf;
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isload = i>>20&1;
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p = i>>24&1;
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ud = i>>23&1;
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tlen = i>>(22 - 1)&2 | i>>15&1;
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wb = i>>21&1;
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reg = i>>16 &0xf;
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freg = i>>12 &0x7;
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offset = (i&0xff) << 2;
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if (coproc != 1 || p != 1 || wb != 0 || tlen > 1)
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goto undef;
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if (reg > 13)
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goto undef;
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if (ud)
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addr = regs[reg] + offset;
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else
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addr = regs[reg] - offset;
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if (isload)
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if (tlen)
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m->freg[freg] = *((uint64*)addr);
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else
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m->freg[freg] = s2d(*((uint32*)addr));
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else
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if (tlen)
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*((uint64*)addr) = m->freg[freg];
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else
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*((uint32*)addr) = d2s(m->freg[freg]);
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goto ret;
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undef:
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doabort = 1;
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ret:
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if (trace || doabort) {
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if (isload)
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runtime·printf(" %p %x\tldf", pc, *pc);
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else
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runtime·printf(" %p %x\tstf", pc, *pc);
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runtime·printf("%s\t\tf%d, %s%d(r%d)", fpprec[tlen], freg, ud ? "" : "-", offset, reg);
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runtime·printf("\t\t// %p", regs[reg] + (ud ? offset : -offset));
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if (coproc != 1 || p != 1 || wb != 0)
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runtime·printf(" coproc: %d pre: %d wb %d", coproc, p, wb);
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runtime·printf("\n");
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fprint();
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}
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if (doabort)
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fabort();
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}
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static void
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fltfix(uint32 *pc, uint32 *regs)
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{
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uint32 i, toarm, freg, reg, prec;
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int64 val;
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uint64 f0;
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bool ok;
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i = *pc;
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toarm = i>>20 & 0x1;
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freg = i>>16 & 0x7;
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reg = i>>12 & 0xf;
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prec = precision(i);
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if (toarm) { // fix
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f0 = m->freg[freg];
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runtime·f64tointc(f0, &val, &ok);
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if (!ok || (int32)val != val)
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val = 0;
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regs[reg] = val;
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} else { // flt
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runtime·fintto64c((int32)regs[reg], &f0);
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m->freg[freg] = f0;
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}
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goto ret;
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ret:
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if (trace || doabort) {
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if (toarm)
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runtime·printf(" %p %x\tfix%s\t\tr%d, f%d\n", pc, *pc, fpprec[prec], reg, freg);
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else
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runtime·printf(" %p %x\tflt%s\t\tf%d, r%d\n", pc, *pc, fpprec[prec], freg, reg);
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fprint();
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}
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if (doabort)
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fabort();
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}
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// returns number of words that the fp instruction is occupying, 0 if next instruction isn't float.
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// TODO(kaib): insert sanity checks for coproc 1
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// returns number of words that the fp instruction
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// is occupying, 0 if next instruction isn't float.
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static uint32
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stepflt(uint32 *pc, uint32 *regs)
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{
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uint32 i, c;
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//printf("stepflt %p %p\n", pc, *pc);
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uint32 i, regd, regm, regn;
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uint32 *addr;
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uint64 uval;
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int64 sval;
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bool nan, ok;
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int32 cmp;
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i = *pc;
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// unconditional forward branches.
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// inserted by linker after we instrument the code.
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if ((i & 0xff000000) == 0xea000000) {
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if (i & 0x00800000) {
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return 0;
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}
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return (i & 0x007fffff) + 2;
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}
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c = i >> 25 & 7;
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switch(c) {
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case 6: // 110
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loadstore(pc, regs);
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return 1;
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case 7: // 111
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if (i>>24 & 1)
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return 0; // ignore swi
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if (i>>4 & 1) { //data transfer
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if ((i&0x00f0ff00) == 0x0090f100) {
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compare(pc, regs);
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} else if ((i&0x00e00f10) == 0x00000110) {
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fltfix(pc, regs);
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} else {
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runtime·printf(" %p %x\t// case 7 fail\n", pc, i);
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fabort();
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}
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} else {
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dataprocess(pc);
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}
|
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return 1;
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}
|
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if(trace)
|
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runtime·printf("stepflt %p %x\n", pc, i);
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// special cases
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if((i&0xfffff000) == 0xe59fb000) {
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// load r11 from pc-relative address.
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// might be part of a floating point move
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// (or might not, but no harm in simulating
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// one instruction too many).
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regs[11] = *(uint32*)((uint8*)pc + (i&0xfff) + 8);
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addr = (uint32*)((uint8*)pc + (i&0xfff) + 8);
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regs[11] = addr[0];
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if(trace)
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runtime·printf("*** cpu R[%d] = *(%p) %x\n",
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11, addr, regs[11]);
|
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return 1;
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}
|
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|
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if(i == 0xe08bb00d) {
|
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// add sp to 11.
|
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// might be part of a large stack offset address
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// (or might not, but again no harm done).
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regs[11] += regs[13];
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|
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if(trace)
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runtime·printf("*** cpu R[%d] += R[%d] %x\n",
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11, 13, regs[11]);
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return 1;
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}
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if(i == 0xeef1fa10) {
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regs[CPSR] = (regs[CPSR]&0x0fffffff) | m->fflag;
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|
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if(trace)
|
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runtime·printf("*** fpsr R[CPSR] = F[CPSR] %x\n", regs[CPSR]);
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return 1;
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}
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goto stage1;
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stage1: // load/store regn is cpureg, regm is 8bit offset
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regd = i>>12 & 0xf;
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regn = i>>16 & 0xf;
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regm = (i & 0xff) << 2; // PLUS or MINUS ??
|
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|
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switch(i & 0xfff00f00) {
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default:
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goto stage2;
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case 0xed900a00: // single load
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addr = (uint32*)(regs[regn] + regm);
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m->freglo[regd] = addr[0];
|
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if(trace)
|
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runtime·printf("*** load F[%d] = %x\n",
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||||
regd, m->freglo[regd]);
|
||||
break;
|
||||
|
||||
case 0xed900b00: // double load
|
||||
addr = (uint32*)(regs[regn] + regm);
|
||||
m->freglo[regd] = addr[0];
|
||||
m->freghi[regd] = addr[1];
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** load D[%d] = %x-%x\n",
|
||||
regd, m->freghi[regd], m->freglo[regd]);
|
||||
break;
|
||||
|
||||
case 0xed800a00: // single store
|
||||
addr = (uint32*)(regs[regn] + regm);
|
||||
addr[0] = m->freglo[regd];
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** *(%p) = %x\n",
|
||||
addr, addr[0]);
|
||||
break;
|
||||
|
||||
case 0xed800b00: // double store
|
||||
addr = (uint32*)(regs[regn] + regm);
|
||||
addr[0] = m->freglo[regd];
|
||||
addr[1] = m->freghi[regd];
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** *(%p) = %x-%x\n",
|
||||
addr, addr[1], addr[0]);
|
||||
break;
|
||||
}
|
||||
return 1;
|
||||
|
||||
stage2: // regd, regm, regn are 4bit variables
|
||||
regm = i>>0 & 0xf;
|
||||
switch(i & 0xfff00ff0) {
|
||||
default:
|
||||
goto stage3;
|
||||
|
||||
case 0xf3000110: // veor
|
||||
m->freglo[regd] = m->freglo[regm]^m->freglo[regn];
|
||||
m->freghi[regd] = m->freghi[regm]^m->freghi[regn];
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** veor D[%d] = %x-%x\n",
|
||||
regd, m->freghi[regd], m->freglo[regd]);
|
||||
break;
|
||||
|
||||
case 0xeeb00b00: // D[regd] = const(regn,regm)
|
||||
regn = (regn<<4) | regm;
|
||||
regm = 0x40000000UL;
|
||||
if(regn & 0x80)
|
||||
regm |= 0x80000000UL;
|
||||
if(regn & 0x40)
|
||||
regm ^= 0x7fc00000UL;
|
||||
regm |= (regn & 0x3f) << 16;
|
||||
m->freglo[regd] = 0;
|
||||
m->freghi[regd] = regm;
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** immed D[%d] = %x-%x\n",
|
||||
regd, m->freghi[regd], m->freglo[regd]);
|
||||
break;
|
||||
|
||||
case 0xeeb00a00: // F[regd] = const(regn,regm)
|
||||
regn = (regn<<4) | regm;
|
||||
regm = 0x40000000UL;
|
||||
if(regn & 0x80)
|
||||
regm |= 0x80000000UL;
|
||||
if(regn & 0x40)
|
||||
regm ^= 0x7e000000UL;
|
||||
regm |= (regn & 0x3f) << 19;
|
||||
m->freglo[regd] = regm;
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** immed D[%d] = %x\n",
|
||||
regd, m->freglo[regd]);
|
||||
break;
|
||||
|
||||
case 0xee300b00: // D[regd] = D[regn]+D[regm]
|
||||
runtime·fadd64c(getd(regn), getd(regm), &uval);
|
||||
putd(regd, uval);
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** add D[%d] = D[%d]+D[%d] %x-%x\n",
|
||||
regd, regn, regm, m->freghi[regd], m->freglo[regd]);
|
||||
break;
|
||||
|
||||
case 0xee300a00: // F[regd] = F[regn]+F[regm]
|
||||
runtime·fadd64c(f2d(m->freglo[regn]), f2d(m->freglo[regm]), &uval);
|
||||
m->freglo[regd] = d2f(uval);
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** add F[%d] = F[%d]+F[%d] %x\n",
|
||||
regd, regn, regm, m->freglo[regd]);
|
||||
break;
|
||||
|
||||
case 0xee300b40: // D[regd] = D[regn]-D[regm]
|
||||
runtime·fsub64c(getd(regn), getd(regm), &uval);
|
||||
putd(regd, uval);
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** sub D[%d] = D[%d]-D[%d] %x-%x\n",
|
||||
regd, regn, regm, m->freghi[regd], m->freglo[regd]);
|
||||
break;
|
||||
|
||||
case 0xee300a40: // F[regd] = F[regn]-F[regm]
|
||||
runtime·fsub64c(f2d(m->freglo[regn]), f2d(m->freglo[regm]), &uval);
|
||||
m->freglo[regd] = d2f(uval);
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** sub F[%d] = F[%d]-F[%d] %x\n",
|
||||
regd, regn, regm, m->freglo[regd]);
|
||||
break;
|
||||
|
||||
case 0xee200b00: // D[regd] = D[regn]*D[regm]
|
||||
runtime·fmul64c(getd(regn), getd(regm), &uval);
|
||||
putd(regd, uval);
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** mul D[%d] = D[%d]*D[%d] %x-%x\n",
|
||||
regd, regn, regm, m->freghi[regd], m->freglo[regd]);
|
||||
break;
|
||||
|
||||
case 0xee200a00: // F[regd] = F[regn]*F[regm]
|
||||
runtime·fmul64c(f2d(m->freglo[regn]), f2d(m->freglo[regm]), &uval);
|
||||
m->freglo[regd] = d2f(uval);
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** mul F[%d] = F[%d]*F[%d] %x\n",
|
||||
regd, regn, regm, m->freglo[regd]);
|
||||
break;
|
||||
|
||||
case 0xee800b00: // D[regd] = D[regn]/D[regm]
|
||||
runtime·fdiv64c(getd(regn), getd(regm), &uval);
|
||||
putd(regd, uval);
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** div D[%d] = D[%d]/D[%d] %x-%x\n",
|
||||
regd, regn, regm, m->freghi[regd], m->freglo[regd]);
|
||||
break;
|
||||
|
||||
case 0xee800a00: // F[regd] = F[regn]/F[regm]
|
||||
runtime·fdiv64c(f2d(m->freglo[regn]), f2d(m->freglo[regm]), &uval);
|
||||
m->freglo[regd] = d2f(uval);
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** div F[%d] = F[%d]/F[%d] %x\n",
|
||||
regd, regn, regm, m->freglo[regd]);
|
||||
break;
|
||||
|
||||
case 0xee000b10: // S[regn] = R[regd] (MOVW) (regm ignored)
|
||||
m->freglo[regn] = regs[regd];
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** cpy S[%d] = R[%d] %x\n",
|
||||
regn, regd, m->freglo[regn]);
|
||||
break;
|
||||
|
||||
case 0xee100b10: // R[regd] = S[regn] (MOVW) (regm ignored)
|
||||
regs[regd] = m->freglo[regn];
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** cpy R[%d] = S[%d] %x\n",
|
||||
regd, regn, regs[regd]);
|
||||
break;
|
||||
}
|
||||
return 1;
|
||||
|
||||
stage3: // regd, regm are 4bit variables
|
||||
switch(i & 0xffff0ff0) {
|
||||
default:
|
||||
goto done;
|
||||
|
||||
case 0xeeb00a40: // F[regd] = F[regm] (MOVF)
|
||||
m->freglo[regd] = m->freglo[regm];
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** F[%d] = F[%d] %x\n",
|
||||
regd, regm, m->freglo[regd]);
|
||||
break;
|
||||
|
||||
case 0xeeb00b40: // D[regd] = D[regm] (MOVD)
|
||||
m->freglo[regd] = m->freglo[regm];
|
||||
m->freghi[regd] = m->freghi[regm];
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** D[%d] = D[%d] %x-%x\n",
|
||||
regd, regm, m->freghi[regd], m->freglo[regd]);
|
||||
break;
|
||||
|
||||
case 0xeeb40bc0: // D[regd] :: D[regm] (CMPD)
|
||||
runtime·fcmp64c(getd(regd), getd(regm), &cmp, &nan);
|
||||
m->fflag = fstatus(nan, cmp);
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** cmp D[%d]::D[%d] %x\n",
|
||||
regd, regm, m->fflag);
|
||||
break;
|
||||
|
||||
case 0xeeb40ac0: // F[regd] :: F[regm] (CMPF)
|
||||
runtime·fcmp64c(f2d(m->freglo[regd]), f2d(m->freglo[regm]), &cmp, &nan);
|
||||
m->fflag = fstatus(nan, cmp);
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** cmp F[%d]::F[%d] %x\n",
|
||||
regd, regm, m->fflag);
|
||||
break;
|
||||
|
||||
case 0xeeb70ac0: // D[regd] = F[regm] (MOVFD)
|
||||
putd(regd, f2d(m->freglo[regm]));
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** f2d D[%d]=F[%d] %x-%x\n",
|
||||
regd, regm, m->freghi[regd], m->freglo[regd]);
|
||||
break;
|
||||
|
||||
case 0xeeb70bc0: // F[regd] = D[regm] (MOVDF)
|
||||
m->freglo[regd] = d2f(getd(regm));
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** d2f F[%d]=D[%d] %x-%x\n",
|
||||
regd, regm, m->freghi[regd], m->freglo[regd]);
|
||||
break;
|
||||
|
||||
case 0xeebd0ac0: // S[regd] = F[regm] (MOVFW)
|
||||
runtime·f64tointc(f2d(m->freglo[regm]), &sval, &ok);
|
||||
if(!ok || (int32)sval != sval)
|
||||
sval = 0;
|
||||
m->freglo[regd] = sval;
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** fix S[%d]=F[%d] %x\n",
|
||||
regd, regm, m->freglo[regd]);
|
||||
break;
|
||||
|
||||
case 0xeebc0ac0: // S[regd] = F[regm] (MOVFW.U)
|
||||
runtime·f64tointc(f2d(m->freglo[regm]), &sval, &ok);
|
||||
if(!ok || (uint32)sval != sval)
|
||||
sval = 0;
|
||||
m->freglo[regd] = sval;
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** fix unsigned S[%d]=F[%d] %x\n",
|
||||
regd, regm, m->freglo[regd]);
|
||||
break;
|
||||
|
||||
case 0xeebd0bc0: // S[regd] = D[regm] (MOVDW)
|
||||
runtime·f64tointc(getd(regm), &sval, &ok);
|
||||
if(!ok || (int32)sval != sval)
|
||||
sval = 0;
|
||||
m->freglo[regd] = sval;
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** fix S[%d]=D[%d] %x\n",
|
||||
regd, regm, m->freglo[regd]);
|
||||
break;
|
||||
|
||||
case 0xeebc0bc0: // S[regd] = D[regm] (MOVDW.U)
|
||||
runtime·f64tointc(getd(regm), &sval, &ok);
|
||||
if(!ok || (uint32)sval != sval)
|
||||
sval = 0;
|
||||
m->freglo[regd] = sval;
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** fix unsigned S[%d]=D[%d] %x\n",
|
||||
regd, regm, m->freglo[regd]);
|
||||
break;
|
||||
|
||||
case 0xeeb80ac0: // D[regd] = S[regm] (MOVWF)
|
||||
cmp = m->freglo[regm];
|
||||
if(cmp < 0) {
|
||||
runtime·fintto64c(-cmp, &uval);
|
||||
putf(regd, d2f(uval));
|
||||
m->freglo[regd] ^= 0x80000000;
|
||||
} else {
|
||||
runtime·fintto64c(cmp, &uval);
|
||||
putf(regd, d2f(uval));
|
||||
}
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** float D[%d]=S[%d] %x-%x\n",
|
||||
regd, regm, m->freghi[regd], m->freglo[regd]);
|
||||
break;
|
||||
|
||||
case 0xeeb80a40: // D[regd] = S[regm] (MOVWF.U)
|
||||
runtime·fintto64c(m->freglo[regm], &uval);
|
||||
putf(regd, d2f(uval));
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** float unsigned D[%d]=S[%d] %x-%x\n",
|
||||
regd, regm, m->freghi[regd], m->freglo[regd]);
|
||||
break;
|
||||
|
||||
case 0xeeb80bc0: // D[regd] = S[regm] (MOVWD)
|
||||
cmp = m->freglo[regm];
|
||||
if(cmp < 0) {
|
||||
runtime·fintto64c(-cmp, &uval);
|
||||
putd(regd, uval);
|
||||
m->freghi[regd] ^= 0x80000000;
|
||||
} else {
|
||||
runtime·fintto64c(cmp, &uval);
|
||||
putd(regd, uval);
|
||||
}
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** float D[%d]=S[%d] %x-%x\n",
|
||||
regd, regm, m->freghi[regd], m->freglo[regd]);
|
||||
break;
|
||||
|
||||
case 0xeeb80b40: // D[regd] = S[regm] (MOVWD.U)
|
||||
runtime·fintto64c(m->freglo[regm], &uval);
|
||||
putd(regd, uval);
|
||||
|
||||
if(trace)
|
||||
runtime·printf("*** float unsigned D[%d]=S[%d] %x-%x\n",
|
||||
regd, regm, m->freghi[regd], m->freglo[regd]);
|
||||
break;
|
||||
}
|
||||
return 1;
|
||||
|
||||
done:
|
||||
if((i&0xff000000) == 0xee000000 ||
|
||||
(i&0xff000000) == 0xed000000) {
|
||||
runtime·printf("stepflt %p %x\n", pc, i);
|
||||
fabort();
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -414,8 +488,12 @@ runtime·_sfloat2(uint32 *lr, uint32 r0)
|
||||
{
|
||||
uint32 skip;
|
||||
|
||||
skip = stepflt(lr, &r0);
|
||||
if(skip == 0)
|
||||
fabort(); // not ok to fail first instruction
|
||||
|
||||
lr += skip;
|
||||
while(skip = stepflt(lr, &r0))
|
||||
lr += skip;
|
||||
return lr;
|
||||
}
|
||||
|
||||
|
||||
@ -230,7 +230,9 @@ struct M
|
||||
uint32 machport; // Return address for Mach IPC (OS X)
|
||||
MCache *mcache;
|
||||
G* lockedg;
|
||||
uint64 freg[8]; // Floating point register storage used by ARM software fp routines
|
||||
uint32 freglo[16]; // D[i] lsb and F[i]
|
||||
uint32 freghi[16]; // D[i] msb and F[i+16]
|
||||
uint32 fflag; // floating point compare flags
|
||||
#ifdef __WINDOWS__
|
||||
void* gostack; // bookmark to keep track of go stack during stdcall
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user