mirror of
https://github.com/golang/go
synced 2024-11-13 16:50:23 -07:00
cmd/8g: factor out prog information
Like CL 12637051, but for 8g instead of 6g. Fix a few minor 6g errors too. R=ken2 CC=golang-dev https://golang.org/cl/12778043
This commit is contained in:
Russ Cox
parent
8eb8ad2454
commit
ac0df6ce89
@ -1,3 +1,7 @@
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// Copyright 2013 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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#include <u.h>
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#include <libc.h>
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#include "gg.h"
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@ -35,6 +39,11 @@ static ProgInfo progtable[ALAST] = {
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[AFUNCDATA]= {Pseudo},
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[APCDATA]= {Pseudo},
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// NOP is an internal no-op that also stands
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// for USED and SET annotations, not the Intel opcode.
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[ANOP]= {LeftRead | RightWrite},
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[AADCL]= {SizeL | LeftRead | RightRdwr | SetCarry | UseCarry},
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[AADCQ]= {SizeQ | LeftRead | RightRdwr | SetCarry | UseCarry},
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[AADCW]= {SizeW | LeftRead | RightRdwr | SetCarry | UseCarry},
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@ -176,13 +185,10 @@ static ProgInfo progtable[ALAST] = {
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[ANEGQ]= {SizeQ | RightRdwr | SetCarry},
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[ANEGW]= {SizeW | RightRdwr | SetCarry},
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// NOP is the opcode for USED and SET annotations, not the Intel opcode.
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[ANOP]= {LeftRead | RightWrite},
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[ANOTB]= {SizeB | RightRdwr},
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[ANOTL]= {SizeL | RightRdwr},
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[ANOTQ]= {SizeQ | RightRdwr},
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[ANOTW]= {SizeQ | RightRdwr},
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[ANOTW]= {SizeW | RightRdwr},
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[AORB]= {SizeB | LeftRead | RightRdwr | SetCarry},
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[AORL]= {SizeL | LeftRead | RightRdwr | SetCarry},
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@ -190,7 +196,7 @@ static ProgInfo progtable[ALAST] = {
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[AORW]= {SizeW | LeftRead | RightRdwr | SetCarry},
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[APOPQ]= {SizeQ | RightWrite},
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[APUSHQ]= {SizeQ | RightWrite},
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[APUSHQ]= {SizeQ | LeftRead},
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[ARCLB]= {SizeB | LeftRead | RightRdwr | ShiftCX | SetCarry | UseCarry},
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[ARCLL]= {SizeL | LeftRead | RightRdwr | ShiftCX | SetCarry | UseCarry},
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@ -168,3 +168,64 @@ int BtoR(int32);
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int BtoF(int32);
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#pragma varargck type "D" Adr*
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/*
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* prog.c
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*/
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typedef struct ProgInfo ProgInfo;
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struct ProgInfo
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{
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uint32 flags; // the bits below
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uint32 reguse; // required registers used by this instruction
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uint32 regset; // required registers set by this instruction
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uint32 regindex; // registers used by addressing mode
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};
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enum
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{
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// Pseudo-op, like TEXT, GLOBL, TYPE, PCDATA, FUNCDATA.
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Pseudo = 1<<1,
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// There's nothing to say about the instruction,
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// but it's still okay to see.
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OK = 1<<2,
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// Size of right-side write, or right-side read if no write.
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SizeB = 1<<3,
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SizeW = 1<<4,
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SizeL = 1<<5,
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SizeQ = 1<<6,
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SizeF = 1<<7, // float aka float32
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SizeD = 1<<8, // double aka float64
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// Left side: address taken, read, write.
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LeftAddr = 1<<9,
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LeftRead = 1<<10,
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LeftWrite = 1<<11,
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// Right side: address taken, read, write.
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RightAddr = 1<<12,
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RightRead = 1<<13,
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RightWrite = 1<<14,
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// Set, use, or kill of carry bit.
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// Kill means we never look at the carry bit after this kind of instruction.
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SetCarry = 1<<15,
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UseCarry = 1<<16,
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KillCarry = 1<<17,
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// Instruction kinds
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Move = 1<<18, // straight move
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Conv = 1<<19, // size conversion
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Cjmp = 1<<20, // conditional jump
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Break = 1<<21, // breaks control flow (no fallthrough)
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Call = 1<<22, // function call
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Jump = 1<<23, // jump
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Skip = 1<<24, // data instruction
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// Special cases for register use.
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ShiftCX = 1<<25, // possible shift by CX
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ImulAXDX = 1<<26, // possible multiply into DX:AX
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};
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void proginfo(ProgInfo*, Prog*);
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@ -42,28 +42,14 @@ static void elimshortmov(Reg *r);
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static int
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needc(Prog *p)
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{
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ProgInfo info;
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while(p != P) {
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switch(p->as) {
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case AADCL:
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case ASBBL:
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case ARCRB:
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case ARCRW:
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case ARCRL:
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proginfo(&info, p);
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if(info.flags & UseCarry)
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return 1;
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case AADDB:
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case AADDW:
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case AADDL:
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case ASUBB:
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case ASUBW:
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case ASUBL:
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case AJMP:
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case ARET:
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case ACALL:
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if(info.flags & (SetCarry|KillCarry))
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return 0;
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default:
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if(p->to.type == D_BRANCH)
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return 0;
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}
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p = p->link;
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}
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return 0;
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@ -94,19 +80,20 @@ peep(void)
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Reg *r, *r1, *r2;
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Prog *p, *p1;
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int t;
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ProgInfo info;
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/*
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* complete R structure
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*/
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t = 0;
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for(r=firstr; r!=R; r=r1) {
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r1 = r->link;
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if(r1 == R)
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break;
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p = r->prog->link;
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while(p != r1->prog)
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switch(p->as) {
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default:
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for(p = r->prog->link; p != r1->prog; p = p->link) {
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proginfo(&info, p);
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if(info.flags & Skip)
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continue;
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r2 = rega();
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r->link = r2;
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r2->link = r1;
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@ -120,14 +107,6 @@ peep(void)
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r1->p1 = r2;
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r = r2;
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t++;
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case ADATA:
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case AGLOBL:
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case ANAME:
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case ASIGNAME:
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case ATYPE:
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p = p->link;
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}
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}
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@ -437,6 +416,7 @@ subprop(Reg *r0)
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Adr *v1, *v2;
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Reg *r;
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int t;
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ProgInfo info;
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p = r0->prog;
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v1 = &p->from;
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@ -446,85 +426,24 @@ subprop(Reg *r0)
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if(!regtyp(v2))
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return 0;
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for(r=uniqp(r0); r!=R; r=uniqp(r)) {
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if(debug['P'] && debug['v'])
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print("\t? %P\n", r->prog);
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if(uniqs(r) == R)
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break;
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p = r->prog;
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switch(p->as) {
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case ACALL:
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proginfo(&info, p);
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if(info.flags & Call)
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return 0;
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case AIMULL:
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case AIMULW:
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if(p->to.type != D_NONE)
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break;
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case ARCLB:
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case ARCLL:
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case ARCLW:
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case ARCRB:
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case ARCRL:
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case ARCRW:
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case AROLB:
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case AROLL:
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case AROLW:
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case ARORB:
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case ARORL:
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case ARORW:
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case ASALB:
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case ASALL:
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case ASALW:
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case ASARB:
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case ASARL:
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case ASARW:
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case ASHLB:
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case ASHLL:
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case ASHLW:
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case ASHRB:
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case ASHRL:
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case ASHRW:
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if(p->from.type == D_CONST)
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break;
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case ADIVB:
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case ADIVL:
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case ADIVW:
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case AIDIVB:
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case AIDIVL:
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case AIDIVW:
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case AIMULB:
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case AMULB:
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case AMULL:
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case AMULW:
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case AREP:
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case AREPN:
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case ACWD:
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case ACDQ:
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case ASTOSB:
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case ASTOSL:
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case AMOVSB:
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case AMOVSL:
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case AFMOVF:
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case AFMOVD:
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case AFMOVFP:
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case AFMOVDP:
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if(info.reguse | info.regset)
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return 0;
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case AMOVL:
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case AMOVSS:
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case AMOVSD:
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if(p->to.type == v1->type)
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if((info.flags & Move) && (info.flags & (SizeL|SizeQ|SizeF|SizeD)) && p->to.type == v1->type)
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goto gotit;
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if(copyau(&p->from, v2) || copyau(&p->to, v2))
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break;
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}
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if(copyau(&p->from, v2) ||
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copyau(&p->to, v2))
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break;
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if(copysub(&p->from, v1, v2, 0) ||
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copysub(&p->to, v1, v2, 0))
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if(copysub(&p->from, v1, v2, 0) || copysub(&p->to, v1, v2, 0))
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break;
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}
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return 0;
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@ -669,215 +588,10 @@ copy1(Adr *v1, Adr *v2, Reg *r, int f)
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int
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copyu(Prog *p, Adr *v, Adr *s)
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{
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ProgInfo info;
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switch(p->as) {
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default:
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if(debug['P'])
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print("unknown op %A\n", p->as);
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/* SBBL; ADCL; FLD1; SAHF */
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return 2;
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case ANEGB:
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case ANEGW:
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case ANEGL:
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case ANOTB:
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case ANOTW:
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case ANOTL:
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if(copyas(&p->to, v))
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return 2;
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break;
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case ALEAL: /* lhs addr, rhs store */
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if(copyas(&p->from, v))
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return 2;
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case ANOP: /* rhs store */
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case AMOVL:
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case AMOVBLSX:
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case AMOVBLZX:
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case AMOVWLSX:
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case AMOVWLZX:
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case AMOVSS:
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case AMOVSD:
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case ACVTSD2SL:
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case ACVTSD2SS:
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case ACVTSL2SD:
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case ACVTSL2SS:
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case ACVTSS2SD:
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case ACVTSS2SL:
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case ACVTTSD2SL:
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case ACVTTSS2SL:
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if(copyas(&p->to, v)) {
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if(s != A)
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return copysub(&p->from, v, s, 1);
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if(copyau(&p->from, v))
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return 4;
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return 3;
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}
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goto caseread;
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case ARCLB:
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case ARCLL:
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case ARCLW:
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case ARCRB:
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case ARCRL:
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case ARCRW:
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case AROLB:
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case AROLL:
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case AROLW:
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case ARORB:
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case ARORL:
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case ARORW:
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case ASALB:
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case ASALL:
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case ASALW:
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case ASARB:
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case ASARL:
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case ASARW:
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case ASHLB:
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case ASHLL:
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case ASHLW:
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case ASHRB:
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case ASHRL:
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case ASHRW:
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if(copyas(&p->to, v))
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return 2;
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if(copyas(&p->from, v))
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if(p->from.type == D_CX)
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return 2;
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goto caseread;
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case AADDB: /* rhs rar */
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case AADDL:
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case AADDW:
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case AANDB:
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case AANDL:
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case AANDW:
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case ADECL:
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case ADECW:
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case AINCL:
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case AINCW:
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case ASUBB:
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case ASUBL:
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case ASUBW:
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case AORB:
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case AORL:
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case AORW:
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case AXORB:
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case AXORL:
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case AXORW:
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case AMOVB:
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case AMOVW:
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case AADDSD:
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case AADDSS:
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case ACMPSD:
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case ACMPSS:
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case ADIVSD:
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case ADIVSS:
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case AMAXSD:
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case AMAXSS:
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case AMINSD:
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case AMINSS:
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case AMULSD:
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case AMULSS:
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case ARCPSS:
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case ARSQRTSS:
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case ASQRTSD:
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case ASQRTSS:
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case ASUBSD:
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case ASUBSS:
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case AXORPD:
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if(copyas(&p->to, v))
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return 2;
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goto caseread;
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case ACMPL: /* read only */
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case ACMPW:
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case ACMPB:
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case ACOMISD:
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case ACOMISS:
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case AUCOMISD:
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case AUCOMISS:
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caseread:
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if(s != A) {
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if(copysub(&p->from, v, s, 1))
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return 1;
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return copysub(&p->to, v, s, 1);
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}
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if(copyau(&p->from, v))
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return 1;
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if(copyau(&p->to, v))
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return 1;
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break;
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case AJGE: /* no reference */
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case AJNE:
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case AJLE:
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case AJEQ:
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case AJHI:
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case AJLS:
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case AJMI:
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case AJPL:
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case AJGT:
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case AJLT:
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case AJCC:
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case AJCS:
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case AADJSP:
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case AWAIT:
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case ACLD:
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break;
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case AIMULL:
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case AIMULW:
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if(p->to.type != D_NONE) {
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if(copyas(&p->to, v))
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return 2;
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goto caseread;
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}
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case ADIVB:
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case ADIVL:
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case ADIVW:
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case AIDIVB:
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case AIDIVL:
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case AIDIVW:
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case AIMULB:
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case AMULB:
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case AMULL:
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case AMULW:
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case ACWD:
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case ACDQ:
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if(v->type == D_AX || v->type == D_DX)
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return 2;
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goto caseread;
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case AREP:
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case AREPN:
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if(v->type == D_CX)
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return 2;
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goto caseread;
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case AMOVSB:
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case AMOVSL:
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if(v->type == D_DI || v->type == D_SI)
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return 2;
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goto caseread;
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case ASTOSB:
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case ASTOSL:
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if(v->type == D_AX || v->type == D_DI)
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return 2;
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goto caseread;
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case AJMP: /* funny */
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case AJMP:
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if(s != A) {
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if(copysub(&p->to, v, s, 1))
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return 1;
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@ -887,12 +601,12 @@ copyu(Prog *p, Adr *v, Adr *s)
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return 1;
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return 0;
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case ARET: /* funny */
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case ARET:
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if(s != A)
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return 1;
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return 3;
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case ACALL: /* funny */
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case ACALL:
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if(REGEXT && v->type <= REGEXT && v->type > exregoffset)
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return 2;
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if(REGARG >= 0 && v->type == (uchar)REGARG)
|
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@ -909,11 +623,47 @@ copyu(Prog *p, Adr *v, Adr *s)
|
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return 4;
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return 3;
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case ATEXT: /* funny */
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case ATEXT:
|
||||
if(REGARG >= 0 && v->type == (uchar)REGARG)
|
||||
return 3;
|
||||
return 0;
|
||||
}
|
||||
|
||||
proginfo(&info, p);
|
||||
|
||||
if((info.reguse|info.regset) & RtoB(v->type))
|
||||
return 2;
|
||||
|
||||
if(info.flags & LeftAddr)
|
||||
if(copyas(&p->from, v))
|
||||
return 2;
|
||||
|
||||
if((info.flags & (RightRead|RightWrite)) == (RightRead|RightWrite))
|
||||
if(copyas(&p->to, v))
|
||||
return 2;
|
||||
|
||||
if(info.flags & RightWrite) {
|
||||
if(copyas(&p->to, v)) {
|
||||
if(s != A)
|
||||
return copysub(&p->from, v, s, 1);
|
||||
if(copyau(&p->from, v))
|
||||
return 4;
|
||||
return 3;
|
||||
}
|
||||
}
|
||||
|
||||
if(info.flags & (LeftAddr|LeftRead|LeftWrite|RightAddr|RightRead|RightWrite)) {
|
||||
if(s != A) {
|
||||
if(copysub(&p->from, v, s, 1))
|
||||
return 1;
|
||||
return copysub(&p->to, v, s, 1);
|
||||
}
|
||||
if(copyau(&p->from, v))
|
||||
return 1;
|
||||
if(copyau(&p->to, v))
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
331
src/cmd/8g/prog.c
Normal file
331
src/cmd/8g/prog.c
Normal file
@ -0,0 +1,331 @@
|
||||
// Copyright 2013 The Go Authors. All rights reserved.
|
||||
// Use of this source code is governed by a BSD-style
|
||||
// license that can be found in the LICENSE file.
|
||||
|
||||
#include <u.h>
|
||||
#include <libc.h>
|
||||
#include "gg.h"
|
||||
#include "opt.h"
|
||||
|
||||
// Matches real RtoB but can be used in global initializer.
|
||||
#define RtoB(r) (1<<((r)-D_AX))
|
||||
|
||||
enum {
|
||||
AX = RtoB(D_AX),
|
||||
BX = RtoB(D_BX),
|
||||
CX = RtoB(D_CX),
|
||||
DX = RtoB(D_DX),
|
||||
DI = RtoB(D_DI),
|
||||
SI = RtoB(D_SI),
|
||||
|
||||
LeftRdwr = LeftRead | LeftWrite,
|
||||
RightRdwr = RightRead | RightWrite,
|
||||
};
|
||||
|
||||
#undef RtoB
|
||||
|
||||
// This table gives the basic information about instruction
|
||||
// generated by the compiler and processed in the optimizer.
|
||||
// See opt.h for bit definitions.
|
||||
//
|
||||
// Instructions not generated need not be listed.
|
||||
// As an exception to that rule, we typically write down all the
|
||||
// size variants of an operation even if we just use a subset.
|
||||
//
|
||||
// The table is formatted for 8-space tabs.
|
||||
static ProgInfo progtable[ALAST] = {
|
||||
[ATYPE]= {Pseudo | Skip},
|
||||
[ATEXT]= {Pseudo},
|
||||
[AFUNCDATA]= {Pseudo},
|
||||
[APCDATA]= {Pseudo},
|
||||
|
||||
// NOP is an internal no-op that also stands
|
||||
// for USED and SET annotations, not the Intel opcode.
|
||||
[ANOP]= {LeftRead | RightWrite},
|
||||
|
||||
[AADCL]= {SizeL | LeftRead | RightRdwr | SetCarry | UseCarry},
|
||||
[AADCW]= {SizeW | LeftRead | RightRdwr | SetCarry | UseCarry},
|
||||
|
||||
[AADDB]= {SizeB | LeftRead | RightRdwr | SetCarry},
|
||||
[AADDL]= {SizeL | LeftRead | RightRdwr | SetCarry},
|
||||
[AADDW]= {SizeW | LeftRead | RightRdwr | SetCarry},
|
||||
|
||||
[AADDSD]= {SizeD | LeftRead | RightRdwr},
|
||||
[AADDSS]= {SizeF | LeftRead | RightRdwr},
|
||||
|
||||
[AANDB]= {SizeB | LeftRead | RightRdwr | SetCarry},
|
||||
[AANDL]= {SizeL | LeftRead | RightRdwr | SetCarry},
|
||||
[AANDW]= {SizeW | LeftRead | RightRdwr | SetCarry},
|
||||
|
||||
[ACALL]= {RightAddr | Call | KillCarry},
|
||||
|
||||
[ACDQ]= {OK, AX, AX | DX},
|
||||
[ACWD]= {OK, AX, AX | DX},
|
||||
|
||||
[ACLD]= {OK},
|
||||
[ASTD]= {OK},
|
||||
|
||||
[ACMPB]= {SizeB | LeftRead | RightRead | SetCarry},
|
||||
[ACMPL]= {SizeL | LeftRead | RightRead | SetCarry},
|
||||
[ACMPW]= {SizeW | LeftRead | RightRead | SetCarry},
|
||||
|
||||
[ACOMISD]= {SizeD | LeftRead | RightRead | SetCarry},
|
||||
[ACOMISS]= {SizeF | LeftRead | RightRead | SetCarry},
|
||||
|
||||
[ACVTSD2SL]= {SizeL | LeftRead | RightWrite | Conv},
|
||||
[ACVTSD2SS]= {SizeF | LeftRead | RightWrite | Conv},
|
||||
[ACVTSL2SD]= {SizeD | LeftRead | RightWrite | Conv},
|
||||
[ACVTSL2SS]= {SizeF | LeftRead | RightWrite | Conv},
|
||||
[ACVTSS2SD]= {SizeD | LeftRead | RightWrite | Conv},
|
||||
[ACVTSS2SL]= {SizeL | LeftRead | RightWrite | Conv},
|
||||
[ACVTTSD2SL]= {SizeL | LeftRead | RightWrite | Conv},
|
||||
[ACVTTSS2SL]= {SizeL | LeftRead | RightWrite | Conv},
|
||||
|
||||
[ADECB]= {SizeB | RightRdwr},
|
||||
[ADECL]= {SizeL | RightRdwr},
|
||||
[ADECW]= {SizeW | RightRdwr},
|
||||
|
||||
[ADIVB]= {SizeB | LeftRead, AX, AX},
|
||||
[ADIVL]= {SizeL | LeftRead, AX|DX, AX|DX},
|
||||
[ADIVW]= {SizeW | LeftRead, AX|DX, AX|DX},
|
||||
|
||||
[ADIVSD]= {SizeD | LeftRead | RightRdwr},
|
||||
[ADIVSS]= {SizeF | LeftRead | RightRdwr},
|
||||
|
||||
[AFLDCW]= {SizeW | LeftAddr },
|
||||
[AFSTCW]= {SizeW | RightAddr },
|
||||
|
||||
[AFADDD]= {SizeD | LeftAddr | RightRdwr},
|
||||
[AFADDDP]= {SizeD | LeftAddr | RightRdwr},
|
||||
[AFADDF]= {SizeF | LeftAddr | RightRdwr},
|
||||
|
||||
[AFCOMD]= {SizeD | LeftAddr | RightRead},
|
||||
[AFCOMDP]= {SizeD | LeftAddr | RightRead},
|
||||
[AFCOMDPP]= {SizeD | LeftAddr | RightRead},
|
||||
[AFCOMF]= {SizeF | LeftAddr | RightRead},
|
||||
[AFCOMFP]= {SizeF | LeftAddr | RightRead},
|
||||
[AFUCOMIP]= {SizeF | LeftAddr | RightRead},
|
||||
|
||||
[AFCHS]= {SizeD | RightRdwr}, // also SizeF
|
||||
|
||||
[AFDIVD]= {SizeD | LeftAddr | RightRdwr},
|
||||
[AFDIVDP]= {SizeD | LeftAddr | RightRdwr},
|
||||
[AFDIVF]= {SizeF | LeftAddr | RightRdwr},
|
||||
|
||||
[AFSUBD]= {SizeD | LeftAddr | RightRdwr},
|
||||
[AFSUBDP]= {SizeD | LeftAddr | RightRdwr},
|
||||
[AFSUBF]= {SizeF | LeftAddr | RightRdwr},
|
||||
[AFSUBRD]= {SizeD | LeftAddr | RightRdwr},
|
||||
[AFSUBRDP]= {SizeD | LeftAddr | RightRdwr},
|
||||
[AFSUBRF]= {SizeF | LeftAddr | RightRdwr},
|
||||
|
||||
[AFMOVD]= {SizeD | LeftAddr | RightWrite},
|
||||
[AFMOVF]= {SizeF | LeftAddr | RightWrite},
|
||||
[AFMOVL]= {SizeL | LeftAddr | RightWrite},
|
||||
[AFMOVW]= {SizeW | LeftAddr | RightWrite},
|
||||
[AFMOVV]= {SizeQ | LeftAddr | RightWrite},
|
||||
|
||||
[AFMOVDP]= {SizeD | LeftRead | RightAddr},
|
||||
[AFMOVFP]= {SizeF | LeftRead | RightAddr},
|
||||
[AFMOVLP]= {SizeL | LeftRead | RightAddr},
|
||||
[AFMOVWP]= {SizeW | LeftRead | RightAddr},
|
||||
[AFMOVVP]= {SizeQ | LeftRead | RightAddr},
|
||||
|
||||
[AFMULD]= {SizeD | LeftAddr | RightRdwr},
|
||||
[AFMULDP]= {SizeD | LeftAddr | RightRdwr},
|
||||
[AFMULF]= {SizeF | LeftAddr | RightRdwr},
|
||||
|
||||
[AIDIVB]= {SizeB | LeftRead, AX, AX},
|
||||
[AIDIVL]= {SizeL | LeftRead, AX|DX, AX|DX},
|
||||
[AIDIVW]= {SizeW | LeftRead, AX|DX, AX|DX},
|
||||
|
||||
[AIMULB]= {SizeB | LeftRead | SetCarry, AX, AX},
|
||||
[AIMULL]= {SizeL | LeftRead | ImulAXDX | SetCarry},
|
||||
[AIMULW]= {SizeW | LeftRead | ImulAXDX | SetCarry},
|
||||
|
||||
[AINCB]= {SizeB | RightRdwr},
|
||||
[AINCL]= {SizeL | RightRdwr},
|
||||
[AINCW]= {SizeW | RightRdwr},
|
||||
|
||||
[AJCC]= {Cjmp | UseCarry},
|
||||
[AJCS]= {Cjmp | UseCarry},
|
||||
[AJEQ]= {Cjmp | UseCarry},
|
||||
[AJGE]= {Cjmp | UseCarry},
|
||||
[AJGT]= {Cjmp | UseCarry},
|
||||
[AJHI]= {Cjmp | UseCarry},
|
||||
[AJLE]= {Cjmp | UseCarry},
|
||||
[AJLS]= {Cjmp | UseCarry},
|
||||
[AJLT]= {Cjmp | UseCarry},
|
||||
[AJMI]= {Cjmp | UseCarry},
|
||||
[AJNE]= {Cjmp | UseCarry},
|
||||
[AJOC]= {Cjmp | UseCarry},
|
||||
[AJOS]= {Cjmp | UseCarry},
|
||||
[AJPC]= {Cjmp | UseCarry},
|
||||
[AJPL]= {Cjmp | UseCarry},
|
||||
[AJPS]= {Cjmp | UseCarry},
|
||||
|
||||
[AJMP]= {Jump | Break | KillCarry},
|
||||
|
||||
[ALEAL]= {LeftAddr | RightWrite},
|
||||
|
||||
[AMOVBLSX]= {SizeL | LeftRead | RightWrite | Conv},
|
||||
[AMOVBLZX]= {SizeL | LeftRead | RightWrite | Conv},
|
||||
[AMOVBWSX]= {SizeW | LeftRead | RightWrite | Conv},
|
||||
[AMOVBWZX]= {SizeW | LeftRead | RightWrite | Conv},
|
||||
[AMOVWLSX]= {SizeL | LeftRead | RightWrite | Conv},
|
||||
[AMOVWLZX]= {SizeL | LeftRead | RightWrite | Conv},
|
||||
|
||||
[AMOVB]= {SizeB | LeftRead | RightWrite | Move},
|
||||
[AMOVL]= {SizeL | LeftRead | RightWrite | Move},
|
||||
[AMOVW]= {SizeW | LeftRead | RightWrite | Move},
|
||||
|
||||
[AMOVSB]= {OK, DI|SI, DI|SI},
|
||||
[AMOVSL]= {OK, DI|SI, DI|SI},
|
||||
[AMOVSW]= {OK, DI|SI, DI|SI},
|
||||
|
||||
[AMOVSD]= {SizeD | LeftRead | RightWrite | Move},
|
||||
[AMOVSS]= {SizeF | LeftRead | RightWrite | Move},
|
||||
|
||||
// We use MOVAPD as a faster synonym for MOVSD.
|
||||
[AMOVAPD]= {SizeD | LeftRead | RightWrite | Move},
|
||||
|
||||
[AMULB]= {SizeB | LeftRead | SetCarry, AX, AX},
|
||||
[AMULL]= {SizeL | LeftRead | SetCarry, AX, AX|DX},
|
||||
[AMULW]= {SizeW | LeftRead | SetCarry, AX, AX|DX},
|
||||
|
||||
[AMULSD]= {SizeD | LeftRead | RightRdwr},
|
||||
[AMULSS]= {SizeF | LeftRead | RightRdwr},
|
||||
|
||||
[ANEGB]= {SizeB | RightRdwr | SetCarry},
|
||||
[ANEGL]= {SizeL | RightRdwr | SetCarry},
|
||||
[ANEGW]= {SizeW | RightRdwr | SetCarry},
|
||||
|
||||
[ANOTB]= {SizeB | RightRdwr},
|
||||
[ANOTL]= {SizeL | RightRdwr},
|
||||
[ANOTW]= {SizeW | RightRdwr},
|
||||
|
||||
[AORB]= {SizeB | LeftRead | RightRdwr | SetCarry},
|
||||
[AORL]= {SizeL | LeftRead | RightRdwr | SetCarry},
|
||||
[AORW]= {SizeW | LeftRead | RightRdwr | SetCarry},
|
||||
|
||||
[APOPL]= {SizeL | RightWrite},
|
||||
[APUSHL]= {SizeL | LeftRead},
|
||||
|
||||
[ARCLB]= {SizeB | LeftRead | RightRdwr | ShiftCX | SetCarry | UseCarry},
|
||||
[ARCLL]= {SizeL | LeftRead | RightRdwr | ShiftCX | SetCarry | UseCarry},
|
||||
[ARCLW]= {SizeW | LeftRead | RightRdwr | ShiftCX | SetCarry | UseCarry},
|
||||
|
||||
[ARCRB]= {SizeB | LeftRead | RightRdwr | ShiftCX | SetCarry | UseCarry},
|
||||
[ARCRL]= {SizeL | LeftRead | RightRdwr | ShiftCX | SetCarry | UseCarry},
|
||||
[ARCRW]= {SizeW | LeftRead | RightRdwr | ShiftCX | SetCarry | UseCarry},
|
||||
|
||||
[AREP]= {OK, CX, CX},
|
||||
[AREPN]= {OK, CX, CX},
|
||||
|
||||
[ARET]= {Break | KillCarry},
|
||||
|
||||
[AROLB]= {SizeB | LeftRead | RightRdwr | ShiftCX | SetCarry},
|
||||
[AROLL]= {SizeL | LeftRead | RightRdwr | ShiftCX | SetCarry},
|
||||
[AROLW]= {SizeW | LeftRead | RightRdwr | ShiftCX | SetCarry},
|
||||
|
||||
[ARORB]= {SizeB | LeftRead | RightRdwr | ShiftCX | SetCarry},
|
||||
[ARORL]= {SizeL | LeftRead | RightRdwr | ShiftCX | SetCarry},
|
||||
[ARORW]= {SizeW | LeftRead | RightRdwr | ShiftCX | SetCarry},
|
||||
|
||||
[ASALB]= {SizeB | LeftRead | RightRdwr | ShiftCX | SetCarry},
|
||||
[ASALL]= {SizeL | LeftRead | RightRdwr | ShiftCX | SetCarry},
|
||||
[ASALW]= {SizeW | LeftRead | RightRdwr | ShiftCX | SetCarry},
|
||||
|
||||
[ASARB]= {SizeB | LeftRead | RightRdwr | ShiftCX | SetCarry},
|
||||
[ASARL]= {SizeL | LeftRead | RightRdwr | ShiftCX | SetCarry},
|
||||
[ASARW]= {SizeW | LeftRead | RightRdwr | ShiftCX | SetCarry},
|
||||
|
||||
[ASBBB]= {SizeB | LeftRead | RightRdwr | SetCarry | UseCarry},
|
||||
[ASBBL]= {SizeL | LeftRead | RightRdwr | SetCarry | UseCarry},
|
||||
[ASBBW]= {SizeW | LeftRead | RightRdwr | SetCarry | UseCarry},
|
||||
|
||||
[ASETCC]= {SizeB | RightRdwr | UseCarry},
|
||||
[ASETCS]= {SizeB | RightRdwr | UseCarry},
|
||||
[ASETEQ]= {SizeB | RightRdwr | UseCarry},
|
||||
[ASETGE]= {SizeB | RightRdwr | UseCarry},
|
||||
[ASETGT]= {SizeB | RightRdwr | UseCarry},
|
||||
[ASETHI]= {SizeB | RightRdwr | UseCarry},
|
||||
[ASETLE]= {SizeB | RightRdwr | UseCarry},
|
||||
[ASETLS]= {SizeB | RightRdwr | UseCarry},
|
||||
[ASETLT]= {SizeB | RightRdwr | UseCarry},
|
||||
[ASETMI]= {SizeB | RightRdwr | UseCarry},
|
||||
[ASETNE]= {SizeB | RightRdwr | UseCarry},
|
||||
[ASETOC]= {SizeB | RightRdwr | UseCarry},
|
||||
[ASETOS]= {SizeB | RightRdwr | UseCarry},
|
||||
[ASETPC]= {SizeB | RightRdwr | UseCarry},
|
||||
[ASETPL]= {SizeB | RightRdwr | UseCarry},
|
||||
[ASETPS]= {SizeB | RightRdwr | UseCarry},
|
||||
|
||||
[ASHLB]= {SizeB | LeftRead | RightRdwr | ShiftCX | SetCarry},
|
||||
[ASHLL]= {SizeL | LeftRead | RightRdwr | ShiftCX | SetCarry},
|
||||
[ASHLW]= {SizeW | LeftRead | RightRdwr | ShiftCX | SetCarry},
|
||||
|
||||
[ASHRB]= {SizeB | LeftRead | RightRdwr | ShiftCX | SetCarry},
|
||||
[ASHRL]= {SizeL | LeftRead | RightRdwr | ShiftCX | SetCarry},
|
||||
[ASHRW]= {SizeW | LeftRead | RightRdwr | ShiftCX | SetCarry},
|
||||
|
||||
[ASTOSB]= {OK, AX|DI, DI},
|
||||
[ASTOSL]= {OK, AX|DI, DI},
|
||||
[ASTOSW]= {OK, AX|DI, DI},
|
||||
|
||||
[ASUBB]= {SizeB | LeftRead | RightRdwr | SetCarry},
|
||||
[ASUBL]= {SizeL | LeftRead | RightRdwr | SetCarry},
|
||||
[ASUBW]= {SizeW | LeftRead | RightRdwr | SetCarry},
|
||||
|
||||
[ASUBSD]= {SizeD | LeftRead | RightRdwr},
|
||||
[ASUBSS]= {SizeF | LeftRead | RightRdwr},
|
||||
|
||||
[ATESTB]= {SizeB | LeftRead | RightRead},
|
||||
[ATESTL]= {SizeL | LeftRead | RightRead},
|
||||
[ATESTW]= {SizeW | LeftRead | RightRead},
|
||||
|
||||
[AUCOMISD]= {SizeD | LeftRead | RightRead},
|
||||
[AUCOMISS]= {SizeF | LeftRead | RightRead},
|
||||
|
||||
[AUNDEF]= {OK},
|
||||
|
||||
[AUSEFIELD]= {OK},
|
||||
|
||||
[AXCHGB]= {SizeB | LeftRdwr | RightRdwr},
|
||||
[AXCHGL]= {SizeL | LeftRdwr | RightRdwr},
|
||||
[AXCHGW]= {SizeW | LeftRdwr | RightRdwr},
|
||||
|
||||
[AXORB]= {SizeB | LeftRead | RightRdwr | SetCarry},
|
||||
[AXORL]= {SizeL | LeftRead | RightRdwr | SetCarry},
|
||||
[AXORW]= {SizeW | LeftRead | RightRdwr | SetCarry},
|
||||
};
|
||||
|
||||
void
|
||||
proginfo(ProgInfo *info, Prog *p)
|
||||
{
|
||||
*info = progtable[p->as];
|
||||
if(info->flags == 0)
|
||||
fatal("unknown instruction %P", p);
|
||||
|
||||
if((info->flags & ShiftCX) && p->from.type != D_CONST)
|
||||
info->reguse |= CX;
|
||||
|
||||
if(info->flags & ImulAXDX) {
|
||||
if(p->to.type == D_NONE) {
|
||||
info->reguse |= AX;
|
||||
info->regset |= AX | DX;
|
||||
} else {
|
||||
info->flags |= RightRdwr;
|
||||
}
|
||||
}
|
||||
|
||||
// Addressing makes some registers used.
|
||||
if(p->from.type >= D_INDIR)
|
||||
info->regindex |= RtoB(p->from.type-D_INDIR);
|
||||
if(p->from.index != D_NONE)
|
||||
info->regindex |= RtoB(p->from.index);
|
||||
if(p->to.type >= D_INDIR)
|
||||
info->regindex |= RtoB(p->to.type-D_INDIR);
|
||||
if(p->to.index != D_NONE)
|
||||
info->regindex |= RtoB(p->to.index);
|
||||
}
|
||||
317
src/cmd/8g/reg.c
317
src/cmd/8g/reg.c
@ -131,6 +131,7 @@ regopt(Prog *firstp)
|
||||
{
|
||||
Reg *r, *r1;
|
||||
Prog *p;
|
||||
ProgInfo info, info2;
|
||||
int i, z, nr;
|
||||
uint32 vreg;
|
||||
Bits bit;
|
||||
@ -190,14 +191,9 @@ regopt(Prog *firstp)
|
||||
*/
|
||||
nr = 0;
|
||||
for(p=firstp; p!=P; p=p->link) {
|
||||
switch(p->as) {
|
||||
case ADATA:
|
||||
case AGLOBL:
|
||||
case ANAME:
|
||||
case ASIGNAME:
|
||||
case ATYPE:
|
||||
proginfo(&info, p);
|
||||
if(info.flags & Skip)
|
||||
continue;
|
||||
}
|
||||
r = rega();
|
||||
nr++;
|
||||
if(firstr == R) {
|
||||
@ -214,10 +210,8 @@ regopt(Prog *firstp)
|
||||
|
||||
r1 = r->p1;
|
||||
if(r1 != R) {
|
||||
switch(r1->prog->as) {
|
||||
case ARET:
|
||||
case AJMP:
|
||||
case AIRETL:
|
||||
proginfo(&info2, r1->prog);
|
||||
if(info2.flags & Break) {
|
||||
r->p1 = R;
|
||||
r1->s1 = R;
|
||||
}
|
||||
@ -227,302 +221,31 @@ regopt(Prog *firstp)
|
||||
if(p->as == ACALL && p->to.type == D_EXTERN)
|
||||
continue;
|
||||
|
||||
// Addressing makes some registers used.
|
||||
if(p->from.type >= D_INDIR)
|
||||
r->use1.b[0] |= RtoB(p->from.type-D_INDIR);
|
||||
if(p->from.index != D_NONE)
|
||||
r->use1.b[0] |= RtoB(p->from.index);
|
||||
if(p->to.type >= D_INDIR)
|
||||
r->use2.b[0] |= RtoB(p->to.type-D_INDIR);
|
||||
if(p->to.index != D_NONE)
|
||||
r->use2.b[0] |= RtoB(p->to.index);
|
||||
r->use1.b[0] |= info.reguse | info.regindex;
|
||||
r->set.b[0] |= info.regset;
|
||||
|
||||
bit = mkvar(r, &p->from);
|
||||
if(bany(&bit))
|
||||
switch(p->as) {
|
||||
/*
|
||||
* funny
|
||||
*/
|
||||
case ALEAL:
|
||||
case AFMOVD:
|
||||
case AFMOVF:
|
||||
case AFMOVL:
|
||||
case AFMOVW:
|
||||
case AFMOVV:
|
||||
if(bany(&bit)) {
|
||||
if(info.flags & LeftAddr)
|
||||
setaddrs(bit);
|
||||
break;
|
||||
|
||||
/*
|
||||
* left side read
|
||||
*/
|
||||
default:
|
||||
if(info.flags & LeftRead)
|
||||
for(z=0; z<BITS; z++)
|
||||
r->use1.b[z] |= bit.b[z];
|
||||
break;
|
||||
|
||||
/*
|
||||
* left side read+write
|
||||
*/
|
||||
case AXCHGB:
|
||||
case AXCHGW:
|
||||
case AXCHGL:
|
||||
for(z=0; z<BITS; z++) {
|
||||
r->use1.b[z] |= bit.b[z];
|
||||
if(info.flags & LeftWrite)
|
||||
for(z=0; z<BITS; z++)
|
||||
r->set.b[z] |= bit.b[z];
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
bit = mkvar(r, &p->to);
|
||||
if(bany(&bit))
|
||||
switch(p->as) {
|
||||
default:
|
||||
yyerror("reg: unknown op: %A", p->as);
|
||||
break;
|
||||
|
||||
/*
|
||||
* right side read
|
||||
*/
|
||||
case ACMPB:
|
||||
case ACMPL:
|
||||
case ACMPW:
|
||||
case ACOMISS:
|
||||
case ACOMISD:
|
||||
case AUCOMISS:
|
||||
case AUCOMISD:
|
||||
case ATESTB:
|
||||
case ATESTL:
|
||||
case ATESTW:
|
||||
for(z=0; z<BITS; z++)
|
||||
r->use2.b[z] |= bit.b[z];
|
||||
break;
|
||||
|
||||
/*
|
||||
* right side write
|
||||
*/
|
||||
case AFSTSW:
|
||||
case ALEAL:
|
||||
case ANOP:
|
||||
case AMOVL:
|
||||
case AMOVB:
|
||||
case AMOVW:
|
||||
case AMOVBLSX:
|
||||
case AMOVBLZX:
|
||||
case AMOVBWSX:
|
||||
case AMOVBWZX:
|
||||
case AMOVWLSX:
|
||||
case AMOVWLZX:
|
||||
case APOPL:
|
||||
|
||||
case AMOVSS:
|
||||
case AMOVSD:
|
||||
case ACVTSD2SL:
|
||||
case ACVTSD2SS:
|
||||
case ACVTSL2SD:
|
||||
case ACVTSL2SS:
|
||||
case ACVTSS2SD:
|
||||
case ACVTSS2SL:
|
||||
case ACVTTSD2SL:
|
||||
case ACVTTSS2SL:
|
||||
for(z=0; z<BITS; z++)
|
||||
r->set.b[z] |= bit.b[z];
|
||||
break;
|
||||
|
||||
/*
|
||||
* right side read+write
|
||||
*/
|
||||
case AINCB:
|
||||
case AINCL:
|
||||
case AINCW:
|
||||
case ADECB:
|
||||
case ADECL:
|
||||
case ADECW:
|
||||
|
||||
case AADDB:
|
||||
case AADDL:
|
||||
case AADDW:
|
||||
case AANDB:
|
||||
case AANDL:
|
||||
case AANDW:
|
||||
case ASUBB:
|
||||
case ASUBL:
|
||||
case ASUBW:
|
||||
case AORB:
|
||||
case AORL:
|
||||
case AORW:
|
||||
case AXORB:
|
||||
case AXORL:
|
||||
case AXORW:
|
||||
case ASALB:
|
||||
case ASALL:
|
||||
case ASALW:
|
||||
case ASARB:
|
||||
case ASARL:
|
||||
case ASARW:
|
||||
case ARCLB:
|
||||
case ARCLL:
|
||||
case ARCLW:
|
||||
case ARCRB:
|
||||
case ARCRL:
|
||||
case ARCRW:
|
||||
case AROLB:
|
||||
case AROLL:
|
||||
case AROLW:
|
||||
case ARORB:
|
||||
case ARORL:
|
||||
case ARORW:
|
||||
case ASHLB:
|
||||
case ASHLL:
|
||||
case ASHLW:
|
||||
case ASHRB:
|
||||
case ASHRL:
|
||||
case ASHRW:
|
||||
case AIMULL:
|
||||
case AIMULW:
|
||||
case ANEGB:
|
||||
case ANEGL:
|
||||
case ANEGW:
|
||||
case ANOTB:
|
||||
case ANOTL:
|
||||
case ANOTW:
|
||||
case AADCL:
|
||||
case ASBBL:
|
||||
|
||||
case ASETCC:
|
||||
case ASETCS:
|
||||
case ASETEQ:
|
||||
case ASETGE:
|
||||
case ASETGT:
|
||||
case ASETHI:
|
||||
case ASETLE:
|
||||
case ASETLS:
|
||||
case ASETLT:
|
||||
case ASETMI:
|
||||
case ASETNE:
|
||||
case ASETOC:
|
||||
case ASETOS:
|
||||
case ASETPC:
|
||||
case ASETPL:
|
||||
case ASETPS:
|
||||
|
||||
case AXCHGB:
|
||||
case AXCHGW:
|
||||
case AXCHGL:
|
||||
|
||||
case AADDSD:
|
||||
case AADDSS:
|
||||
case ACMPSD:
|
||||
case ACMPSS:
|
||||
case ADIVSD:
|
||||
case ADIVSS:
|
||||
case AMAXSD:
|
||||
case AMAXSS:
|
||||
case AMINSD:
|
||||
case AMINSS:
|
||||
case AMULSD:
|
||||
case AMULSS:
|
||||
case ARCPSS:
|
||||
case ARSQRTSS:
|
||||
case ASQRTSD:
|
||||
case ASQRTSS:
|
||||
case ASUBSD:
|
||||
case ASUBSS:
|
||||
case AXORPD:
|
||||
for(z=0; z<BITS; z++) {
|
||||
r->set.b[z] |= bit.b[z];
|
||||
r->use2.b[z] |= bit.b[z];
|
||||
}
|
||||
break;
|
||||
|
||||
/*
|
||||
* funny
|
||||
*/
|
||||
case AFMOVDP:
|
||||
case AFMOVFP:
|
||||
case AFMOVLP:
|
||||
case AFMOVVP:
|
||||
case AFMOVWP:
|
||||
case ACALL:
|
||||
if(bany(&bit)) {
|
||||
if(info.flags & RightAddr)
|
||||
setaddrs(bit);
|
||||
break;
|
||||
}
|
||||
|
||||
switch(p->as) {
|
||||
case AIMULL:
|
||||
case AIMULW:
|
||||
if(p->to.type != D_NONE)
|
||||
break;
|
||||
|
||||
case AIDIVL:
|
||||
case AIDIVW:
|
||||
case ADIVL:
|
||||
case ADIVW:
|
||||
case AMULL:
|
||||
case AMULW:
|
||||
r->set.b[0] |= RtoB(D_AX) | RtoB(D_DX);
|
||||
r->use1.b[0] |= RtoB(D_AX) | RtoB(D_DX);
|
||||
break;
|
||||
|
||||
case AIDIVB:
|
||||
case AIMULB:
|
||||
case ADIVB:
|
||||
case AMULB:
|
||||
r->set.b[0] |= RtoB(D_AX);
|
||||
r->use1.b[0] |= RtoB(D_AX);
|
||||
break;
|
||||
|
||||
case ACWD:
|
||||
r->set.b[0] |= RtoB(D_AX) | RtoB(D_DX);
|
||||
r->use1.b[0] |= RtoB(D_AX);
|
||||
break;
|
||||
|
||||
case ACDQ:
|
||||
r->set.b[0] |= RtoB(D_DX);
|
||||
r->use1.b[0] |= RtoB(D_AX);
|
||||
break;
|
||||
|
||||
case AREP:
|
||||
case AREPN:
|
||||
case ALOOP:
|
||||
case ALOOPEQ:
|
||||
case ALOOPNE:
|
||||
r->set.b[0] |= RtoB(D_CX);
|
||||
r->use1.b[0] |= RtoB(D_CX);
|
||||
break;
|
||||
|
||||
case AMOVSB:
|
||||
case AMOVSL:
|
||||
case AMOVSW:
|
||||
case ACMPSB:
|
||||
case ACMPSL:
|
||||
case ACMPSW:
|
||||
r->set.b[0] |= RtoB(D_SI) | RtoB(D_DI);
|
||||
r->use1.b[0] |= RtoB(D_SI) | RtoB(D_DI);
|
||||
break;
|
||||
|
||||
case ASTOSB:
|
||||
case ASTOSL:
|
||||
case ASTOSW:
|
||||
case ASCASB:
|
||||
case ASCASL:
|
||||
case ASCASW:
|
||||
r->set.b[0] |= RtoB(D_DI);
|
||||
r->use1.b[0] |= RtoB(D_AX) | RtoB(D_DI);
|
||||
break;
|
||||
|
||||
case AINSB:
|
||||
case AINSL:
|
||||
case AINSW:
|
||||
r->set.b[0] |= RtoB(D_DX) | RtoB(D_DI);
|
||||
r->use1.b[0] |= RtoB(D_DI);
|
||||
break;
|
||||
|
||||
case AOUTSB:
|
||||
case AOUTSL:
|
||||
case AOUTSW:
|
||||
r->set.b[0] |= RtoB(D_DI);
|
||||
r->use1.b[0] |= RtoB(D_DX) | RtoB(D_DI);
|
||||
break;
|
||||
if(info.flags & RightRead)
|
||||
for(z=0; z<BITS; z++)
|
||||
r->use2.b[z] |= bit.b[z];
|
||||
if(info.flags & RightWrite)
|
||||
for(z=0; z<BITS; z++)
|
||||
r->set.b[z] |= bit.b[z];
|
||||
}
|
||||
}
|
||||
if(firstr == R)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user