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cmd/internal/obj/riscv: improve register MOVB/MOVH/MOVBU/MOVHU for rva22u64

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When GORISCV64 enables rva22u64, use SEXTB for MOVB, SEXTH for MOVH, ZEXTH
for MOVHU and ADDUW for MOVWU. These are single instruction alternatives
to the two instruction shift sequences that are needed otherwise.

Change-Id: Iea5e394f57e238ae8771400a87287c1ee507d44c
Reviewed-on: https://go-review.googlesource.com/c/go/+/572736
Reviewed-by: David Chase <drchase@google.com>
Run-TryBot: Joel Sing <joel@sing.id.au>
Reviewed-by: Mark Ryan <markdryan@rivosinc.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
TryBot-Result: Gopher Robot <gobot@golang.org>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Reviewed-by: M Zhuo <mengzhuo1203@gmail.com>
This commit is contained in:
Joel Sing 2023-12-09 19:18:00 +11:00
parent ac0b2f95a5
commit a6ecdf29e3
2 changed files with 37 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/cmd/asm/internal/asm/testdata/riscv64.s vendored
View File

@ -462,12 +462,12 @@ start:
MOVW X5, (X6) // 23205300
MOVW X5, 4(X6) // 23225300
MOVB X5, X6 // 1393820313538343
MOVH X5, X6 // 1393020313530343
MOVB X5, X6 // 1393820313538343 or 13934260
MOVH X5, X6 // 1393020313530343 or 13935260
MOVW X5, X6 // 1b830200
MOVBU X5, X6 // 13f3f20f
MOVHU X5, X6 // 1393020313530303
MOVWU X5, X6 // 1393020213530302
MOVHU X5, X6 // 1393020313530303 or 3bc30208
MOVWU X5, X6 // 1393020213530302 or 3b830208
MOVF 4(X5), F0 // 07a04200
MOVF F0, 4(X5) // 27a20200

49
src/cmd/internal/obj/riscv/obj.go
View File

@ -26,6 +26,7 @@ import (
"cmd/internal/sys"
"fmt"
"internal/abi"
"internal/buildcfg"
"log"
"math/bits"
"strings"
@ -2157,25 +2158,41 @@ func instructionsForMOV(p *obj.Prog) []*instruction {
case AMOVD: // MOVD Ra, Rb -> FSGNJD Ra, Ra, Rb
ins.as, ins.rs1 = AFSGNJD, uint32(p.From.Reg)
case AMOVB, AMOVH:
// Use SLLI/SRAI to extend.
ins.as, ins.rs1, ins.rs2 = ASLLI, uint32(p.From.Reg), obj.REG_NONE
if p.As == AMOVB {
ins.imm = 56
} else if p.As == AMOVH {
ins.imm = 48
if buildcfg.GORISCV64 >= 22 {
// Use SEXTB or SEXTH to extend.
ins.as, ins.rs1, ins.rs2 = ASEXTB, uint32(p.From.Reg), obj.REG_NONE
if p.As == AMOVH {
ins.as = ASEXTH
}
} else {
// Use SLLI/SRAI sequence to extend.
ins.as, ins.rs1, ins.rs2 = ASLLI, uint32(p.From.Reg), obj.REG_NONE
if p.As == AMOVB {
ins.imm = 56
} else if p.As == AMOVH {
ins.imm = 48
}
ins2 := &instruction{as: ASRAI, rd: ins.rd, rs1: ins.rd, imm: ins.imm}
inss = append(inss, ins2)
}
ins2 := &instruction{as: ASRAI, rd: ins.rd, rs1: ins.rd, imm: ins.imm}
inss = append(inss, ins2)
case AMOVHU, AMOVWU:
// Use SLLI/SRLI to extend.
ins.as, ins.rs1, ins.rs2 = ASLLI, uint32(p.From.Reg), obj.REG_NONE
if p.As == AMOVHU {
ins.imm = 48
} else if p.As == AMOVWU {
ins.imm = 32
if buildcfg.GORISCV64 >= 22 {
// Use ZEXTH or ADDUW to extend.
ins.as, ins.rs1, ins.rs2, ins.imm = AZEXTH, uint32(p.From.Reg), obj.REG_NONE, 0
if p.As == AMOVWU {
ins.as, ins.rs2 = AADDUW, REG_ZERO
}
} else {
// Use SLLI/SRLI sequence to extend.
ins.as, ins.rs1, ins.rs2 = ASLLI, uint32(p.From.Reg), obj.REG_NONE
if p.As == AMOVHU {
ins.imm = 48
} else if p.As == AMOVWU {
ins.imm = 32
}
ins2 := &instruction{as: ASRLI, rd: ins.rd, rs1: ins.rd, imm: ins.imm}
inss = append(inss, ins2)
}
ins2 := &instruction{as: ASRLI, rd: ins.rd, rs1: ins.rd, imm: ins.imm}
inss = append(inss, ins2)
}
case p.From.Type == obj.TYPE_MEM && p.To.Type == obj.TYPE_REG: