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cmd/compile,bytealg: change context register on riscv64

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The register ABI will use X8-X23 (CL 356519),
this CL changes context register from X20(S4) to X26(S10) to meet the
prerequisite.

Update #40724

Change-Id: I93d51d22fe7b3ea5ceffe96dff93e3af60fbe7f6
Reviewed-on: https://go-review.googlesource.com/c/go/+/357974
Trust: mzh <mzh@golangcn.org>
Run-TryBot: mzh <mzh@golangcn.org>
Reviewed-by: Joel Sing <joel@sing.id.au>
Reviewed-by: Cherry Mui <cherryyz@google.com>
TryBot-Result: Gopher Robot <gobot@golang.org>
This commit is contained in:
Meng Zhuo 2021-10-22 14:36:06 +08:00 committed by mzh
parent 3a5e3d8173
commit 9faef5a654
5 changed files with 9 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/cmd/compile/internal/riscv64/ssa.go
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@ -648,7 +648,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
}
case ssa.OpRISCV64LoweredGetClosurePtr:
// Closure pointer is S4 (riscv.REG_CTXT).
// Closure pointer is S10 (riscv.REG_CTXT).
ssagen.CheckLoweredGetClosurePtr(v)
case ssa.OpRISCV64LoweredGetCallerSP:

4
src/cmd/compile/internal/ssa/gen/RISCV64Ops.go
View File

@ -26,7 +26,7 @@ import (
const (
riscv64REG_G = 27
riscv64REG_CTXT = 20
riscv64REG_CTXT = 26
riscv64REG_LR = 1
riscv64REG_SP = 2
riscv64REG_GP = 3
@ -115,7 +115,7 @@ func init() {
panic("Too many RISCV64 registers")
}
regCtxt := regNamed["X20"]
regCtxt := regNamed["X26"]
callerSave := gpMask | fpMask | regNamed["g"]
var (

4
src/cmd/compile/internal/ssa/opGen.go
View File

@ -28898,7 +28898,7 @@ var opcodeTable = [...]opInfo{
call: true,
reg: regInfo{
inputs: []inputInfo{
{1, 524288}, // X20
{1, 33554432}, // X26
{0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
},
clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
@ -29189,7 +29189,7 @@ var opcodeTable = [...]opInfo{
argLen: 0,
reg: regInfo{
outputs: []outputInfo{
{0, 524288}, // X20
{0, 33554432}, // X26
},
},
},

6
src/cmd/internal/obj/riscv/cpu.go
View File

@ -125,13 +125,13 @@ const (
REG_A7 = REG_X17
REG_S2 = REG_X18
REG_S3 = REG_X19
REG_S4 = REG_X20 // aka REG_CTXT
REG_S4 = REG_X20
REG_S5 = REG_X21
REG_S6 = REG_X22
REG_S7 = REG_X23
REG_S8 = REG_X24
REG_S9 = REG_X25
REG_S10 = REG_X26
REG_S10 = REG_X26 // aka REG_CTXT
REG_S11 = REG_X27 // aka REG_G
REG_T3 = REG_X28
REG_T4 = REG_X29
@ -139,8 +139,8 @@ const (
REG_T6 = REG_X31 // aka REG_TMP
// Go runtime register names.
REG_CTXT = REG_S10 // Context for closures.
REG_G = REG_S11 // G pointer.
REG_CTXT = REG_S4 // Context for closures.
REG_LR = REG_RA // Link register.
REG_TMP = REG_T6 // Reserved for assembler use.

2
src/internal/bytealg/equal_riscv64.s
View File

@ -5,7 +5,7 @@
#include "go_asm.h"
#include "textflag.h"
#define CTXT S4
#define CTXT S10
// func memequal(a, b unsafe.Pointer, size uintptr) bool
TEXT runtime·memequal(SB),NOSPLIT|NOFRAME,$0-25