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Revert "cmd/internal/obj/arm64, cmd/link: use two instructions rather than three for loads from memory"
This reverts commit 3a9bc571b0.
Breaks darwin/arm64.
Change-Id: Ib958beacabca48020a6a47332fbdec99d994060b
Reviewed-on: https://go-review.googlesource.com/16906
Reviewed-by: Michael Hudson-Doyle <michael.hudson@canonical.com>
This commit is contained in:
David Crawshaw
parent
a734a8550a
commit
9958a7b563
@ -260,16 +260,16 @@ var optab = []Optab{
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{AMOVW, C_VCONADDR, C_NONE, C_REG, 68, 8, 0, 0, 0},
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{AMOVD, C_VCON, C_NONE, C_REG, 12, 4, 0, LFROM, 0},
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{AMOVD, C_VCONADDR, C_NONE, C_REG, 68, 8, 0, 0, 0},
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{AMOVB, C_REG, C_NONE, C_ADDR, 64, 8, 0, 0, 0},
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{AMOVBU, C_REG, C_NONE, C_ADDR, 64, 8, 0, 0, 0},
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{AMOVH, C_REG, C_NONE, C_ADDR, 64, 8, 0, 0, 0},
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{AMOVW, C_REG, C_NONE, C_ADDR, 64, 8, 0, 0, 0},
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{AMOVD, C_REG, C_NONE, C_ADDR, 64, 8, 0, 0, 0},
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{AMOVB, C_ADDR, C_NONE, C_REG, 65, 8, 0, 0, 0},
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{AMOVBU, C_ADDR, C_NONE, C_REG, 65, 8, 0, 0, 0},
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{AMOVH, C_ADDR, C_NONE, C_REG, 65, 8, 0, 0, 0},
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{AMOVW, C_ADDR, C_NONE, C_REG, 65, 8, 0, 0, 0},
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{AMOVD, C_ADDR, C_NONE, C_REG, 65, 8, 0, 0, 0},
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{AMOVB, C_REG, C_NONE, C_ADDR, 64, 12, 0, 0, 0},
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{AMOVBU, C_REG, C_NONE, C_ADDR, 64, 12, 0, 0, 0},
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{AMOVH, C_REG, C_NONE, C_ADDR, 64, 12, 0, 0, 0},
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{AMOVW, C_REG, C_NONE, C_ADDR, 64, 12, 0, 0, 0},
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{AMOVD, C_REG, C_NONE, C_ADDR, 64, 12, 0, 0, 0},
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{AMOVB, C_ADDR, C_NONE, C_REG, 65, 12, 0, 0, 0},
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{AMOVBU, C_ADDR, C_NONE, C_REG, 65, 12, 0, 0, 0},
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{AMOVH, C_ADDR, C_NONE, C_REG, 65, 12, 0, 0, 0},
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{AMOVW, C_ADDR, C_NONE, C_REG, 65, 12, 0, 0, 0},
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{AMOVD, C_ADDR, C_NONE, C_REG, 65, 12, 0, 0, 0},
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{AMOVD, C_TLS_LE, C_NONE, C_REG, 69, 4, 0, 0, 0},
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{AMOVD, C_TLS_IE, C_NONE, C_REG, 70, 8, 0, 0, 0},
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{AMUL, C_REG, C_REG, C_REG, 15, 4, 0, 0, 0},
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@ -450,10 +450,10 @@ var optab = []Optab{
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{AFMOVS, C_LOREG, C_NONE, C_FREG, 31, 8, 0, LFROM, 0},
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{AFMOVD, C_LAUTO, C_NONE, C_FREG, 31, 8, REGSP, LFROM, 0},
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{AFMOVD, C_LOREG, C_NONE, C_FREG, 31, 8, 0, LFROM, 0},
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{AFMOVS, C_FREG, C_NONE, C_ADDR, 64, 8, 0, 0, 0},
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{AFMOVS, C_ADDR, C_NONE, C_FREG, 65, 8, 0, 0, 0},
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{AFMOVD, C_FREG, C_NONE, C_ADDR, 64, 8, 0, 0, 0},
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{AFMOVD, C_ADDR, C_NONE, C_FREG, 65, 8, 0, 0, 0},
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{AFMOVS, C_FREG, C_NONE, C_ADDR, 64, 12, 0, 0, 0},
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{AFMOVS, C_ADDR, C_NONE, C_FREG, 65, 12, 0, 0, 0},
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{AFMOVD, C_FREG, C_NONE, C_ADDR, 64, 12, 0, 0, 0},
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{AFMOVD, C_ADDR, C_NONE, C_FREG, 65, 12, 0, 0, 0},
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{AFADDS, C_FREG, C_NONE, C_FREG, 54, 4, 0, 0, 0},
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{AFADDS, C_FREG, C_FREG, C_FREG, 54, 4, 0, 0, 0},
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{AFADDS, C_FCON, C_NONE, C_FREG, 54, 4, 0, 0, 0},
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@ -2701,26 +2701,28 @@ func asmout(ctxt *obj.Link, p *obj.Prog, o *Optab, out []uint32) {
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o1 = ADR(0, uint32(d), uint32(p.To.Reg))
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/* reloc ops */
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/* reloc ops */
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case 64: /* movT R,addr -> adrp + add + movT R, (REGTMP) */
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o1 = ADR(1, 0, REGTMP)
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o2 = olsr12u(ctxt, int32(opstr12(ctxt, int(p.As))), 0, REGTMP, int(p.From.Reg))
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o2 = opirr(ctxt, AADD) | REGTMP&31<<5 | REGTMP&31
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rel := obj.Addrel(ctxt.Cursym)
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rel.Off = int32(ctxt.Pc)
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rel.Siz = 8
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rel.Sym = p.To.Sym
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rel.Add = p.To.Offset
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rel.Type = movereloc(p.As)
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rel.Type = obj.R_ADDRARM64
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o3 = olsr12u(ctxt, int32(opstr12(ctxt, int(p.As))), 0, REGTMP, int(p.From.Reg))
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case 65: /* movT addr,R -> adrp REGTMP, 0; ldr R, [REGTMP, #0] + relocs */
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case 65: /* movT addr,R -> adrp + add + movT (REGTMP), R */
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o1 = ADR(1, 0, REGTMP)
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o2 = olsr12u(ctxt, int32(opldr12(ctxt, int(p.As))), 0, REGTMP, int(p.To.Reg))
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o2 = opirr(ctxt, AADD) | REGTMP&31<<5 | REGTMP&31
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rel := obj.Addrel(ctxt.Cursym)
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rel.Off = int32(ctxt.Pc)
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rel.Siz = 8
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rel.Sym = p.From.Sym
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rel.Add = p.From.Offset
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rel.Siz = 8
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rel.Type = movereloc(p.As)
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rel.Type = obj.R_ADDRARM64
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o3 = olsr12u(ctxt, int32(opldr12(ctxt, int(p.As))), 0, REGTMP, int(p.To.Reg))
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case 66: /* ldp O(R)!, (r1, r2); ldp (R)O!, (r1, r2) */
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v := int32(p.From.Offset)
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@ -4159,19 +4161,3 @@ func movesize(a int) int {
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return -1
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}
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}
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func movereloc(a int16) int32 {
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switch movesize(int(a)) {
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case 0:
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return obj.R_ARM64_LOAD8
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case 1:
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return obj.R_ARM64_LOAD16
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case 2:
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return obj.R_ARM64_LOAD32
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case 3:
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return obj.R_ARM64_LOAD64
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case -1:
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panic("xxx")
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}
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return -1
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}
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@ -467,11 +467,6 @@ const (
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// referenced (thread local) symbol from the GOT.
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R_ARM64_TLS_IE
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R_ARM64_LOAD8
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R_ARM64_LOAD16
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R_ARM64_LOAD32
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R_ARM64_LOAD64
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// PPC64.
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// R_POWER_TLS_LE is used to implement the "local exec" model for tls
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@ -133,30 +133,6 @@ func elfreloc1(r *ld.Reloc, sectoff int64) int {
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ld.Thearch.Vput(uint64(sectoff + 4))
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ld.Thearch.Vput(ld.R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC | uint64(elfsym)<<32)
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case obj.R_ARM64_LOAD8:
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ld.Thearch.Vput(ld.R_AARCH64_ADR_PREL_PG_HI21 | uint64(elfsym)<<32)
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ld.Thearch.Vput(uint64(r.Xadd))
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ld.Thearch.Vput(uint64(sectoff + 4))
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ld.Thearch.Vput(ld.R_AARCH64_LDST8_ABS_LO12_NC | uint64(elfsym)<<32)
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case obj.R_ARM64_LOAD16:
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ld.Thearch.Vput(ld.R_AARCH64_ADR_PREL_PG_HI21 | uint64(elfsym)<<32)
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ld.Thearch.Vput(uint64(r.Xadd))
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ld.Thearch.Vput(uint64(sectoff + 4))
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ld.Thearch.Vput(ld.R_AARCH64_LDST16_ABS_LO12_NC | uint64(elfsym)<<32)
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case obj.R_ARM64_LOAD32:
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ld.Thearch.Vput(ld.R_AARCH64_ADR_PREL_PG_HI21 | uint64(elfsym)<<32)
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ld.Thearch.Vput(uint64(r.Xadd))
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ld.Thearch.Vput(uint64(sectoff + 4))
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ld.Thearch.Vput(ld.R_AARCH64_LDST32_ABS_LO12_NC | uint64(elfsym)<<32)
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case obj.R_ARM64_LOAD64:
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ld.Thearch.Vput(ld.R_AARCH64_ADR_PREL_PG_HI21 | uint64(elfsym)<<32)
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ld.Thearch.Vput(uint64(r.Xadd))
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ld.Thearch.Vput(uint64(sectoff + 4))
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ld.Thearch.Vput(ld.R_AARCH64_LDST64_ABS_LO12_NC | uint64(elfsym)<<32)
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case obj.R_CALLARM64:
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if r.Siz != 4 {
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return -1
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@ -253,72 +229,13 @@ func machoreloc1(r *ld.Reloc, sectoff int64) int {
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return 0
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}
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func archrelocaddr(r *ld.Reloc, s *ld.LSym, val *int64) int {
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var o1, o2 uint32
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if ld.Ctxt.Arch.ByteOrder == binary.BigEndian {
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o1 = uint32(*val >> 32)
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o2 = uint32(*val)
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} else {
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o1 = uint32(*val)
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o2 = uint32(*val >> 32)
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}
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// We are inserting an address into two instructions: adrp and
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// then either addi or a load.
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address := ld.Symaddr(r.Sym) + r.Add
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pgaddress := (address &^ 0xfff) - ((s.Value + int64(r.Off)) &^ 0xfff)
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if pgaddress < -1<<31 || pgaddress >= 1<<31 {
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ld.Ctxt.Diag("relocation for %s is too big (>=2G): %d", s.Name, pgaddress)
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}
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pgoff := uint32(address & 0xfff)
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o1 |= uint32((((pgaddress >> 12) & 3) << 29) | (((pgaddress >> 12 >> 2) & 0x7ffff) << 5))
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switch r.Type {
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case obj.R_ADDRARM64, obj.R_ARM64_LOAD8:
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o2 |= pgoff << 10
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case obj.R_ARM64_LOAD16:
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if pgoff&0x1 != 0 {
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ld.Diag("offset for 16-byte load/store has unaligned value %d", pgoff)
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}
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o2 |= pgoff << 9
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case obj.R_ARM64_LOAD32:
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if pgoff&0x3 != 0 {
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ld.Diag("offset for 32-byte load/store has unaligned value %d", pgoff)
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}
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o2 |= pgoff << 8
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case obj.R_ARM64_LOAD64:
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if pgoff&0x7 != 0 {
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ld.Diag("offset for 64-byte load/store has unaligned value %d", pgoff)
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}
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o2 |= pgoff << 7
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default:
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return -1
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}
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if ld.Ctxt.Arch.ByteOrder == binary.BigEndian {
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*val = int64(o1)<<32 | int64(o2)
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} else {
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*val = int64(o2)<<32 | int64(o1)
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}
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return 0
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}
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func archreloc(r *ld.Reloc, s *ld.LSym, val *int64) int {
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if ld.Linkmode == ld.LinkExternal {
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switch r.Type {
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default:
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return -1
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case obj.R_ADDRARM64,
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obj.R_ARM64_LOAD8,
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obj.R_ARM64_LOAD16,
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obj.R_ARM64_LOAD32,
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obj.R_ARM64_LOAD64:
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case obj.R_ADDRARM64:
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r.Done = 0
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// set up addend for eventual relocation via outer symbol.
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@ -387,8 +304,32 @@ func archreloc(r *ld.Reloc, s *ld.LSym, val *int64) int {
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*val = ld.Symaddr(r.Sym) + r.Add - ld.Symaddr(ld.Linklookup(ld.Ctxt, ".got", 0))
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return 0
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case obj.R_ADDRARM64, obj.R_ARM64_LOAD8, obj.R_ARM64_LOAD16, obj.R_ARM64_LOAD32, obj.R_ARM64_LOAD64:
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return archrelocaddr(r, s, val)
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case obj.R_ADDRARM64:
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t := ld.Symaddr(r.Sym) + r.Add - ((s.Value + int64(r.Off)) &^ 0xfff)
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if t >= 1<<32 || t < -1<<32 {
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ld.Diag("program too large, address relocation distance = %d", t)
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}
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var o0, o1 uint32
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if ld.Ctxt.Arch.ByteOrder == binary.BigEndian {
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o0 = uint32(*val >> 32)
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o1 = uint32(*val)
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} else {
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o0 = uint32(*val)
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o1 = uint32(*val >> 32)
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}
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o0 |= (uint32((t>>12)&3) << 29) | (uint32((t>>12>>2)&0x7ffff) << 5)
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o1 |= uint32(t&0xfff) << 10
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// when laid out, the instruction order must always be o1, o2.
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if ld.Ctxt.Arch.ByteOrder == binary.BigEndian {
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*val = int64(o0)<<32 | int64(o1)
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} else {
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*val = int64(o1)<<32 | int64(o0)
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}
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return 0
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case obj.R_ARM64_TLS_LE:
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r.Done = 0
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@ -372,10 +372,6 @@ const (
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R_AARCH64_CALL26 = 283
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R_AARCH64_ADR_PREL_PG_HI21 = 275
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R_AARCH64_ADD_ABS_LO12_NC = 277
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R_AARCH64_LDST8_ABS_LO12_NC = 278
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R_AARCH64_LDST16_ABS_LO12_NC = 284
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R_AARCH64_LDST32_ABS_LO12_NC = 285
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R_AARCH64_LDST64_ABS_LO12_NC = 286
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R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 = 541
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R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC = 542
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R_AARCH64_TLSLE_MOVW_TPREL_G0 = 547
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