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sync/atomic: add memory barriers to Load/StoreInt32 on darwin/arm

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After switching to an iPhone 5 for the darwin/arm builds,
TestStoreLoadRelAcq32 started to timeout on every builder run.
Adding the same memory barriers as armLoadUint64 and armStoreUint64
makes the test complete successfully.

Fixes sync/atomic tests on the darwin/arm builder.

Change-Id: Id73de31679304e259bdbd7f2f94383ae7fd70ee4
Reviewed-on: https://go-review.googlesource.com/67390
TryBot-Result: Gobot Gobot <gobot@golang.org>
Reviewed-by: Dmitry Vyukov <dvyukov@google.com>
This commit is contained in:
Elias Naur 2017-10-01 12:51:54 +02:00
parent f2af0c1780
commit 9735fcfce7
1 changed files with 10 additions and 0 deletions
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10
src/sync/atomic/asm_darwin_arm.s
View File

@ -6,6 +6,12 @@
// Darwin/ARM atomic operations.
#define DMB_ISHST_7 \
WORD $0xf57ff05a // dmb ishst
#define DMB_ISH_7 \
WORD $0xf57ff05b // dmb ish
TEXT ·CompareAndSwapInt32(SB),NOSPLIT,$0
B ·CompareAndSwapUint32(SB)
@ -58,9 +64,11 @@ TEXT ·LoadUint32(SB),NOSPLIT,$0-8
MOVW addr+0(FP), R1
load32loop:
LDREX (R1), R2 // loads R2
DMB_ISHST_7
STREX R2, (R1), R0 // stores R2
CMP $0, R0
BNE load32loop
DMB_ISH_7
MOVW R2, val+4(FP)
RET
@ -84,9 +92,11 @@ TEXT ·StoreUint32(SB),NOSPLIT,$0-8
MOVW val+4(FP), R2
storeloop:
LDREX (R1), R4 // loads R4
DMB_ISHST_7
STREX R2, (R1), R0 // stores R2
CMP $0, R0
BNE storeloop
DMB_ISH_7
RET
TEXT ·StoreInt64(SB),NOSPLIT,$0