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cmd/asm: add check for register and shift/extension combination on arm64
The current code lacks a check on whether the register and shift/extension combination is valid, for example the follow instructions also compiles. ADD F1<<1, R1, R3 ADD V1<<1, R1, R3 MOVW (R9)(F8.SXTW<<2), R19 VST1 R4.D[1], (R0) Actually only general registers can perform shift operations, and element and arrangement extensions are only applicable to vector registers. This CL adds a check for the register and shift/extension combination on arm64. Change-Id: I93dd9343e92a66899cba8eaf4e0ac5430e94692b Reviewed-on: https://go-review.googlesource.com/c/go/+/312571 Trust: eric fang <eric.fang@arm.com> Reviewed-by: eric fang <eric.fang@arm.com> Reviewed-by: Keith Randall <khr@golang.org> Run-TryBot: eric fang <eric.fang@arm.com> TryBot-Result: Go Bot <gobot@golang.org>
This commit is contained in:
eric fang
parent
f439a76253
commit
9726c78539
@ -147,7 +147,16 @@ func arm64RegisterNumber(name string, n int16) (int16, bool) {
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return 0, false
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}
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// ARM64RegisterExtension parses an ARM64 register with extension or arrangement.
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// ARM64RegisterShift constructs an ARM64 register with shift operation.
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func ARM64RegisterShift(reg, op, count int16) (int64, error) {
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// the base register of shift operations must be general register.
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if reg > arm64.REG_R31 || reg < arm64.REG_R0 {
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return 0, errors.New("invalid register for shift operation")
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}
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return int64(reg&31)<<16 | int64(op)<<22 | int64(uint16(count)), nil
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}
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// ARM64RegisterExtension constructs an ARM64 register with extension or arrangement.
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func ARM64RegisterExtension(a *obj.Addr, ext string, reg, num int16, isAmount, isIndex bool) error {
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Rnum := (reg & 31) + int16(num<<5)
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if isAmount {
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@ -155,154 +164,163 @@ func ARM64RegisterExtension(a *obj.Addr, ext string, reg, num int16, isAmount, i
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return errors.New("index shift amount is out of range")
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}
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}
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switch ext {
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case "UXTB":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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if a.Type == obj.TYPE_MEM {
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return errors.New("invalid shift for the register offset addressing mode")
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}
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a.Reg = arm64.REG_UXTB + Rnum
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case "UXTH":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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if a.Type == obj.TYPE_MEM {
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return errors.New("invalid shift for the register offset addressing mode")
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}
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a.Reg = arm64.REG_UXTH + Rnum
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case "UXTW":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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// effective address of memory is a base register value and an offset register value.
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if a.Type == obj.TYPE_MEM {
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a.Index = arm64.REG_UXTW + Rnum
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} else {
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a.Reg = arm64.REG_UXTW + Rnum
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}
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case "UXTX":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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if a.Type == obj.TYPE_MEM {
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return errors.New("invalid shift for the register offset addressing mode")
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}
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a.Reg = arm64.REG_UXTX + Rnum
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case "SXTB":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_SXTB + Rnum
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case "SXTH":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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if a.Type == obj.TYPE_MEM {
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return errors.New("invalid shift for the register offset addressing mode")
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}
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a.Reg = arm64.REG_SXTH + Rnum
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case "SXTW":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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if a.Type == obj.TYPE_MEM {
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a.Index = arm64.REG_SXTW + Rnum
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} else {
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a.Reg = arm64.REG_SXTW + Rnum
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}
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case "SXTX":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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if a.Type == obj.TYPE_MEM {
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a.Index = arm64.REG_SXTX + Rnum
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} else {
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a.Reg = arm64.REG_SXTX + Rnum
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}
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case "LSL":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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a.Index = arm64.REG_LSL + Rnum
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case "B8":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_8B & 15) << 5)
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case "B16":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_16B & 15) << 5)
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case "H4":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_4H & 15) << 5)
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case "H8":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_8H & 15) << 5)
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case "S2":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_2S & 15) << 5)
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case "S4":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_4S & 15) << 5)
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case "D1":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_1D & 15) << 5)
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case "D2":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_2D & 15) << 5)
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case "Q1":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_1Q & 15) << 5)
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case "B":
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if !isIndex {
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return nil
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}
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a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_B & 15) << 5)
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a.Index = num
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case "H":
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if !isIndex {
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return nil
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}
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a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_H & 15) << 5)
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a.Index = num
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case "S":
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if !isIndex {
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return nil
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}
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a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_S & 15) << 5)
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a.Index = num
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case "D":
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if !isIndex {
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return nil
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}
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a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_D & 15) << 5)
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a.Index = num
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default:
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return errors.New("unsupported register extension type: " + ext)
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}
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if reg <= arm64.REG_R31 && reg >= arm64.REG_R0 {
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switch ext {
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case "UXTB":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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if a.Type == obj.TYPE_MEM {
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return errors.New("invalid shift for the register offset addressing mode")
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}
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a.Reg = arm64.REG_UXTB + Rnum
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case "UXTH":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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if a.Type == obj.TYPE_MEM {
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return errors.New("invalid shift for the register offset addressing mode")
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}
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a.Reg = arm64.REG_UXTH + Rnum
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case "UXTW":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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// effective address of memory is a base register value and an offset register value.
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if a.Type == obj.TYPE_MEM {
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a.Index = arm64.REG_UXTW + Rnum
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} else {
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a.Reg = arm64.REG_UXTW + Rnum
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}
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case "UXTX":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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if a.Type == obj.TYPE_MEM {
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return errors.New("invalid shift for the register offset addressing mode")
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}
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a.Reg = arm64.REG_UXTX + Rnum
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case "SXTB":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_SXTB + Rnum
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case "SXTH":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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if a.Type == obj.TYPE_MEM {
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return errors.New("invalid shift for the register offset addressing mode")
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}
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a.Reg = arm64.REG_SXTH + Rnum
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case "SXTW":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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if a.Type == obj.TYPE_MEM {
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a.Index = arm64.REG_SXTW + Rnum
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} else {
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a.Reg = arm64.REG_SXTW + Rnum
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}
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case "SXTX":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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if a.Type == obj.TYPE_MEM {
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a.Index = arm64.REG_SXTX + Rnum
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} else {
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a.Reg = arm64.REG_SXTX + Rnum
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}
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case "LSL":
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if !isAmount {
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return errors.New("invalid register extension")
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}
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a.Index = arm64.REG_LSL + Rnum
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default:
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return errors.New("unsupported general register extension type: " + ext)
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}
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} else if reg <= arm64.REG_V31 && reg >= arm64.REG_V0 {
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switch ext {
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case "B8":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_8B & 15) << 5)
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case "B16":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_16B & 15) << 5)
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case "H4":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_4H & 15) << 5)
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case "H8":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_8H & 15) << 5)
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case "S2":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_2S & 15) << 5)
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case "S4":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_4S & 15) << 5)
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case "D1":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_1D & 15) << 5)
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case "D2":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_2D & 15) << 5)
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case "Q1":
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if isIndex {
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return errors.New("invalid register extension")
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}
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a.Reg = arm64.REG_ARNG + (reg & 31) + ((arm64.ARNG_1Q & 15) << 5)
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case "B":
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if !isIndex {
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return nil
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}
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a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_B & 15) << 5)
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a.Index = num
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case "H":
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if !isIndex {
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return nil
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}
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a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_H & 15) << 5)
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a.Index = num
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case "S":
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if !isIndex {
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return nil
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}
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a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_S & 15) << 5)
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a.Index = num
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case "D":
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if !isIndex {
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return nil
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}
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a.Reg = arm64.REG_ELEM + (reg & 31) + ((arm64.ARNG_D & 15) << 5)
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a.Index = num
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default:
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return errors.New("unsupported simd register extension type: " + ext)
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}
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} else {
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return errors.New("invalid register and extension combination")
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}
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return nil
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}
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// ARM64RegisterArrangement parses an ARM64 vector register arrangement.
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// ARM64RegisterArrangement constructs an ARM64 vector register arrangement.
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func ARM64RegisterArrangement(reg int16, name, arng string) (int64, error) {
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var curQ, curSize uint16
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if name[0] != 'V' {
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@ -689,7 +689,11 @@ func (p *Parser) registerShift(name string, prefix rune) int64 {
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p.errorf("unexpected %s in register shift", tok.String())
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}
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if p.arch.Family == sys.ARM64 {
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return int64(r1&31)<<16 | int64(op)<<22 | int64(uint16(count))
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off, err := arch.ARM64RegisterShift(r1, op, count)
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if err != nil {
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p.errorf(err.Error())
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}
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return off
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} else {
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return int64((r1 & 15) | op<<5 | count)
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}
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14
src/cmd/asm/internal/asm/testdata/arm64error.s
vendored
14
src/cmd/asm/internal/asm/testdata/arm64error.s
vendored
@ -96,13 +96,13 @@ TEXT errors(SB),$0
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VMOV V8.H[9], R3 // ERROR "register element index out of range 0 to 7"
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VMOV V8.S[4], R3 // ERROR "register element index out of range 0 to 3"
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VMOV V8.D[2], R3 // ERROR "register element index out of range 0 to 1"
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VDUP V8.B[16], R3.B16 // ERROR "register element index out of range 0 to 15"
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VDUP V8.B[17], R3.B8 // ERROR "register element index out of range 0 to 15"
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VDUP V8.H[9], R3.H4 // ERROR "register element index out of range 0 to 7"
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VDUP V8.H[9], R3.H8 // ERROR "register element index out of range 0 to 7"
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VDUP V8.S[4], R3.S2 // ERROR "register element index out of range 0 to 3"
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VDUP V8.S[4], R3.S4 // ERROR "register element index out of range 0 to 3"
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VDUP V8.D[2], R3.D2 // ERROR "register element index out of range 0 to 1"
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VDUP V8.B[16], V3.B16 // ERROR "register element index out of range 0 to 15"
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VDUP V8.B[17], V3.B8 // ERROR "register element index out of range 0 to 15"
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VDUP V8.H[9], V3.H4 // ERROR "register element index out of range 0 to 7"
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VDUP V8.H[9], V3.H8 // ERROR "register element index out of range 0 to 7"
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VDUP V8.S[4], V3.S2 // ERROR "register element index out of range 0 to 3"
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VDUP V8.S[4], V3.S4 // ERROR "register element index out of range 0 to 3"
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VDUP V8.D[2], V3.D2 // ERROR "register element index out of range 0 to 1"
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VFMLA V1.D2, V12.D2, V3.S2 // ERROR "operand mismatch"
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VFMLA V1.S2, V12.S2, V3.D2 // ERROR "operand mismatch"
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VFMLA V1.S4, V12.S2, V3.D2 // ERROR "operand mismatch"
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