mirror of
https://github.com/golang/go
synced 2024-11-17 01:04:50 -07:00
cmd/internal/obj/riscv: regenerate instruction encoding table
This CL updates riscv instructions by https://github.com/riscv/riscv-opcodes which adds instruction: APAUSE And removes the following unused instructions: AFENCEI AFMVQX AFMVXQ AHFENCEGVMA AHFENCEVVMA ASLLIRV32 ASRAIRV32 ASRLIRV32 AURET Change-Id: I314570c643af3e6bbc9d2cd471b6b39985bcbdff Reviewed-on: https://go-review.googlesource.com/c/go/+/409415 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Benny Siegert <bsiegert@gmail.com> Reviewed-by: Joel Sing <joel@sing.id.au> TryBot-Result: Gopher Robot <gobot@golang.org> Run-TryBot: M Zhuo <mzh@golangcn.org>
This commit is contained in:
Meng Zhuo
M Zhuo
parent
d9dce0cd26
commit
8e8303e1d0
@ -26,9 +26,6 @@ var Anames = []string{
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"SRL",
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"SUB",
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"SRA",
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"SLLIRV32",
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"SRLIRV32",
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"SRAIRV32",
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"JAL",
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"JALR",
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"BEQ",
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@ -47,8 +44,8 @@ var Anames = []string{
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"SH",
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"SB",
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"FENCE",
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"FENCEI",
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"FENCETSO",
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"PAUSE",
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"ADDIW",
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"SLLIW",
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"SRLIW",
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@ -201,8 +198,6 @@ var Anames = []string{
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"FSGNJQ",
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"FSGNJNQ",
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"FSGNJXQ",
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"FMVXQ",
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"FMVQX",
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"FEQQ",
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"FLEQ",
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"FLTQ",
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@ -219,12 +214,9 @@ var Anames = []string{
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"SBREAK",
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"MRET",
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"SRET",
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"URET",
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"DRET",
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"WFI",
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"SFENCEVMA",
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"HFENCEGVMA",
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"HFENCEVVMA",
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"WORD",
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"BEQZ",
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"BGEZ",
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@ -309,12 +309,6 @@ const (
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ASUB
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ASRA
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// The SLL/SRL/SRA instructions differ slightly between RV32 and RV64,
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// hence there are pseudo-opcodes for the RV32 specific versions.
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ASLLIRV32
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ASRLIRV32
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ASRAIRV32
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// 2.5: Control Transfer Instructions
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AJAL
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AJALR
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@ -338,8 +332,8 @@ const (
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// 2.7: Memory Ordering Instructions
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AFENCE
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AFENCEI
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AFENCETSO
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APAUSE
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// 5.2: Integer Computational Instructions (RV64I)
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AADDIW
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@ -532,8 +526,6 @@ const (
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AFSGNJQ
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AFSGNJNQ
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AFSGNJXQ
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AFMVXQ
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AFMVQX
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// 13.4 Quad-Precision Floating-Point Compare Instructions
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AFEQQ
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@ -562,7 +554,6 @@ const (
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// 3.2.2: Trap-Return Instructions
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AMRET
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ASRET
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AURET
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ADRET
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// 3.2.3: Wait for Interrupt
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@ -571,10 +562,6 @@ const (
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// 4.2.1: Supervisor Memory-Management Fence Instruction
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ASFENCEVMA
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// Hypervisor Memory-Management Instructions
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AHFENCEGVMA
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AHFENCEVVMA
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// The escape hatch. Inserts a single 32-bit word.
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AWORD
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@ -1,5 +1,4 @@
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// Code generated by parse_opcodes -go; DO NOT EDIT.
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// Code generated by parse.py -go rv64_a rv64_d rv64_f rv64_i rv64_m rv64_q rv_a rv_d rv_f rv_i rv_m rv_q rv_s rv_system rv_zicsr; DO NOT EDIT.
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package riscv
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import "cmd/internal/obj"
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@ -14,108 +13,332 @@ type inst struct {
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func encode(a obj.As) *inst {
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switch a {
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case ABEQ:
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return &inst{0x63, 0x0, 0x0, 0, 0x0}
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case ABNE:
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return &inst{0x63, 0x1, 0x0, 0, 0x0}
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case ABLT:
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return &inst{0x63, 0x4, 0x0, 0, 0x0}
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case ABGE:
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return &inst{0x63, 0x5, 0x0, 0, 0x0}
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case ABLTU:
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return &inst{0x63, 0x6, 0x0, 0, 0x0}
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case ABGEU:
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return &inst{0x63, 0x7, 0x0, 0, 0x0}
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case AJALR:
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return &inst{0x67, 0x0, 0x0, 0, 0x0}
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case AJAL:
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return &inst{0x6f, 0x0, 0x0, 0, 0x0}
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case ALUI:
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return &inst{0x37, 0x0, 0x0, 0, 0x0}
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case AAUIPC:
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return &inst{0x17, 0x0, 0x0, 0, 0x0}
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case AADDI:
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return &inst{0x13, 0x0, 0x0, 0, 0x0}
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case ASLLI:
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return &inst{0x13, 0x1, 0x0, 0, 0x0}
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case ASLTI:
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return &inst{0x13, 0x2, 0x0, 0, 0x0}
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case ASLTIU:
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return &inst{0x13, 0x3, 0x0, 0, 0x0}
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case AXORI:
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return &inst{0x13, 0x4, 0x0, 0, 0x0}
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case ASRLI:
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return &inst{0x13, 0x5, 0x0, 0, 0x0}
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case ASRAI:
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return &inst{0x13, 0x5, 0x0, 1024, 0x20}
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case AORI:
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return &inst{0x13, 0x6, 0x0, 0, 0x0}
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case AANDI:
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return &inst{0x13, 0x7, 0x0, 0, 0x0}
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case AADD:
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return &inst{0x33, 0x0, 0x0, 0, 0x0}
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case ASUB:
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return &inst{0x33, 0x0, 0x0, 1024, 0x20}
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case ASLL:
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return &inst{0x33, 0x1, 0x0, 0, 0x0}
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case ASLT:
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return &inst{0x33, 0x2, 0x0, 0, 0x0}
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case ASLTU:
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return &inst{0x33, 0x3, 0x0, 0, 0x0}
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case AXOR:
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return &inst{0x33, 0x4, 0x0, 0, 0x0}
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case ASRL:
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return &inst{0x33, 0x5, 0x0, 0, 0x0}
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case ASRA:
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return &inst{0x33, 0x5, 0x0, 1024, 0x20}
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case AOR:
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return &inst{0x33, 0x6, 0x0, 0, 0x0}
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case AAND:
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return &inst{0x33, 0x7, 0x0, 0, 0x0}
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case AADDI:
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return &inst{0x13, 0x0, 0x0, 0, 0x0}
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case AADDIW:
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return &inst{0x1b, 0x0, 0x0, 0, 0x0}
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case ASLLIW:
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return &inst{0x1b, 0x1, 0x0, 0, 0x0}
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case ASRLIW:
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return &inst{0x1b, 0x5, 0x0, 0, 0x0}
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case ASRAIW:
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return &inst{0x1b, 0x5, 0x0, 1024, 0x20}
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case AADDW:
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return &inst{0x3b, 0x0, 0x0, 0, 0x0}
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case ASUBW:
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return &inst{0x3b, 0x0, 0x0, 1024, 0x20}
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case ASLLW:
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return &inst{0x3b, 0x1, 0x0, 0, 0x0}
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case ASRLW:
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return &inst{0x3b, 0x5, 0x0, 0, 0x0}
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case ASRAW:
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return &inst{0x3b, 0x5, 0x0, 1024, 0x20}
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case ALB:
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return &inst{0x3, 0x0, 0x0, 0, 0x0}
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case ALH:
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return &inst{0x3, 0x1, 0x0, 0, 0x0}
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case ALW:
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return &inst{0x3, 0x2, 0x0, 0, 0x0}
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case ALD:
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return &inst{0x3, 0x3, 0x0, 0, 0x0}
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case ALBU:
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return &inst{0x3, 0x4, 0x0, 0, 0x0}
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case ALHU:
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return &inst{0x3, 0x5, 0x0, 0, 0x0}
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case ALWU:
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return &inst{0x3, 0x6, 0x0, 0, 0x0}
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case ASB:
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return &inst{0x23, 0x0, 0x0, 0, 0x0}
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case ASH:
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return &inst{0x23, 0x1, 0x0, 0, 0x0}
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case ASW:
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return &inst{0x23, 0x2, 0x0, 0, 0x0}
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case ASD:
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return &inst{0x23, 0x3, 0x0, 0, 0x0}
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case AAMOADDD:
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return &inst{0x2f, 0x3, 0x0, 0, 0x0}
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case AAMOADDW:
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return &inst{0x2f, 0x2, 0x0, 0, 0x0}
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case AAMOANDD:
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return &inst{0x2f, 0x3, 0x0, 1536, 0x30}
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case AAMOANDW:
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return &inst{0x2f, 0x2, 0x0, 1536, 0x30}
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case AAMOMAXD:
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return &inst{0x2f, 0x3, 0x0, -1536, 0x50}
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case AAMOMAXW:
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return &inst{0x2f, 0x2, 0x0, -1536, 0x50}
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case AAMOMAXUD:
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return &inst{0x2f, 0x3, 0x0, -512, 0x70}
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case AAMOMAXUW:
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return &inst{0x2f, 0x2, 0x0, -512, 0x70}
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case AAMOMIND:
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return &inst{0x2f, 0x3, 0x0, -2048, 0x40}
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case AAMOMINW:
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return &inst{0x2f, 0x2, 0x0, -2048, 0x40}
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case AAMOMINUD:
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return &inst{0x2f, 0x3, 0x0, -1024, 0x60}
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case AAMOMINUW:
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return &inst{0x2f, 0x2, 0x0, -1024, 0x60}
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case AAMOORD:
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return &inst{0x2f, 0x3, 0x0, 1024, 0x20}
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case AAMOORW:
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return &inst{0x2f, 0x2, 0x0, 1024, 0x20}
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case AAMOSWAPD:
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return &inst{0x2f, 0x3, 0x0, 128, 0x4}
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case AAMOSWAPW:
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return &inst{0x2f, 0x2, 0x0, 128, 0x4}
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case AAMOXORD:
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return &inst{0x2f, 0x3, 0x0, 512, 0x10}
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case AAMOXORW:
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return &inst{0x2f, 0x2, 0x0, 512, 0x10}
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case AAND:
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return &inst{0x33, 0x7, 0x0, 0, 0x0}
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case AANDI:
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return &inst{0x13, 0x7, 0x0, 0, 0x0}
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case AAUIPC:
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return &inst{0x17, 0x0, 0x0, 0, 0x0}
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case ABEQ:
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return &inst{0x63, 0x0, 0x0, 0, 0x0}
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case ABGE:
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return &inst{0x63, 0x5, 0x0, 0, 0x0}
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case ABGEU:
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return &inst{0x63, 0x7, 0x0, 0, 0x0}
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case ABLT:
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return &inst{0x63, 0x4, 0x0, 0, 0x0}
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case ABLTU:
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return &inst{0x63, 0x6, 0x0, 0, 0x0}
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case ABNE:
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return &inst{0x63, 0x1, 0x0, 0, 0x0}
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case ACSRRC:
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return &inst{0x73, 0x3, 0x0, 0, 0x0}
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case ACSRRCI:
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return &inst{0x73, 0x7, 0x0, 0, 0x0}
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case ACSRRS:
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return &inst{0x73, 0x2, 0x0, 0, 0x0}
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case ACSRRSI:
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return &inst{0x73, 0x6, 0x0, 0, 0x0}
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case ACSRRW:
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return &inst{0x73, 0x1, 0x0, 0, 0x0}
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case ACSRRWI:
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return &inst{0x73, 0x5, 0x0, 0, 0x0}
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case ADIV:
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return &inst{0x33, 0x4, 0x0, 32, 0x1}
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case ADIVU:
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return &inst{0x33, 0x5, 0x0, 32, 0x1}
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case ADIVUW:
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return &inst{0x3b, 0x5, 0x0, 32, 0x1}
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case ADIVW:
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return &inst{0x3b, 0x4, 0x0, 32, 0x1}
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case ADRET:
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return &inst{0x73, 0x0, 0x12, 1970, 0x3d}
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case AEBREAK:
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return &inst{0x73, 0x0, 0x1, 1, 0x0}
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case AECALL:
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return &inst{0x73, 0x0, 0x0, 0, 0x0}
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case AFADDD:
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return &inst{0x53, 0x0, 0x0, 32, 0x1}
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case AFADDQ:
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return &inst{0x53, 0x0, 0x0, 96, 0x3}
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case AFADDS:
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return &inst{0x53, 0x0, 0x0, 0, 0x0}
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case AFCLASSD:
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return &inst{0x53, 0x1, 0x0, -480, 0x71}
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case AFCLASSQ:
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return &inst{0x53, 0x1, 0x0, -416, 0x73}
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case AFCLASSS:
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return &inst{0x53, 0x1, 0x0, -512, 0x70}
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case AFCVTDL:
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return &inst{0x53, 0x0, 0x2, -734, 0x69}
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case AFCVTDLU:
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return &inst{0x53, 0x0, 0x3, -733, 0x69}
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case AFCVTDQ:
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return &inst{0x53, 0x0, 0x3, 1059, 0x21}
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case AFCVTDS:
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return &inst{0x53, 0x0, 0x0, 1056, 0x21}
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case AFCVTDW:
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return &inst{0x53, 0x0, 0x0, -736, 0x69}
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case AFCVTDWU:
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return &inst{0x53, 0x0, 0x1, -735, 0x69}
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case AFCVTLD:
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return &inst{0x53, 0x0, 0x2, -990, 0x61}
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case AFCVTLQ:
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return &inst{0x53, 0x0, 0x2, -926, 0x63}
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case AFCVTLS:
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return &inst{0x53, 0x0, 0x2, -1022, 0x60}
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case AFCVTLUD:
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return &inst{0x53, 0x0, 0x3, -989, 0x61}
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case AFCVTLUQ:
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return &inst{0x53, 0x0, 0x3, -925, 0x63}
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case AFCVTLUS:
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return &inst{0x53, 0x0, 0x3, -1021, 0x60}
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case AFCVTQD:
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return &inst{0x53, 0x0, 0x1, 1121, 0x23}
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case AFCVTQL:
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return &inst{0x53, 0x0, 0x2, -670, 0x6b}
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case AFCVTQLU:
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return &inst{0x53, 0x0, 0x3, -669, 0x6b}
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case AFCVTQS:
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return &inst{0x53, 0x0, 0x0, 1120, 0x23}
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case AFCVTQW:
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return &inst{0x53, 0x0, 0x0, -672, 0x6b}
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case AFCVTQWU:
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return &inst{0x53, 0x0, 0x1, -671, 0x6b}
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case AFCVTSD:
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return &inst{0x53, 0x0, 0x1, 1025, 0x20}
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case AFCVTSL:
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return &inst{0x53, 0x0, 0x2, -766, 0x68}
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case AFCVTSLU:
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return &inst{0x53, 0x0, 0x3, -765, 0x68}
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case AFCVTSQ:
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return &inst{0x53, 0x0, 0x3, 1027, 0x20}
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case AFCVTSW:
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return &inst{0x53, 0x0, 0x0, -768, 0x68}
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case AFCVTSWU:
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return &inst{0x53, 0x0, 0x1, -767, 0x68}
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case AFCVTWD:
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return &inst{0x53, 0x0, 0x0, -992, 0x61}
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case AFCVTWQ:
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return &inst{0x53, 0x0, 0x0, -928, 0x63}
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case AFCVTWS:
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return &inst{0x53, 0x0, 0x0, -1024, 0x60}
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case AFCVTWUD:
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return &inst{0x53, 0x0, 0x1, -991, 0x61}
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case AFCVTWUQ:
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return &inst{0x53, 0x0, 0x1, -927, 0x63}
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case AFCVTWUS:
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return &inst{0x53, 0x0, 0x1, -1023, 0x60}
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case AFDIVD:
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return &inst{0x53, 0x0, 0x0, 416, 0xd}
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case AFDIVQ:
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return &inst{0x53, 0x0, 0x0, 480, 0xf}
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case AFDIVS:
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return &inst{0x53, 0x0, 0x0, 384, 0xc}
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case AFENCE:
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return &inst{0xf, 0x0, 0x0, 0, 0x0}
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case AFENCEI:
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return &inst{0xf, 0x1, 0x0, 0, 0x0}
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case AFENCETSO:
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return &inst{0xf, 0x0, 0x13, -1997, 0x41}
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case AFEQD:
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return &inst{0x53, 0x2, 0x0, -1504, 0x51}
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case AFEQQ:
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return &inst{0x53, 0x2, 0x0, -1440, 0x53}
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case AFEQS:
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return &inst{0x53, 0x2, 0x0, -1536, 0x50}
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case AFLD:
|
||||
return &inst{0x7, 0x3, 0x0, 0, 0x0}
|
||||
case AFLED:
|
||||
return &inst{0x53, 0x0, 0x0, -1504, 0x51}
|
||||
case AFLEQ:
|
||||
return &inst{0x53, 0x0, 0x0, -1440, 0x53}
|
||||
case AFLES:
|
||||
return &inst{0x53, 0x0, 0x0, -1536, 0x50}
|
||||
case AFLQ:
|
||||
return &inst{0x7, 0x4, 0x0, 0, 0x0}
|
||||
case AFLTD:
|
||||
return &inst{0x53, 0x1, 0x0, -1504, 0x51}
|
||||
case AFLTQ:
|
||||
return &inst{0x53, 0x1, 0x0, -1440, 0x53}
|
||||
case AFLTS:
|
||||
return &inst{0x53, 0x1, 0x0, -1536, 0x50}
|
||||
case AFLW:
|
||||
return &inst{0x7, 0x2, 0x0, 0, 0x0}
|
||||
case AFMADDD:
|
||||
return &inst{0x43, 0x0, 0x0, 32, 0x1}
|
||||
case AFMADDQ:
|
||||
return &inst{0x43, 0x0, 0x0, 96, 0x3}
|
||||
case AFMADDS:
|
||||
return &inst{0x43, 0x0, 0x0, 0, 0x0}
|
||||
case AFMAXD:
|
||||
return &inst{0x53, 0x1, 0x0, 672, 0x15}
|
||||
case AFMAXQ:
|
||||
return &inst{0x53, 0x1, 0x0, 736, 0x17}
|
||||
case AFMAXS:
|
||||
return &inst{0x53, 0x1, 0x0, 640, 0x14}
|
||||
case AFMIND:
|
||||
return &inst{0x53, 0x0, 0x0, 672, 0x15}
|
||||
case AFMINQ:
|
||||
return &inst{0x53, 0x0, 0x0, 736, 0x17}
|
||||
case AFMINS:
|
||||
return &inst{0x53, 0x0, 0x0, 640, 0x14}
|
||||
case AFMSUBD:
|
||||
return &inst{0x47, 0x0, 0x0, 32, 0x1}
|
||||
case AFMSUBQ:
|
||||
return &inst{0x47, 0x0, 0x0, 96, 0x3}
|
||||
case AFMSUBS:
|
||||
return &inst{0x47, 0x0, 0x0, 0, 0x0}
|
||||
case AFMULD:
|
||||
return &inst{0x53, 0x0, 0x0, 288, 0x9}
|
||||
case AFMULQ:
|
||||
return &inst{0x53, 0x0, 0x0, 352, 0xb}
|
||||
case AFMULS:
|
||||
return &inst{0x53, 0x0, 0x0, 256, 0x8}
|
||||
case AFMVDX:
|
||||
return &inst{0x53, 0x0, 0x0, -224, 0x79}
|
||||
case AFMVSX:
|
||||
return &inst{0x53, 0x0, 0x0, -256, 0x78}
|
||||
case AFMVWX:
|
||||
return &inst{0x53, 0x0, 0x0, -256, 0x78}
|
||||
case AFMVXD:
|
||||
return &inst{0x53, 0x0, 0x0, -480, 0x71}
|
||||
case AFMVXS:
|
||||
return &inst{0x53, 0x0, 0x0, -512, 0x70}
|
||||
case AFMVXW:
|
||||
return &inst{0x53, 0x0, 0x0, -512, 0x70}
|
||||
case AFNMADDD:
|
||||
return &inst{0x4f, 0x0, 0x0, 32, 0x1}
|
||||
case AFNMADDQ:
|
||||
return &inst{0x4f, 0x0, 0x0, 96, 0x3}
|
||||
case AFNMADDS:
|
||||
return &inst{0x4f, 0x0, 0x0, 0, 0x0}
|
||||
case AFNMSUBD:
|
||||
return &inst{0x4b, 0x0, 0x0, 32, 0x1}
|
||||
case AFNMSUBQ:
|
||||
return &inst{0x4b, 0x0, 0x0, 96, 0x3}
|
||||
case AFNMSUBS:
|
||||
return &inst{0x4b, 0x0, 0x0, 0, 0x0}
|
||||
case AFRCSR:
|
||||
return &inst{0x73, 0x2, 0x3, 3, 0x0}
|
||||
case AFRFLAGS:
|
||||
return &inst{0x73, 0x2, 0x1, 1, 0x0}
|
||||
case AFRRM:
|
||||
return &inst{0x73, 0x2, 0x2, 2, 0x0}
|
||||
case AFSCSR:
|
||||
return &inst{0x73, 0x1, 0x3, 3, 0x0}
|
||||
case AFSD:
|
||||
return &inst{0x27, 0x3, 0x0, 0, 0x0}
|
||||
case AFSFLAGS:
|
||||
return &inst{0x73, 0x1, 0x1, 1, 0x0}
|
||||
case AFSFLAGSI:
|
||||
return &inst{0x73, 0x5, 0x1, 1, 0x0}
|
||||
case AFSGNJD:
|
||||
return &inst{0x53, 0x0, 0x0, 544, 0x11}
|
||||
case AFSGNJQ:
|
||||
return &inst{0x53, 0x0, 0x0, 608, 0x13}
|
||||
case AFSGNJS:
|
||||
return &inst{0x53, 0x0, 0x0, 512, 0x10}
|
||||
case AFSGNJND:
|
||||
return &inst{0x53, 0x1, 0x0, 544, 0x11}
|
||||
case AFSGNJNQ:
|
||||
return &inst{0x53, 0x1, 0x0, 608, 0x13}
|
||||
case AFSGNJNS:
|
||||
return &inst{0x53, 0x1, 0x0, 512, 0x10}
|
||||
case AFSGNJXD:
|
||||
return &inst{0x53, 0x2, 0x0, 544, 0x11}
|
||||
case AFSGNJXQ:
|
||||
return &inst{0x53, 0x2, 0x0, 608, 0x13}
|
||||
case AFSGNJXS:
|
||||
return &inst{0x53, 0x2, 0x0, 512, 0x10}
|
||||
case AFSQ:
|
||||
return &inst{0x27, 0x4, 0x0, 0, 0x0}
|
||||
case AFSQRTD:
|
||||
return &inst{0x53, 0x0, 0x0, 1440, 0x2d}
|
||||
case AFSQRTQ:
|
||||
return &inst{0x53, 0x0, 0x0, 1504, 0x2f}
|
||||
case AFSQRTS:
|
||||
return &inst{0x53, 0x0, 0x0, 1408, 0x2c}
|
||||
case AFSRM:
|
||||
return &inst{0x73, 0x1, 0x2, 2, 0x0}
|
||||
case AFSRMI:
|
||||
return &inst{0x73, 0x5, 0x2, 2, 0x0}
|
||||
case AFSUBD:
|
||||
return &inst{0x53, 0x0, 0x0, 160, 0x5}
|
||||
case AFSUBQ:
|
||||
return &inst{0x53, 0x0, 0x0, 224, 0x7}
|
||||
case AFSUBS:
|
||||
return &inst{0x53, 0x0, 0x0, 128, 0x4}
|
||||
case AFSW:
|
||||
return &inst{0x27, 0x2, 0x0, 0, 0x0}
|
||||
case AJAL:
|
||||
return &inst{0x6f, 0x0, 0x0, 0, 0x0}
|
||||
case AJALR:
|
||||
return &inst{0x67, 0x0, 0x0, 0, 0x0}
|
||||
case ALB:
|
||||
return &inst{0x3, 0x0, 0x0, 0, 0x0}
|
||||
case ALBU:
|
||||
return &inst{0x3, 0x4, 0x0, 0, 0x0}
|
||||
case ALD:
|
||||
return &inst{0x3, 0x3, 0x0, 0, 0x0}
|
||||
case ALH:
|
||||
return &inst{0x3, 0x1, 0x0, 0, 0x0}
|
||||
case ALHU:
|
||||
return &inst{0x3, 0x5, 0x0, 0, 0x0}
|
||||
case ALRD:
|
||||
return &inst{0x2f, 0x3, 0x0, 256, 0x8}
|
||||
case ALRW:
|
||||
return &inst{0x2f, 0x2, 0x0, 256, 0x8}
|
||||
case ALUI:
|
||||
return &inst{0x37, 0x0, 0x0, 0, 0x0}
|
||||
case ALW:
|
||||
return &inst{0x3, 0x2, 0x0, 0, 0x0}
|
||||
case ALWU:
|
||||
return &inst{0x3, 0x6, 0x0, 0, 0x0}
|
||||
case AMRET:
|
||||
return &inst{0x73, 0x0, 0x2, 770, 0x18}
|
||||
case AMUL:
|
||||
return &inst{0x33, 0x0, 0x0, 32, 0x1}
|
||||
case AMULH:
|
||||
@ -124,336 +347,96 @@ func encode(a obj.As) *inst {
|
||||
return &inst{0x33, 0x2, 0x0, 32, 0x1}
|
||||
case AMULHU:
|
||||
return &inst{0x33, 0x3, 0x0, 32, 0x1}
|
||||
case ADIV:
|
||||
return &inst{0x33, 0x4, 0x0, 32, 0x1}
|
||||
case ADIVU:
|
||||
return &inst{0x33, 0x5, 0x0, 32, 0x1}
|
||||
case AMULW:
|
||||
return &inst{0x3b, 0x0, 0x0, 32, 0x1}
|
||||
case AOR:
|
||||
return &inst{0x33, 0x6, 0x0, 0, 0x0}
|
||||
case AORI:
|
||||
return &inst{0x13, 0x6, 0x0, 0, 0x0}
|
||||
case APAUSE:
|
||||
return &inst{0xf, 0x0, 0x10, 16, 0x0}
|
||||
case ARDCYCLE:
|
||||
return &inst{0x73, 0x2, 0x0, -1024, 0x60}
|
||||
case ARDCYCLEH:
|
||||
return &inst{0x73, 0x2, 0x0, -896, 0x64}
|
||||
case ARDINSTRET:
|
||||
return &inst{0x73, 0x2, 0x2, -1022, 0x60}
|
||||
case ARDINSTRETH:
|
||||
return &inst{0x73, 0x2, 0x2, -894, 0x64}
|
||||
case ARDTIME:
|
||||
return &inst{0x73, 0x2, 0x1, -1023, 0x60}
|
||||
case ARDTIMEH:
|
||||
return &inst{0x73, 0x2, 0x1, -895, 0x64}
|
||||
case AREM:
|
||||
return &inst{0x33, 0x6, 0x0, 32, 0x1}
|
||||
case AREMU:
|
||||
return &inst{0x33, 0x7, 0x0, 32, 0x1}
|
||||
case AMULW:
|
||||
return &inst{0x3b, 0x0, 0x0, 32, 0x1}
|
||||
case ADIVW:
|
||||
return &inst{0x3b, 0x4, 0x0, 32, 0x1}
|
||||
case ADIVUW:
|
||||
return &inst{0x3b, 0x5, 0x0, 32, 0x1}
|
||||
case AREMW:
|
||||
return &inst{0x3b, 0x6, 0x0, 32, 0x1}
|
||||
case AREMUW:
|
||||
return &inst{0x3b, 0x7, 0x0, 32, 0x1}
|
||||
case AAMOADDW:
|
||||
return &inst{0x2f, 0x2, 0x0, 0, 0x0}
|
||||
case AAMOXORW:
|
||||
return &inst{0x2f, 0x2, 0x0, 512, 0x10}
|
||||
case AAMOORW:
|
||||
return &inst{0x2f, 0x2, 0x0, 1024, 0x20}
|
||||
case AAMOANDW:
|
||||
return &inst{0x2f, 0x2, 0x0, 1536, 0x30}
|
||||
case AAMOMINW:
|
||||
return &inst{0x2f, 0x2, 0x0, -2048, 0x40}
|
||||
case AAMOMAXW:
|
||||
return &inst{0x2f, 0x2, 0x0, -1536, 0x50}
|
||||
case AAMOMINUW:
|
||||
return &inst{0x2f, 0x2, 0x0, -1024, 0x60}
|
||||
case AAMOMAXUW:
|
||||
return &inst{0x2f, 0x2, 0x0, -512, 0x70}
|
||||
case AAMOSWAPW:
|
||||
return &inst{0x2f, 0x2, 0x0, 128, 0x4}
|
||||
case ALRW:
|
||||
return &inst{0x2f, 0x2, 0x0, 256, 0x8}
|
||||
case ASCW:
|
||||
return &inst{0x2f, 0x2, 0x0, 384, 0xc}
|
||||
case AAMOADDD:
|
||||
return &inst{0x2f, 0x3, 0x0, 0, 0x0}
|
||||
case AAMOXORD:
|
||||
return &inst{0x2f, 0x3, 0x0, 512, 0x10}
|
||||
case AAMOORD:
|
||||
return &inst{0x2f, 0x3, 0x0, 1024, 0x20}
|
||||
case AAMOANDD:
|
||||
return &inst{0x2f, 0x3, 0x0, 1536, 0x30}
|
||||
case AAMOMIND:
|
||||
return &inst{0x2f, 0x3, 0x0, -2048, 0x40}
|
||||
case AAMOMAXD:
|
||||
return &inst{0x2f, 0x3, 0x0, -1536, 0x50}
|
||||
case AAMOMINUD:
|
||||
return &inst{0x2f, 0x3, 0x0, -1024, 0x60}
|
||||
case AAMOMAXUD:
|
||||
return &inst{0x2f, 0x3, 0x0, -512, 0x70}
|
||||
case AAMOSWAPD:
|
||||
return &inst{0x2f, 0x3, 0x0, 128, 0x4}
|
||||
case ALRD:
|
||||
return &inst{0x2f, 0x3, 0x0, 256, 0x8}
|
||||
case ASCD:
|
||||
return &inst{0x2f, 0x3, 0x0, 384, 0xc}
|
||||
case AECALL:
|
||||
return &inst{0x73, 0x0, 0x0, 0, 0x0}
|
||||
case AEBREAK:
|
||||
return &inst{0x73, 0x0, 0x1, 1, 0x0}
|
||||
case AURET:
|
||||
return &inst{0x73, 0x0, 0x2, 2, 0x0}
|
||||
case ASRET:
|
||||
return &inst{0x73, 0x0, 0x2, 258, 0x8}
|
||||
case AMRET:
|
||||
return &inst{0x73, 0x0, 0x2, 770, 0x18}
|
||||
case ADRET:
|
||||
return &inst{0x73, 0x0, 0x12, 1970, 0x3d}
|
||||
case ASFENCEVMA:
|
||||
return &inst{0x73, 0x0, 0x0, 288, 0x9}
|
||||
case AWFI:
|
||||
return &inst{0x73, 0x0, 0x5, 261, 0x8}
|
||||
case ACSRRW:
|
||||
return &inst{0x73, 0x1, 0x0, 0, 0x0}
|
||||
case ACSRRS:
|
||||
return &inst{0x73, 0x2, 0x0, 0, 0x0}
|
||||
case ACSRRC:
|
||||
return &inst{0x73, 0x3, 0x0, 0, 0x0}
|
||||
case ACSRRWI:
|
||||
return &inst{0x73, 0x5, 0x0, 0, 0x0}
|
||||
case ACSRRSI:
|
||||
return &inst{0x73, 0x6, 0x0, 0, 0x0}
|
||||
case ACSRRCI:
|
||||
return &inst{0x73, 0x7, 0x0, 0, 0x0}
|
||||
case AHFENCEVVMA:
|
||||
return &inst{0x73, 0x0, 0x0, 544, 0x11}
|
||||
case AHFENCEGVMA:
|
||||
return &inst{0x73, 0x0, 0x0, 1568, 0x31}
|
||||
case AFADDS:
|
||||
return &inst{0x53, 0x0, 0x0, 0, 0x0}
|
||||
case AFSUBS:
|
||||
return &inst{0x53, 0x0, 0x0, 128, 0x4}
|
||||
case AFMULS:
|
||||
return &inst{0x53, 0x0, 0x0, 256, 0x8}
|
||||
case AFDIVS:
|
||||
return &inst{0x53, 0x0, 0x0, 384, 0xc}
|
||||
case AFSGNJS:
|
||||
return &inst{0x53, 0x0, 0x0, 512, 0x10}
|
||||
case AFSGNJNS:
|
||||
return &inst{0x53, 0x1, 0x0, 512, 0x10}
|
||||
case AFSGNJXS:
|
||||
return &inst{0x53, 0x2, 0x0, 512, 0x10}
|
||||
case AFMINS:
|
||||
return &inst{0x53, 0x0, 0x0, 640, 0x14}
|
||||
case AFMAXS:
|
||||
return &inst{0x53, 0x1, 0x0, 640, 0x14}
|
||||
case AFSQRTS:
|
||||
return &inst{0x53, 0x0, 0x0, 1408, 0x2c}
|
||||
case AFADDD:
|
||||
return &inst{0x53, 0x0, 0x0, 32, 0x1}
|
||||
case AFSUBD:
|
||||
return &inst{0x53, 0x0, 0x0, 160, 0x5}
|
||||
case AFMULD:
|
||||
return &inst{0x53, 0x0, 0x0, 288, 0x9}
|
||||
case AFDIVD:
|
||||
return &inst{0x53, 0x0, 0x0, 416, 0xd}
|
||||
case AFSGNJD:
|
||||
return &inst{0x53, 0x0, 0x0, 544, 0x11}
|
||||
case AFSGNJND:
|
||||
return &inst{0x53, 0x1, 0x0, 544, 0x11}
|
||||
case AFSGNJXD:
|
||||
return &inst{0x53, 0x2, 0x0, 544, 0x11}
|
||||
case AFMIND:
|
||||
return &inst{0x53, 0x0, 0x0, 672, 0x15}
|
||||
case AFMAXD:
|
||||
return &inst{0x53, 0x1, 0x0, 672, 0x15}
|
||||
case AFCVTSD:
|
||||
return &inst{0x53, 0x0, 0x1, 1025, 0x20}
|
||||
case AFCVTDS:
|
||||
return &inst{0x53, 0x0, 0x0, 1056, 0x21}
|
||||
case AFSQRTD:
|
||||
return &inst{0x53, 0x0, 0x0, 1440, 0x2d}
|
||||
case AFADDQ:
|
||||
return &inst{0x53, 0x0, 0x0, 96, 0x3}
|
||||
case AFSUBQ:
|
||||
return &inst{0x53, 0x0, 0x0, 224, 0x7}
|
||||
case AFMULQ:
|
||||
return &inst{0x53, 0x0, 0x0, 352, 0xb}
|
||||
case AFDIVQ:
|
||||
return &inst{0x53, 0x0, 0x0, 480, 0xf}
|
||||
case AFSGNJQ:
|
||||
return &inst{0x53, 0x0, 0x0, 608, 0x13}
|
||||
case AFSGNJNQ:
|
||||
return &inst{0x53, 0x1, 0x0, 608, 0x13}
|
||||
case AFSGNJXQ:
|
||||
return &inst{0x53, 0x2, 0x0, 608, 0x13}
|
||||
case AFMINQ:
|
||||
return &inst{0x53, 0x0, 0x0, 736, 0x17}
|
||||
case AFMAXQ:
|
||||
return &inst{0x53, 0x1, 0x0, 736, 0x17}
|
||||
case AFCVTSQ:
|
||||
return &inst{0x53, 0x0, 0x3, 1027, 0x20}
|
||||
case AFCVTQS:
|
||||
return &inst{0x53, 0x0, 0x0, 1120, 0x23}
|
||||
case AFCVTDQ:
|
||||
return &inst{0x53, 0x0, 0x3, 1059, 0x21}
|
||||
case AFCVTQD:
|
||||
return &inst{0x53, 0x0, 0x1, 1121, 0x23}
|
||||
case AFSQRTQ:
|
||||
return &inst{0x53, 0x0, 0x0, 1504, 0x2f}
|
||||
case AFLES:
|
||||
return &inst{0x53, 0x0, 0x0, -1536, 0x50}
|
||||
case AFLTS:
|
||||
return &inst{0x53, 0x1, 0x0, -1536, 0x50}
|
||||
case AFEQS:
|
||||
return &inst{0x53, 0x2, 0x0, -1536, 0x50}
|
||||
case AFLED:
|
||||
return &inst{0x53, 0x0, 0x0, -1504, 0x51}
|
||||
case AFLTD:
|
||||
return &inst{0x53, 0x1, 0x0, -1504, 0x51}
|
||||
case AFEQD:
|
||||
return &inst{0x53, 0x2, 0x0, -1504, 0x51}
|
||||
case AFLEQ:
|
||||
return &inst{0x53, 0x0, 0x0, -1440, 0x53}
|
||||
case AFLTQ:
|
||||
return &inst{0x53, 0x1, 0x0, -1440, 0x53}
|
||||
case AFEQQ:
|
||||
return &inst{0x53, 0x2, 0x0, -1440, 0x53}
|
||||
case AFCVTWS:
|
||||
return &inst{0x53, 0x0, 0x0, -1024, 0x60}
|
||||
case AFCVTWUS:
|
||||
return &inst{0x53, 0x0, 0x1, -1023, 0x60}
|
||||
case AFCVTLS:
|
||||
return &inst{0x53, 0x0, 0x2, -1022, 0x60}
|
||||
case AFCVTLUS:
|
||||
return &inst{0x53, 0x0, 0x3, -1021, 0x60}
|
||||
case AFMVXW:
|
||||
return &inst{0x53, 0x0, 0x0, -512, 0x70}
|
||||
case AFCLASSS:
|
||||
return &inst{0x53, 0x1, 0x0, -512, 0x70}
|
||||
case AFCVTWD:
|
||||
return &inst{0x53, 0x0, 0x0, -992, 0x61}
|
||||
case AFCVTWUD:
|
||||
return &inst{0x53, 0x0, 0x1, -991, 0x61}
|
||||
case AFCVTLD:
|
||||
return &inst{0x53, 0x0, 0x2, -990, 0x61}
|
||||
case AFCVTLUD:
|
||||
return &inst{0x53, 0x0, 0x3, -989, 0x61}
|
||||
case AFMVXD:
|
||||
return &inst{0x53, 0x0, 0x0, -480, 0x71}
|
||||
case AFCLASSD:
|
||||
return &inst{0x53, 0x1, 0x0, -480, 0x71}
|
||||
case AFCVTWQ:
|
||||
return &inst{0x53, 0x0, 0x0, -928, 0x63}
|
||||
case AFCVTWUQ:
|
||||
return &inst{0x53, 0x0, 0x1, -927, 0x63}
|
||||
case AFCVTLQ:
|
||||
return &inst{0x53, 0x0, 0x2, -926, 0x63}
|
||||
case AFCVTLUQ:
|
||||
return &inst{0x53, 0x0, 0x3, -925, 0x63}
|
||||
case AFMVXQ:
|
||||
return &inst{0x53, 0x0, 0x0, -416, 0x73}
|
||||
case AFCLASSQ:
|
||||
return &inst{0x53, 0x1, 0x0, -416, 0x73}
|
||||
case AFCVTSW:
|
||||
return &inst{0x53, 0x0, 0x0, -768, 0x68}
|
||||
case AFCVTSWU:
|
||||
return &inst{0x53, 0x0, 0x1, -767, 0x68}
|
||||
case AFCVTSL:
|
||||
return &inst{0x53, 0x0, 0x2, -766, 0x68}
|
||||
case AFCVTSLU:
|
||||
return &inst{0x53, 0x0, 0x3, -765, 0x68}
|
||||
case AFMVWX:
|
||||
return &inst{0x53, 0x0, 0x0, -256, 0x78}
|
||||
case AFCVTDW:
|
||||
return &inst{0x53, 0x0, 0x0, -736, 0x69}
|
||||
case AFCVTDWU:
|
||||
return &inst{0x53, 0x0, 0x1, -735, 0x69}
|
||||
case AFCVTDL:
|
||||
return &inst{0x53, 0x0, 0x2, -734, 0x69}
|
||||
case AFCVTDLU:
|
||||
return &inst{0x53, 0x0, 0x3, -733, 0x69}
|
||||
case AFMVDX:
|
||||
return &inst{0x53, 0x0, 0x0, -224, 0x79}
|
||||
case AFCVTQW:
|
||||
return &inst{0x53, 0x0, 0x0, -672, 0x6b}
|
||||
case AFCVTQWU:
|
||||
return &inst{0x53, 0x0, 0x1, -671, 0x6b}
|
||||
case AFCVTQL:
|
||||
return &inst{0x53, 0x0, 0x2, -670, 0x6b}
|
||||
case AFCVTQLU:
|
||||
return &inst{0x53, 0x0, 0x3, -669, 0x6b}
|
||||
case AFMVQX:
|
||||
return &inst{0x53, 0x0, 0x0, -160, 0x7b}
|
||||
case AFLW:
|
||||
return &inst{0x7, 0x2, 0x0, 0, 0x0}
|
||||
case AFLD:
|
||||
return &inst{0x7, 0x3, 0x0, 0, 0x0}
|
||||
case AFLQ:
|
||||
return &inst{0x7, 0x4, 0x0, 0, 0x0}
|
||||
case AFSW:
|
||||
return &inst{0x27, 0x2, 0x0, 0, 0x0}
|
||||
case AFSD:
|
||||
return &inst{0x27, 0x3, 0x0, 0, 0x0}
|
||||
case AFSQ:
|
||||
return &inst{0x27, 0x4, 0x0, 0, 0x0}
|
||||
case AFMADDS:
|
||||
return &inst{0x43, 0x0, 0x0, 0, 0x0}
|
||||
case AFMSUBS:
|
||||
return &inst{0x47, 0x0, 0x0, 0, 0x0}
|
||||
case AFNMSUBS:
|
||||
return &inst{0x4b, 0x0, 0x0, 0, 0x0}
|
||||
case AFNMADDS:
|
||||
return &inst{0x4f, 0x0, 0x0, 0, 0x0}
|
||||
case AFMADDD:
|
||||
return &inst{0x43, 0x0, 0x0, 32, 0x1}
|
||||
case AFMSUBD:
|
||||
return &inst{0x47, 0x0, 0x0, 32, 0x1}
|
||||
case AFNMSUBD:
|
||||
return &inst{0x4b, 0x0, 0x0, 32, 0x1}
|
||||
case AFNMADDD:
|
||||
return &inst{0x4f, 0x0, 0x0, 32, 0x1}
|
||||
case AFMADDQ:
|
||||
return &inst{0x43, 0x0, 0x0, 96, 0x3}
|
||||
case AFMSUBQ:
|
||||
return &inst{0x47, 0x0, 0x0, 96, 0x3}
|
||||
case AFNMSUBQ:
|
||||
return &inst{0x4b, 0x0, 0x0, 96, 0x3}
|
||||
case AFNMADDQ:
|
||||
return &inst{0x4f, 0x0, 0x0, 96, 0x3}
|
||||
case ASLLIRV32:
|
||||
return &inst{0x13, 0x1, 0x0, 0, 0x0}
|
||||
case ASRLIRV32:
|
||||
return &inst{0x13, 0x5, 0x0, 0, 0x0}
|
||||
case ASRAIRV32:
|
||||
return &inst{0x13, 0x5, 0x0, 1024, 0x20}
|
||||
case AFRFLAGS:
|
||||
return &inst{0x73, 0x2, 0x1, 1, 0x0}
|
||||
case AFSFLAGS:
|
||||
return &inst{0x73, 0x1, 0x1, 1, 0x0}
|
||||
case AFSFLAGSI:
|
||||
return &inst{0x73, 0x5, 0x1, 1, 0x0}
|
||||
case AFRRM:
|
||||
return &inst{0x73, 0x2, 0x2, 2, 0x0}
|
||||
case AFSRM:
|
||||
return &inst{0x73, 0x1, 0x2, 2, 0x0}
|
||||
case AFSRMI:
|
||||
return &inst{0x73, 0x5, 0x2, 2, 0x0}
|
||||
case AFSCSR:
|
||||
return &inst{0x73, 0x1, 0x3, 3, 0x0}
|
||||
case AFRCSR:
|
||||
return &inst{0x73, 0x2, 0x3, 3, 0x0}
|
||||
case ARDCYCLE:
|
||||
return &inst{0x73, 0x2, 0x0, -1024, 0x60}
|
||||
case ARDTIME:
|
||||
return &inst{0x73, 0x2, 0x1, -1023, 0x60}
|
||||
case ARDINSTRET:
|
||||
return &inst{0x73, 0x2, 0x2, -1022, 0x60}
|
||||
case ARDCYCLEH:
|
||||
return &inst{0x73, 0x2, 0x0, -896, 0x64}
|
||||
case ARDTIMEH:
|
||||
return &inst{0x73, 0x2, 0x1, -895, 0x64}
|
||||
case ARDINSTRETH:
|
||||
return &inst{0x73, 0x2, 0x2, -894, 0x64}
|
||||
case ASCALL:
|
||||
return &inst{0x73, 0x0, 0x0, 0, 0x0}
|
||||
case AREMW:
|
||||
return &inst{0x3b, 0x6, 0x0, 32, 0x1}
|
||||
case ASB:
|
||||
return &inst{0x23, 0x0, 0x0, 0, 0x0}
|
||||
case ASBREAK:
|
||||
return &inst{0x73, 0x0, 0x1, 1, 0x0}
|
||||
case AFMVXS:
|
||||
return &inst{0x53, 0x0, 0x0, -512, 0x70}
|
||||
case AFMVSX:
|
||||
return &inst{0x53, 0x0, 0x0, -256, 0x78}
|
||||
case AFENCETSO:
|
||||
return &inst{0xf, 0x0, 0x13, -1997, 0x41}
|
||||
case ASCD:
|
||||
return &inst{0x2f, 0x3, 0x0, 384, 0xc}
|
||||
case ASCW:
|
||||
return &inst{0x2f, 0x2, 0x0, 384, 0xc}
|
||||
case ASCALL:
|
||||
return &inst{0x73, 0x0, 0x0, 0, 0x0}
|
||||
case ASD:
|
||||
return &inst{0x23, 0x3, 0x0, 0, 0x0}
|
||||
case ASFENCEVMA:
|
||||
return &inst{0x73, 0x0, 0x0, 288, 0x9}
|
||||
case ASH:
|
||||
return &inst{0x23, 0x1, 0x0, 0, 0x0}
|
||||
case ASLL:
|
||||
return &inst{0x33, 0x1, 0x0, 0, 0x0}
|
||||
case ASLLI:
|
||||
return &inst{0x13, 0x1, 0x0, 0, 0x0}
|
||||
case ASLLIW:
|
||||
return &inst{0x1b, 0x1, 0x0, 0, 0x0}
|
||||
case ASLLW:
|
||||
return &inst{0x3b, 0x1, 0x0, 0, 0x0}
|
||||
case ASLT:
|
||||
return &inst{0x33, 0x2, 0x0, 0, 0x0}
|
||||
case ASLTI:
|
||||
return &inst{0x13, 0x2, 0x0, 0, 0x0}
|
||||
case ASLTIU:
|
||||
return &inst{0x13, 0x3, 0x0, 0, 0x0}
|
||||
case ASLTU:
|
||||
return &inst{0x33, 0x3, 0x0, 0, 0x0}
|
||||
case ASRA:
|
||||
return &inst{0x33, 0x5, 0x0, 1024, 0x20}
|
||||
case ASRAI:
|
||||
return &inst{0x13, 0x5, 0x0, 1024, 0x20}
|
||||
case ASRAIW:
|
||||
return &inst{0x1b, 0x5, 0x0, 1024, 0x20}
|
||||
case ASRAW:
|
||||
return &inst{0x3b, 0x5, 0x0, 1024, 0x20}
|
||||
case ASRET:
|
||||
return &inst{0x73, 0x0, 0x2, 258, 0x8}
|
||||
case ASRL:
|
||||
return &inst{0x33, 0x5, 0x0, 0, 0x0}
|
||||
case ASRLI:
|
||||
return &inst{0x13, 0x5, 0x0, 0, 0x0}
|
||||
case ASRLIW:
|
||||
return &inst{0x1b, 0x5, 0x0, 0, 0x0}
|
||||
case ASRLW:
|
||||
return &inst{0x3b, 0x5, 0x0, 0, 0x0}
|
||||
case ASUB:
|
||||
return &inst{0x33, 0x0, 0x0, 1024, 0x20}
|
||||
case ASUBW:
|
||||
return &inst{0x3b, 0x0, 0x0, 1024, 0x20}
|
||||
case ASW:
|
||||
return &inst{0x23, 0x2, 0x0, 0, 0x0}
|
||||
case AWFI:
|
||||
return &inst{0x73, 0x0, 0x5, 261, 0x8}
|
||||
case AXOR:
|
||||
return &inst{0x33, 0x4, 0x0, 0, 0x0}
|
||||
case AXORI:
|
||||
return &inst{0x13, 0x4, 0x0, 0, 0x0}
|
||||
}
|
||||
return nil
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user