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cmd/internal/obj/s390x: fix m6 field encoding for VSTRC instruction on s390x

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M6 field for all extended mnemonics of VSTRC set to zero
This fixes VSTRC codegen to emit correctly  and added testcases for all
the extended mnemonics.

Fixes #69216

Change-Id: I2a1b7fb61d6bd6444286eab56a506225c90b75e7
Reviewed-on: https://go-review.googlesource.com/c/go/+/612315
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Reviewed-by: Vishwanatha HD <vishwanatha.hd@ibm.com>
Reviewed-by: Carlos Amedee <carlos@golang.org>
This commit is contained in:
Srinivas Pokala 2024-09-11 06:53:00 +02:00 committed by Cherry Mui
parent 6cce1911b7
commit 889178d5b6
3 changed files with 23 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/cmd/asm/internal/asm/testdata/s390x.s vendored
View File

@ -521,6 +521,19 @@ TEXT main·foo(SB),DUPOK|NOSPLIT,$16-0 // TEXT main.foo(SB), DUPOK|NOSPLIT, $16-
VSUMQG V19, V20, V21 // e75340003e67
VSUMB V7, V8, V9 // e79780000064
VSUMH V22, V23, V24 // e78670001e64
VSTRC V18, V20, V22, V24 // e78240006f8a
VSTRCB V18, V20, V22, V24 // e78240006f8a
VSTRCH V18, V20, V22, V24 // e78241006f8a
VSTRCF V18, V20, V22, V24 // e78242006f8a
VSTRCBS V18, V20, V22, V24 // e78240106f8a
VSTRCHS V18, V20, V22, V24 // e78241106f8a
VSTRCFS V18, V20, V22, V24 // e78242106f8a
VSTRCZB V18, V20, V22, V24 // e78240206f8a
VSTRCZH V18, V20, V22, V24 // e78241206f8a
VSTRCZF V18, V20, V22, V24 // e78242206f8a
VSTRCZBS V18, V20, V22, V24 // e78240306f8a
VSTRCZHS V18, V20, V22, V24 // e78241306f8a
VSTRCZFS V18, V20, V22, V24 // e78242306f8a
RET
RET foo(SB)

4
src/cmd/internal/obj/s390x/asmz.go
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@ -1450,6 +1450,7 @@ func buildop(ctxt *obj.Link) {
opset(AVMALOB, r)
opset(AVMALOH, r)
opset(AVMALOF, r)
opset(AVSTRC, r)
opset(AVSTRCB, r)
opset(AVSTRCH, r)
opset(AVSTRCF, r)
@ -4346,8 +4347,7 @@ func (c *ctxtz) asmout(p *obj.Prog, asm *[]byte) {
zVRRc(op, uint32(p.To.Reg), uint32(v2), uint32(p.From.Reg), m6, m5, m4, asm)
case 120: // VRR-d
op, m6, _ := vop(p.As)
m5 := singleElementMask(p.As)
op, m6, m5 := vop(p.As)
v1 := uint32(p.To.Reg)
v2 := uint32(p.From.Reg)
v3 := uint32(p.Reg)

14
src/cmd/internal/obj/s390x/vector.go
View File

@ -45,8 +45,14 @@ func vop(as obj.As) (opcode, es, cs uint32) {
return op_VAC, 0, 0
case AVACQ:
return op_VAC, 4, 0
case AVMSLG, AVMSLEG, AVMSLOG, AVMSLEOG:
case AVMSLG:
return op_VMSL, 3, 0
case AVMSLEG:
return op_VMSL, 3, 8
case AVMSLOG:
return op_VMSL, 3, 4
case AVMSLEOG:
return op_VMSL, 3, 12
case AVACCC:
return op_VACCC, 0, 0
case AVACCCQ:
@ -1058,12 +1064,6 @@ func singleElementMask(as obj.As) uint32 {
AWFTCIDB,
AWFIDB:
return 8
case AVMSLEG:
return 8
case AVMSLOG:
return 4
case AVMSLEOG:
return 12
}
return 0
}