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cmd/compile: ensure equal functions don't do unaligned loads
On architectures which don't support unaligned loads, make sure we don't generate code that requires them. Generated hash functions also matter in this respect, but they all look ok. Update #37716 Fixes #46283 Change-Id: I6197fdfe04da4428092c99bd871d93738789e16b Reviewed-on: https://go-review.googlesource.com/c/go/+/322151 Trust: Keith Randall <khr@golang.org> Trust: Josh Bleecher Snyder <josharian@gmail.com> Run-TryBot: Keith Randall <khr@golang.org> Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com> Reviewed-by: eric fang <eric.fang@arm.com> TryBot-Result: Go Bot <gobot@golang.org>
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@ -6,6 +6,7 @@ package reflectdata
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import (
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"fmt"
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"math/bits"
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"sort"
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"cmd/compile/internal/base"
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@ -47,6 +48,11 @@ func eqCanPanic(t *types.Type) bool {
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func AlgType(t *types.Type) types.AlgKind {
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a, _ := types.AlgType(t)
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if a == types.AMEM {
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if t.Alignment() < int64(base.Ctxt.Arch.Alignment) && t.Alignment() < t.Width {
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// For example, we can't treat [2]int16 as an int32 if int32s require
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// 4-byte alignment. See issue 46283.
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return a
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}
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switch t.Width {
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case 0:
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return types.AMEM0
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@ -769,6 +775,20 @@ func memrun(t *types.Type, start int) (size int64, next int) {
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if f := t.Field(next); f.Sym.IsBlank() || !isRegularMemory(f.Type) {
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break
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}
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// For issue 46283, don't combine fields if the resulting load would
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// require a larger alignment than the component fields.
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if base.Ctxt.Arch.Alignment > 1 {
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align := t.Alignment()
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if off := t.Field(start).Offset; off&(align-1) != 0 {
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// Offset is less aligned than the containing type.
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// Use offset to determine alignment.
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align = 1 << uint(bits.TrailingZeros64(uint64(off)))
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}
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size := t.Field(next).End() - t.Field(start).Offset
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if size > align {
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break
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}
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}
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}
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return t.Field(next-1).End() - t.Field(start).Offset, next
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}
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96
src/cmd/compile/internal/test/align_test.go
Normal file
96
src/cmd/compile/internal/test/align_test.go
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@ -0,0 +1,96 @@
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// Copyright 2021 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// Test to make sure that equality functions (and hash
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// functions) don't do unaligned reads on architectures
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// that can't do unaligned reads. See issue 46283.
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package test
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import "testing"
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type T1 struct {
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x float32
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a, b, c, d int16 // memequal64
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}
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type T2 struct {
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x float32
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a, b, c, d int32 // memequal128
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}
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type A2 [2]byte // eq uses a 2-byte load
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type A4 [4]byte // eq uses a 4-byte load
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type A8 [8]byte // eq uses an 8-byte load
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//go:noinline
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func cmpT1(p, q *T1) {
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if *p != *q {
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panic("comparison test wrong")
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}
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}
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//go:noinline
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func cmpT2(p, q *T2) {
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if *p != *q {
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panic("comparison test wrong")
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}
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}
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//go:noinline
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func cmpA2(p, q *A2) {
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if *p != *q {
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panic("comparison test wrong")
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}
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}
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//go:noinline
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func cmpA4(p, q *A4) {
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if *p != *q {
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panic("comparison test wrong")
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}
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}
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//go:noinline
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func cmpA8(p, q *A8) {
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if *p != *q {
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panic("comparison test wrong")
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}
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}
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func TestAlignEqual(t *testing.T) {
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cmpT1(&T1{}, &T1{})
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cmpT2(&T2{}, &T2{})
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m1 := map[T1]bool{}
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m1[T1{}] = true
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m1[T1{}] = false
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if len(m1) != 1 {
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t.Fatalf("len(m1)=%d, want 1", len(m1))
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}
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m2 := map[T2]bool{}
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m2[T2{}] = true
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m2[T2{}] = false
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if len(m2) != 1 {
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t.Fatalf("len(m2)=%d, want 1", len(m2))
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}
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type X2 struct {
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y byte
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z A2
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}
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var x2 X2
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cmpA2(&x2.z, &A2{})
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type X4 struct {
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y byte
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z A4
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}
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var x4 X4
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cmpA4(&x4.z, &A4{})
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type X8 struct {
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y byte
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z A8
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}
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var x8 X8
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cmpA8(&x8.z, &A8{})
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}
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@ -40,6 +40,12 @@ type Arch struct {
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// MinLC is the minimum length of an instruction code.
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MinLC int
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// Alignment is maximum alignment required by the architecture
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// for any (compiler-generated) load or store instruction.
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// Loads or stores smaller than Alignment must be naturally aligned.
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// Loads or stores larger than Alignment need only be Alignment-aligned.
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Alignment int8
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}
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// InFamily reports whether a is a member of any of the specified
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@ -60,6 +66,7 @@ var Arch386 = &Arch{
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PtrSize: 4,
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RegSize: 4,
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MinLC: 1,
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Alignment: 1,
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}
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var ArchAMD64 = &Arch{
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@ -69,6 +76,7 @@ var ArchAMD64 = &Arch{
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PtrSize: 8,
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RegSize: 8,
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MinLC: 1,
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Alignment: 1,
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}
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var ArchARM = &Arch{
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@ -78,6 +86,7 @@ var ArchARM = &Arch{
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PtrSize: 4,
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RegSize: 4,
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MinLC: 4,
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Alignment: 4, // TODO: just for arm5?
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}
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var ArchARM64 = &Arch{
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@ -87,6 +96,7 @@ var ArchARM64 = &Arch{
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PtrSize: 8,
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RegSize: 8,
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MinLC: 4,
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Alignment: 1,
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}
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var ArchMIPS = &Arch{
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@ -96,6 +106,7 @@ var ArchMIPS = &Arch{
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PtrSize: 4,
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RegSize: 4,
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MinLC: 4,
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Alignment: 4,
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}
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var ArchMIPSLE = &Arch{
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@ -105,6 +116,7 @@ var ArchMIPSLE = &Arch{
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PtrSize: 4,
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RegSize: 4,
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MinLC: 4,
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Alignment: 4,
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}
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var ArchMIPS64 = &Arch{
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@ -114,6 +126,7 @@ var ArchMIPS64 = &Arch{
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PtrSize: 8,
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RegSize: 8,
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MinLC: 4,
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Alignment: 8,
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}
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var ArchMIPS64LE = &Arch{
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@ -123,6 +136,7 @@ var ArchMIPS64LE = &Arch{
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PtrSize: 8,
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RegSize: 8,
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MinLC: 4,
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Alignment: 8,
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}
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var ArchPPC64 = &Arch{
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@ -132,6 +146,7 @@ var ArchPPC64 = &Arch{
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PtrSize: 8,
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RegSize: 8,
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MinLC: 4,
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Alignment: 1,
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}
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var ArchPPC64LE = &Arch{
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@ -141,6 +156,7 @@ var ArchPPC64LE = &Arch{
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PtrSize: 8,
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RegSize: 8,
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MinLC: 4,
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Alignment: 1,
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}
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var ArchRISCV64 = &Arch{
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@ -150,6 +166,7 @@ var ArchRISCV64 = &Arch{
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PtrSize: 8,
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RegSize: 8,
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MinLC: 4,
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Alignment: 8, // riscv unaligned loads work, but are really slow (trap + simulated by OS)
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}
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var ArchS390X = &Arch{
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@ -159,6 +176,7 @@ var ArchS390X = &Arch{
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PtrSize: 8,
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RegSize: 8,
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MinLC: 2,
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Alignment: 1,
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}
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var ArchWasm = &Arch{
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@ -168,6 +186,7 @@ var ArchWasm = &Arch{
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PtrSize: 8,
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RegSize: 8,
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MinLC: 1,
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Alignment: 1,
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}
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var Archs = [...]*Arch{
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