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cmd/asm, cmd/internal/obj/ppc64: Add ISA 2.05, 2.06 and 2.07 instructions.
This change adds instructions from ISA 2.05, 2.06 and 2.07 that are frequently used in assembly optimizations for ppc64. It also fixes two problems: * the implementation of RLDICR[CC]/RLDICL[CC] did not consider all possible cases for the bit mask. * removed two non-existing instructions that were added by mistake in the VMX implementation (VORL/VANDL). Change-Id: Iaef4e5c6a5240c2156c6c0f28ad3bcd8780e9830 Reviewed-on: https://go-review.googlesource.com/36230 Run-TryBot: Lynn Boger <laboger@linux.vnet.ibm.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com>
This commit is contained in:
Carlos Eduardo Seo
Lynn Boger
parent
06637fb314
commit
85ecc51c48
31
src/cmd/asm/internal/asm/testdata/ppc64.s
vendored
31
src/cmd/asm/internal/asm/testdata/ppc64.s
vendored
@ -540,6 +540,14 @@ label1:
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// }
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// FCMPU F1, F2, CR0
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// FTDIV FRA, FRB, BF produces
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// ftdiv BF, FRA, FRB
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FTDIV F1,F2,$7
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// FTSQRT FRB, BF produces
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// ftsqrt BF, FRB
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FTSQRT F2,$7
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//
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// CMP
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//
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@ -567,6 +575,10 @@ label1:
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// }
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CMP R1, $4, CR0 // CMP R1, CR0, $4
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// CMPB RS,RB,RA produces
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// cmpb RA,RS,RB
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CMPB R2,R2,R1
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//
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// rotate and mask
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//
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@ -673,6 +685,13 @@ label1:
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DCBF (R1)
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DCBF (R1+R2) // DCBF (R1)(R2*1)
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// Population count, X-form
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// <MNEMONIC> RS,RA produces
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// <mnemonic> RA,RS
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POPCNTD R1,R2
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POPCNTW R1,R2
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POPCNTB R1,R2
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// VMX instructions
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// Described as:
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@ -703,14 +722,14 @@ label1:
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// Vector AND, VX-form
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// <MNEMONIC> VRA,VRB,VRT produces
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// <mnemonic> VRT,VRA,VRB
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VANDL V10, V9, V8
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VAND V10, V9, V8
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VANDC V15, V14, V13
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VNAND V19, V18, V17
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// Vector OR, VX-form
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// <MNEMONIC> VRA,VRB,VRT produces
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// <mnemonic> VRT,VRA,VRB
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VORL V26, V25, V24
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VOR V26, V25, V24
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VORC V23, V22, V21
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VNOR V20, V19, V18
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VXOR V17, V16, V15
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@ -739,6 +758,14 @@ label1:
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VADDEUQM V4, V3, V2, V1
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VADDECUQ V4, V3, V2, V1
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// Vector polynomial multiply-sum, VX-form
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// <MNEMONIC> VRA,VRB,VRT produces
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// <mnemonic> VRT,VRA,VRB
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VPMSUMB V2, V3, V1
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VPMSUMH V2, V3, V1
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VPMSUMW V2, V3, V1
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VPMSUMD V2, V3, V1
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// Vector SUB, VX-form
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// <MNEMONIC> VRA,VRB,VRT produces
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// <mnemonic> VRT,VRA,VRB
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@ -626,6 +626,9 @@ const (
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ACNTLZDCC
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ACMPW /* CMP with L=0 */
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ACMPWU
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ACMPB
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AFTDIV
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AFTSQRT
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ADIVD
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ADIVDCC
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ADIVDE
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@ -704,6 +707,9 @@ const (
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/* more 64-bit operations */
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AHRFID
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APOPCNTD
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APOPCNTW
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APOPCNTB
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/* Vector */
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ALV
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@ -721,11 +727,9 @@ const (
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ASTVX
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ASTVXL
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AVAND
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AVANDL
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AVANDC
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AVNAND
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AVOR
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AVORL
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AVORC
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AVNOR
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AVXOR
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@ -770,6 +774,11 @@ const (
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AVSUBE
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AVSUBEUQM
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AVSUBECUQ
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AVPMSUM
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AVPMSUMB
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AVPMSUMH
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AVPMSUMW
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AVPMSUMD
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AVR
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AVRLB
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AVRLH
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@ -871,9 +880,13 @@ const (
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ASTXSIWX
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AMFVSR
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AMFVSRD
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AMFFPRD
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AMFVRD
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AMFVSRWZ
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AMTVSR
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AMTVSRD
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AMTFPRD
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AMTVRD
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AMTVSRWA
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AMTVSRWZ
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AXXLAND
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@ -248,6 +248,9 @@ var Anames = []string{
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"CNTLZDCC",
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"CMPW",
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"CMPWU",
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"CMPB",
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"FTDIV",
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"FTSQRT",
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"DIVD",
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"DIVDCC",
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"DIVDE",
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@ -321,6 +324,9 @@ var Anames = []string{
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"REMDUV",
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"REMDUVCC",
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"HRFID",
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"POPCNTD",
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"POPCNTW",
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"POPCNTB",
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"LV",
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"LVEBX",
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"LVEHX",
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@ -336,11 +342,9 @@ var Anames = []string{
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"STVX",
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"STVXL",
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"VAND",
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"VANDL",
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"VANDC",
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"VNAND",
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"VOR",
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"VORL",
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"VORC",
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"VNOR",
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"VXOR",
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@ -385,6 +389,11 @@ var Anames = []string{
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"VSUBE",
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"VSUBEUQM",
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"VSUBECUQ",
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"VPMSUM",
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"VPMSUMB",
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"VPMSUMH",
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"VPMSUMW",
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"VPMSUMD",
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"VR",
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"VRLB",
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"VRLH",
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@ -484,9 +493,13 @@ var Anames = []string{
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"STXSIWX",
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"MFVSR",
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"MFVSRD",
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"MFFPRD",
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"MFVRD",
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"MFVSRWZ",
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"MTVSR",
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"MTVSRD",
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"MTFPRD",
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"MTVRD",
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"MTVSRWA",
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"MTVSRWZ",
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"XXLAND",
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@ -346,6 +346,12 @@ var optab = []Optab{
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{AMOVD, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsrd */
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{AMOVWZ, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsr */
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/* Other ISA 2.05+ instructions */
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{APOPCNTD, C_REG, C_NONE, C_NONE, C_REG, 93, 4, 0}, /* population count, x-form */
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{ACMPB, C_REG, C_REG, C_NONE, C_REG, 92, 4, 0}, /* compare byte, x-form */
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{AFTDIV, C_FREG, C_FREG, C_NONE, C_SCON, 92, 4, 0}, /* floating test for sw divide, x-form */
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{AFTSQRT, C_FREG, C_NONE, C_NONE, C_SCON, 93, 4, 0}, /* floating test for sw square root, x-form */
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/* Vector instructions */
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/* Vector load */
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@ -372,6 +378,9 @@ var optab = []Optab{
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{AVSUBSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract signed saturate, vx-form */
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{AVSUBE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector subtract extended, va-form */
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/* Vector multiply */
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{AVPMSUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector polynomial multiply & sum, vx-form */
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/* Vector rotate */
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{AVR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector rotate, vx-form */
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@ -428,9 +437,13 @@ var optab = []Optab{
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/* VSX move from VSR */
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{AMFVSR, C_VSREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, /* vsx move from vsr, xx1-form */
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{AMFVSR, C_FREG, C_NONE, C_NONE, C_REG, 88, 4, 0},
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{AMFVSR, C_VREG, C_NONE, C_NONE, C_REG, 88, 4, 0},
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/* VSX move to VSR */
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{AMTVSR, C_REG, C_NONE, C_NONE, C_VSREG, 88, 4, 0}, /* vsx move to vsr, xx1-form */
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{AMTVSR, C_REG, C_NONE, C_NONE, C_FREG, 88, 4, 0},
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{AMTVSR, C_REG, C_NONE, C_NONE, C_VREG, 88, 4, 0},
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/* VSX logical */
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{AXXLAND, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx and, xx3-form */
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@ -1161,6 +1174,10 @@ func buildop(ctxt *obj.Link) {
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opset(ADIVDUVCC, r0)
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opset(ADIVDUCC, r0)
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case APOPCNTD:
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opset(APOPCNTW, r0)
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opset(APOPCNTB, r0)
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case AMOVBZ: /* lbz, stz, rlwm(r/r), lhz, lha, stz, and x variants */
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opset(AMOVH, r0)
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@ -1192,12 +1209,12 @@ func buildop(ctxt *obj.Link) {
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opset(ASTVXL, r0)
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case AVAND: /* vand, vandc, vnand */
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opset(AVANDL, r0)
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opset(AVAND, r0)
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opset(AVANDC, r0)
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opset(AVNAND, r0)
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case AVOR: /* vor, vorc, vxor, vnor, veqv */
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opset(AVORL, r0)
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opset(AVOR, r0)
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opset(AVORC, r0)
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opset(AVXOR, r0)
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opset(AVNOR, r0)
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@ -1253,6 +1270,12 @@ func buildop(ctxt *obj.Link) {
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opset(AVSUBEUQM, r0)
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opset(AVSUBECUQ, r0)
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case AVPMSUM: /* vpmsumb, vpmsumh, vpmsumw, vpmsumd */
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opset(AVPMSUMB, r0)
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opset(AVPMSUMH, r0)
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opset(AVPMSUMW, r0)
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opset(AVPMSUMD, r0)
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case AVR: /* vrlb, vrlh, vrlw, vrld */
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opset(AVRLB, r0)
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opset(AVRLH, r0)
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@ -1375,12 +1398,16 @@ func buildop(ctxt *obj.Link) {
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case ASTXSI: /* stxsiwx */
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opset(ASTXSIWX, r0)
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case AMFVSR: /* mfvsrd, mfvsrwz */
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case AMFVSR: /* mfvsrd, mfvsrwz (and extended mnemonics) */
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opset(AMFVSRD, r0)
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opset(AMFFPRD, r0)
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opset(AMFVRD, r0)
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opset(AMFVSRWZ, r0)
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case AMTVSR: /* mtvsrd, mtvsrwa, mtvsrwz */
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case AMTVSR: /* mtvsrd, mtvsrwa, mtvsrwz (and extended mnemonics) */
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opset(AMTVSRD, r0)
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opset(AMTFPRD, r0)
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opset(AMTVRD, r0)
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opset(AMTVSRWA, r0)
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opset(AMTVSRWZ, r0)
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@ -1710,6 +1737,15 @@ func buildop(ctxt *obj.Link) {
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case ACMPU:
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opset(ACMPWU, r0)
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case ACMPB:
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opset(ACMPB, r0)
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case AFTDIV:
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opset(AFTDIV, r0)
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case AFTSQRT:
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opset(AFTSQRT, r0)
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case AADD,
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AANDCC, /* and. Rb,Rs,Ra; andi. $uimm,Rs,Ra; andis. $uimm,Rs,Ra */
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AFMOVSX,
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@ -1783,7 +1819,7 @@ func AOP_RRR(op uint32, d uint32, a uint32, b uint32) uint32 {
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return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11
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}
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/* VX-form 2-register operands, r/r/none */
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/* VX-form 2-register operands, r/none/r */
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func AOP_RR(op uint32, d uint32, a uint32) uint32 {
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return op | (d&31)<<21 | (a&31)<<11
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}
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@ -1881,6 +1917,10 @@ func OP_RLW(op uint32, a uint32, s uint32, sh uint32, mb uint32, me uint32) uint
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return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | (mb&31)<<6 | (me&31)<<1
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}
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func AOP_RLDIC(op uint32, a uint32, s uint32, sh uint32, m uint32) uint32 {
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return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1 | (m&31)<<6 | ((m&32)>>5)<<5
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}
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func AOP_ISEL(op uint32, t uint32, a uint32, b uint32, bc uint32) uint32 {
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return op | (t&31)<<21 | (a&31)<<16 | (b&31)<<11 | (bc&0x1F)<<6
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}
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@ -2353,6 +2393,11 @@ func asmout(ctxt *obj.Link, p *obj.Prog, o *Optab, out []uint32) {
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if mask[1] != 63 {
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ctxt.Diag("invalid mask for rotate: %x (end != bit 63)\n%v", uint64(d), p)
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}
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o1 = LOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
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o1 |= (uint32(a) & 31) << 6
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if a&0x20 != 0 {
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o1 |= 1 << 5 /* mb[5] is top bit */
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}
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case ARLDCR, ARLDCRCC:
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var mask [2]uint8
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@ -2362,22 +2407,28 @@ func asmout(ctxt *obj.Link, p *obj.Prog, o *Optab, out []uint32) {
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if mask[0] != 0 {
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ctxt.Diag("invalid mask for rotate: %x (start != 0)\n%v", uint64(d), p)
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}
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o1 = LOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
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o1 |= (uint32(a) & 31) << 6
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if a&0x20 != 0 {
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o1 |= 1 << 5 /* mb[5] is top bit */
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}
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// These opcodes use a shift count like the ppc64 asm, no mask conversion done
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case ARLDICR, ARLDICRCC, ARLDICL, ARLDICLCC:
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a = int(d)
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case ARLDICR, ARLDICRCC:
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me := int(d)
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sh := regoff(ctxt, &p.From)
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o1 = AOP_RLDIC(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(me))
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case ARLDICL, ARLDICLCC:
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mb := int(d)
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sh := regoff(ctxt, &p.From)
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o1 = AOP_RLDIC(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(mb))
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default:
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ctxt.Diag("unexpected op in rldc case\n%v", p)
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a = 0
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}
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o1 = LOP_RRR(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
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o1 |= (uint32(a) & 31) << 6
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if a&0x20 != 0 {
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o1 |= 1 << 5 /* mb[5] is top bit */
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}
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case 17, /* bc bo,bi,lbra (same for now) */
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16: /* bc bo,bi,sbra */
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a := 0
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@ -3170,8 +3221,24 @@ func asmout(ctxt *obj.Link, p *obj.Prog, o *Optab, out []uint32) {
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/* 2-register operand order: XS, RA or RA, XT */
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xt := int32(p.To.Reg)
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xs := int32(p.From.Reg)
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if REG_VS0 <= xt && xt <= REG_VS63 {
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/* We need to treat the special case of extended mnemonics that may have a FREG/VREG as an argument */
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if REG_V0 <= xt && xt <= REG_V31 {
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/* Convert V0-V31 to VS32-VS63 */
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xt = xt + 64
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o1 = AOP_XX1(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
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} else if REG_F0 <= xt && xt <= REG_F31 {
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/* Convert F0-F31 to VS0-VS31 */
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xt = xt + 64
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o1 = AOP_XX1(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
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} else if REG_VS0 <= xt && xt <= REG_VS63 {
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o1 = AOP_XX1(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
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} else if REG_V0 <= xs && xs <= REG_V31 {
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/* Likewise for XS */
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xs = xs + 64
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o1 = AOP_XX1(oprrr(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
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} else if REG_F0 <= xs && xs <= REG_F31 {
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xs = xs + 64
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o1 = AOP_XX1(oprrr(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
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||||
} else if REG_VS0 <= xs && xs <= REG_VS63 {
|
||||
o1 = AOP_XX1(oprrr(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
|
||||
}
|
||||
@ -3199,6 +3266,30 @@ func asmout(ctxt *obj.Link, p *obj.Prog, o *Optab, out []uint32) {
|
||||
/* 3-register operand order: XA, XB, XC, XT */
|
||||
o1 = AOP_XX4(oprrr(ctxt, p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.From3.Reg))
|
||||
|
||||
case 92: /* X-form instructions, 3-operands */
|
||||
if p.To.Type == obj.TYPE_CONST {
|
||||
/* imm reg reg */
|
||||
/* operand order: FRA, FRB, BF */
|
||||
bf := int(regoff(ctxt, &p.To)) << 2
|
||||
o1 = AOP_RRR(opirr(ctxt, p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg))
|
||||
} else if p.To.Type == obj.TYPE_REG {
|
||||
/* reg reg reg */
|
||||
/* operand order: RS, RB, RA */
|
||||
o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
|
||||
}
|
||||
|
||||
case 93: /* X-form instructions, 2-operands */
|
||||
if p.To.Type == obj.TYPE_CONST {
|
||||
/* imm reg */
|
||||
/* operand order: FRB, BF */
|
||||
bf := int(regoff(ctxt, &p.To)) << 2
|
||||
o1 = AOP_RR(opirr(ctxt, p.As), uint32(bf), uint32(p.From.Reg))
|
||||
} else if p.Reg == 0 {
|
||||
/* popcnt* r,r, X-form */
|
||||
/* operand order: RS, RA */
|
||||
o1 = AOP_RRR(oprrr(ctxt, p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
out[0] = o1
|
||||
@ -3281,6 +3372,8 @@ func oprrr(ctxt *obj.Link, a obj.As) uint32 {
|
||||
return OPVCC(31, 0, 0, 0) /* L=0 */
|
||||
case ACMPWU:
|
||||
return OPVCC(31, 32, 0, 0)
|
||||
case ACMPB:
|
||||
return OPVCC(31, 508, 0, 0) /* cmpb - v2.05 */
|
||||
|
||||
case ACNTLZW:
|
||||
return OPVCC(31, 26, 0, 0)
|
||||
@ -3621,6 +3714,13 @@ func oprrr(ctxt *obj.Link, a obj.As) uint32 {
|
||||
case AORNCC:
|
||||
return OPVCC(31, 412, 0, 1)
|
||||
|
||||
case APOPCNTD:
|
||||
return OPVCC(31, 506, 0, 0) /* popcntd - v2.06 */
|
||||
case APOPCNTW:
|
||||
return OPVCC(31, 378, 0, 0) /* popcntw - v2.06 */
|
||||
case APOPCNTB:
|
||||
return OPVCC(31, 122, 0, 0) /* popcntb - v2.02 */
|
||||
|
||||
case ARFI:
|
||||
return OPVCC(19, 50, 0, 0)
|
||||
case ARFCI:
|
||||
@ -3757,14 +3857,14 @@ func oprrr(ctxt *obj.Link, a obj.As) uint32 {
|
||||
/* Vector (VMX/Altivec) instructions */
|
||||
/* ISA 2.03 enables these for PPC970. For POWERx processors, these */
|
||||
/* are enabled starting at POWER6 (ISA 2.05). */
|
||||
case AVANDL:
|
||||
case AVAND:
|
||||
return OPVX(4, 1028, 0, 0) /* vand - v2.03 */
|
||||
case AVANDC:
|
||||
return OPVX(4, 1092, 0, 0) /* vandc - v2.03 */
|
||||
case AVNAND:
|
||||
return OPVX(4, 1412, 0, 0) /* vnand - v2.07 */
|
||||
|
||||
case AVORL:
|
||||
case AVOR:
|
||||
return OPVX(4, 1156, 0, 0) /* vor - v2.03 */
|
||||
case AVORC:
|
||||
return OPVX(4, 1348, 0, 0) /* vorc - v2.07 */
|
||||
@ -3810,6 +3910,15 @@ func oprrr(ctxt *obj.Link, a obj.As) uint32 {
|
||||
case AVADDECUQ:
|
||||
return OPVX(4, 61, 0, 0) /* vaddecuq - v2.07 */
|
||||
|
||||
case AVPMSUMB:
|
||||
return OPVX(4, 1032, 0, 0) /* vpmsumb - v2.07 */
|
||||
case AVPMSUMH:
|
||||
return OPVX(4, 1096, 0, 0) /* vpmsumh - v2.07 */
|
||||
case AVPMSUMW:
|
||||
return OPVX(4, 1160, 0, 0) /* vpmsumw - v2.07 */
|
||||
case AVPMSUMD:
|
||||
return OPVX(4, 1224, 0, 0) /* vpmsumd - v2.07 */
|
||||
|
||||
case AVSUBUBM:
|
||||
return OPVX(4, 1024, 0, 0) /* vsububm - v2.03 */
|
||||
case AVSUBUHM:
|
||||
@ -3976,12 +4085,12 @@ func oprrr(ctxt *obj.Link, a obj.As) uint32 {
|
||||
|
||||
/* Vector scalar (VSX) instructions */
|
||||
/* ISA 2.06 enables these for POWER7. */
|
||||
case AMFVSRD:
|
||||
case AMFVSRD, AMFVRD, AMFFPRD:
|
||||
return OPVXX1(31, 51, 0) /* mfvsrd - v2.07 */
|
||||
case AMFVSRWZ:
|
||||
return OPVXX1(31, 115, 0) /* mfvsrwz - v2.07 */
|
||||
|
||||
case AMTVSRD:
|
||||
case AMTVSRD, AMTFPRD, AMTVRD:
|
||||
return OPVXX1(31, 179, 0) /* mtvsrd - v2.07 */
|
||||
case AMTVSRWA:
|
||||
return OPVXX1(31, 211, 0) /* mtvsrwa - v2.07 */
|
||||
@ -4260,6 +4369,11 @@ func opirr(ctxt *obj.Link, a obj.As) uint32 {
|
||||
return OPVX(4, 908, 0, 0) /* vspltisw - v2.03 */
|
||||
/* End of vector instructions */
|
||||
|
||||
case AFTDIV:
|
||||
return OPVCC(63, 128, 0, 0) /* ftdiv - v2.06 */
|
||||
case AFTSQRT:
|
||||
return OPVCC(63, 160, 0, 0) /* ftsqrt - v2.06 */
|
||||
|
||||
case AXOR:
|
||||
return OPVCC(26, 0, 0, 0) /* XORIL */
|
||||
case -AXOR:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user