cmd/asm,cmd/internal/obj/ppc64: recognize ppc64 ISA 3.1 MMA registers

Allow the assembler frontend to match MMA register arguments added by
ISA 3.1. The prefix "A" (for accumulator) is chosen to identify them.

Updates #44549

Change-Id: I363e7d1103aee19d7966829d2079c3d876621efc
Reviewed-on: https://go-review.googlesource.com/c/go/+/419534
Reviewed-by: Cherry Mui <cherryyz@google.com>
Run-TryBot: Paul Murphy <murp@ibm.com>
Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com>
TryBot-Result: Gopher Robot <gobot@golang.org>
Reviewed-by: Michael Knyszek <mknyszek@google.com>

src/cmd/asm/internal/arch/arch.go

@@ -336,6 +336,9 @@ func archPPC64(linkArch *obj.LinkArch) *Arch {
 	for i := ppc64.REG_VS0; i <= ppc64.REG_VS63; i++ {
 		register[obj.Rconv(i)] = int16(i)
 	}
+	for i := ppc64.REG_A0; i <= ppc64.REG_A7; i++ {
+		register[obj.Rconv(i)] = int16(i)
+	}
 	for i := ppc64.REG_CR0; i <= ppc64.REG_CR7; i++ {
 		register[obj.Rconv(i)] = int16(i)
 	}

src/cmd/asm/internal/arch/ppc64.go

@@ -77,6 +77,10 @@ func ppc64RegisterNumber(name string, n int16) (int16, bool) {
 		if 0 <= n && n <= 7 {
 			return ppc64.REG_CR0 + n, true
 		}
+	case "A":
+		if 0 <= n && n <= 8 {
+			return ppc64.REG_A0 + n, true
+		}
 	case "VS":
 		if 0 <= n && n <= 63 {
 			return ppc64.REG_VS0 + n, true

src/cmd/internal/obj/ppc64/a.out.go

@@ -258,6 +258,18 @@ const (
 	REG_CR6
 	REG_CR7
 
+	// MMA accumulator registers, these shadow VSR 0-31
+	// e.g MMAx shadows VSRx*4-VSRx*4+3 or
+	//     MMA0 shadows VSR0-VSR3
+	REG_A0
+	REG_A1
+	REG_A2
+	REG_A3
+	REG_A4
+	REG_A5
+	REG_A6
+	REG_A7
+
 	REG_MSR
 	REG_FPSCR
 	REG_CR
@@ -399,6 +411,7 @@ const (
 	C_CREG     /* The condition registor (CR) */
 	C_CRBIT    /* A single bit of the CR register (0-31) */
 	C_SPR      /* special processor register */
+	C_AREG     /* MMA accumulator register */
 	C_ZCON     /* The constant zero */
 	C_U1CON    /* 1 bit unsigned constant */
 	C_U2CON    /* 2 bit unsigned constant */

src/cmd/internal/obj/ppc64/anames9.go

@@ -16,6 +16,7 @@ var cnames9 = []string{
 	"CREG",
 	"CRBIT",
 	"SPR",
+	"MREG",
 	"ZCON",
 	"U1CON",
 	"U2CON",

src/cmd/internal/obj/ppc64/asm9.go

@@ -882,6 +882,9 @@ func (c *ctxt9) aclassreg(reg int16) int {
 
 		return C_SPR
 	}
+	if REG_A0 <= reg && reg <= REG_A7 {
+		return C_AREG
+	}
 	if reg == REG_FPSCR {
 		return C_FPSCR
 	}

src/cmd/internal/obj/ppc64/asm_test.go

@@ -469,6 +469,7 @@ func TestAddrClassifier(t *testing.T) {
 		{obj.Addr{Type: obj.TYPE_REG, Reg: REG_SPR0 + 8}, C_LR},
 		{obj.Addr{Type: obj.TYPE_REG, Reg: REG_SPR0 + 9}, C_CTR},
 		{obj.Addr{Type: obj.TYPE_REG, Reg: REG_FPSCR}, C_FPSCR},
+		{obj.Addr{Type: obj.TYPE_REG, Reg: REG_A1}, C_AREG},
 
 		// Memory type arguments.
 		{obj.Addr{Type: obj.TYPE_MEM, Name: obj.NAME_GOTREF}, C_ADDR},

src/cmd/internal/obj/ppc64/list9.go

@@ -67,6 +67,9 @@ func rconv(r int) string {
 		crf := (r - REG_CR0LT) / 4
 		return fmt.Sprintf("CR%d%s", crf, bits[r%4])
 	}
+	if REG_A0 <= r && r <= REG_A7 {
+		return fmt.Sprintf("A%d", r-REG_A0)
+	}
 	if r == REG_CR {
 		return "CR"
 	}