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cmd/compile: improve s390x rules for folding ADDconst into loads/stores
There is no benefit to folding ADDconsts unless the resultant immediate will fit into a 20-bit signed integer, so limit these rules accordingly. Also the signed load operations were missing, so I've added them, and I've also removed some MOVDaddr rules that were dead code (MOVDaddrs are rematerializable on s390x which means they can't take inputs other than SP or SB). Change-Id: Iebeba78da37d3d71d32d4b7f49fe4ea9095d40ec Reviewed-on: https://go-review.googlesource.com/30616 Run-TryBot: Michael Munday <munday@ca.ibm.com> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Keith Randall <khr@golang.org> Reviewed-by: David Chase <drchase@google.com>
This commit is contained in:
Michael Munday
David Chase
parent
d7b34d5f29
commit
807a7ebd51
@ -553,18 +553,15 @@
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(MULLWconst [c] x) && isPowerOfTwo(c-1) && c >= 17 -> (ADDW (SLWconst <v.Type> [log2(c-1)] x) x)
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// Fold ADD into MOVDaddr. Odd offsets from SB shouldn't be folded (LARL can't handle them).
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(ADDconst [c] (MOVDaddr [d] {s} x)) && ((c+d)&1 == 0) && is32Bit(c+d) -> (MOVDaddr [c+d] {s} x)
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(MOVDaddr [c] {s} (ADDconst [d] x)) && ((c+d)&1 == 0) && is32Bit(c+d) -> (MOVDaddr [c+d] {s} x)
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(ADDconst [c] (MOVDaddr [d] {s} x)) && x.Op != OpSB && is32Bit(c+d) -> (MOVDaddr [c+d] {s} x)
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(MOVDaddr [c] {s} (ADDconst [d] x)) && x.Op != OpSB && is32Bit(c+d) -> (MOVDaddr [c+d] {s} x)
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(MOVDaddr [c] {s} (ADD x y)) && x.Op != OpSB && y.Op != OpSB -> (MOVDaddridx [c] {s} x y)
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(ADDconst [c] (MOVDaddr [d] {s} x:(SB))) && ((c+d)&1 == 0) && is32Bit(c+d) -> (MOVDaddr [c+d] {s} x)
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(ADDconst [c] (MOVDaddr [d] {s} x)) && x.Op != OpSB && is20Bit(c+d) -> (MOVDaddr [c+d] {s} x)
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(ADD x (MOVDaddr [c] {s} y)) && x.Op != OpSB && y.Op != OpSB -> (MOVDaddridx [c] {s} x y)
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(ADD (MOVDaddr [c] {s} x) y) && x.Op != OpSB && y.Op != OpSB -> (MOVDaddridx [c] {s} x y)
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// fold ADDconst into MOVDaddrx
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(ADDconst [c] (MOVDaddridx [d] {s} x y)) && is32Bit(c+d) -> (MOVDaddridx [c+d] {s} x y)
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(MOVDaddridx [c] {s} (ADDconst [d] x) y) && is32Bit(c+d) && x.Op != OpSB -> (MOVDaddridx [c+d] {s} x y)
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(MOVDaddridx [c] {s} x (ADDconst [d] y)) && is32Bit(c+d) && y.Op != OpSB -> (MOVDaddridx [c+d] {s} x y)
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(ADDconst [c] (MOVDaddridx [d] {s} x y)) && is20Bit(c+d) -> (MOVDaddridx [c+d] {s} x y)
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(MOVDaddridx [c] {s} (ADDconst [d] x) y) && is20Bit(c+d) && x.Op != OpSB -> (MOVDaddridx [c+d] {s} x y)
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(MOVDaddridx [c] {s} x (ADDconst [d] y)) && is20Bit(c+d) && y.Op != OpSB -> (MOVDaddridx [c+d] {s} x y)
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// reverse ordering of compare instruction
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(MOVDLT x y (InvertFlags cmp)) -> (MOVDGT x y cmp)
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@ -662,19 +659,22 @@
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// the ADDconst get eliminated, we still have to compute the ADDconst and we now
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// have potentially two live values (ptr and (ADDconst [off] ptr)) instead of one.
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// Nevertheless, let's do it!
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(MOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVDload [off1+off2] {sym} ptr mem)
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(MOVWZload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVWZload [off1+off2] {sym} ptr mem)
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(MOVHZload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVHZload [off1+off2] {sym} ptr mem)
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(MOVBZload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2) -> (MOVBZload [off1+off2] {sym} ptr mem)
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(FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2) -> (FMOVSload [off1+off2] {sym} ptr mem)
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(FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(off1+off2) -> (FMOVDload [off1+off2] {sym} ptr mem)
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(MOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVDload [off1+off2] {sym} ptr mem)
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(MOVWload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVWload [off1+off2] {sym} ptr mem)
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(MOVHload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVHload [off1+off2] {sym} ptr mem)
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(MOVBload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVBload [off1+off2] {sym} ptr mem)
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(MOVWZload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVWZload [off1+off2] {sym} ptr mem)
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(MOVHZload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVHZload [off1+off2] {sym} ptr mem)
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(MOVBZload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (MOVBZload [off1+off2] {sym} ptr mem)
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(FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (FMOVSload [off1+off2] {sym} ptr mem)
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(FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is20Bit(off1+off2) -> (FMOVDload [off1+off2] {sym} ptr mem)
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(MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVDstore [off1+off2] {sym} ptr val mem)
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(MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVWstore [off1+off2] {sym} ptr val mem)
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(MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVHstore [off1+off2] {sym} ptr val mem)
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(MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (MOVBstore [off1+off2] {sym} ptr val mem)
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(FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (FMOVSstore [off1+off2] {sym} ptr val mem)
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(FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(off1+off2) -> (FMOVDstore [off1+off2] {sym} ptr val mem)
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(MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is20Bit(off1+off2) -> (MOVDstore [off1+off2] {sym} ptr val mem)
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(MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is20Bit(off1+off2) -> (MOVWstore [off1+off2] {sym} ptr val mem)
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(MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is20Bit(off1+off2) -> (MOVHstore [off1+off2] {sym} ptr val mem)
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(MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is20Bit(off1+off2) -> (MOVBstore [off1+off2] {sym} ptr val mem)
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(FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is20Bit(off1+off2) -> (FMOVSstore [off1+off2] {sym} ptr val mem)
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(FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is20Bit(off1+off2) -> (FMOVDstore [off1+off2] {sym} ptr val mem)
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// Fold constants into stores.
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(MOVDstore [off] {sym} ptr (MOVDconst [c]) mem) && validValAndOff(c,off) && int64(int16(c)) == c && ptr.Op != OpSB ->
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@ -809,20 +809,12 @@
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(FMOVSstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (FMOVSstoreidx [c+d] {sym} ptr idx val mem)
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(FMOVDstoreidx [c] {sym} ptr (ADDconst [d] idx) val mem) -> (FMOVDstoreidx [c+d] {sym} ptr idx val mem)
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// fold MOVDaddrs together
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(MOVDaddr [off1] {sym1} (MOVDaddr [off2] {sym2} x)) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
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(MOVDaddr [off1+off2] {mergeSym(sym1,sym2)} x)
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// MOVDaddr into MOVDaddridx
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(MOVDaddridx [off1] {sym1} (MOVDaddr [off2] {sym2} x) y) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && x.Op != OpSB ->
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(MOVDaddridx [off1+off2] {mergeSym(sym1,sym2)} x y)
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(MOVDaddridx [off1] {sym1} x (MOVDaddr [off2] {sym2} y)) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) && y.Op != OpSB ->
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(MOVDaddridx [off1+off2] {mergeSym(sym1,sym2)} x y)
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// MOVDaddridx into MOVDaddr
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(MOVDaddr [off1] {sym1} (MOVDaddridx [off2] {sym2} x y)) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
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(MOVDaddridx [off1+off2] {mergeSym(sym1,sym2)} x y)
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// Absorb InvertFlags into branches.
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(LT (InvertFlags cmp) yes no) -> (GT cmp yes no)
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(GT (InvertFlags cmp) yes no) -> (LT cmp yes no)
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@ -518,8 +518,6 @@ func rewriteValueS390X(v *Value, config *Config) bool {
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return rewriteValueS390X_OpS390XMOVDLT(v, config)
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case OpS390XMOVDNE:
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return rewriteValueS390X_OpS390XMOVDNE(v, config)
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case OpS390XMOVDaddr:
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return rewriteValueS390X_OpS390XMOVDaddr(v, config)
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case OpS390XMOVDaddridx:
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return rewriteValueS390X_OpS390XMOVDaddridx(v, config)
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case OpS390XMOVDload:
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@ -6058,7 +6056,7 @@ func rewriteValueS390X_OpS390XADDWconst(v *Value, config *Config) bool {
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func rewriteValueS390X_OpS390XADDconst(v *Value, config *Config) bool {
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b := v.Block
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_ = b
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// match: (ADDconst [c] (MOVDaddr [d] {s} x))
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// match: (ADDconst [c] (MOVDaddr [d] {s} x:(SB)))
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// cond: ((c+d)&1 == 0) && is32Bit(c+d)
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// result: (MOVDaddr [c+d] {s} x)
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for {
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@ -6070,6 +6068,9 @@ func rewriteValueS390X_OpS390XADDconst(v *Value, config *Config) bool {
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d := v_0.AuxInt
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s := v_0.Aux
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x := v_0.Args[0]
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if x.Op != OpSB {
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break
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}
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if !(((c+d)&1 == 0) && is32Bit(c+d)) {
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break
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}
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@ -6080,7 +6081,7 @@ func rewriteValueS390X_OpS390XADDconst(v *Value, config *Config) bool {
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return true
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}
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// match: (ADDconst [c] (MOVDaddr [d] {s} x))
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// cond: x.Op != OpSB && is32Bit(c+d)
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// cond: x.Op != OpSB && is20Bit(c+d)
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// result: (MOVDaddr [c+d] {s} x)
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for {
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c := v.AuxInt
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@ -6091,7 +6092,7 @@ func rewriteValueS390X_OpS390XADDconst(v *Value, config *Config) bool {
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d := v_0.AuxInt
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s := v_0.Aux
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x := v_0.Args[0]
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if !(x.Op != OpSB && is32Bit(c+d)) {
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if !(x.Op != OpSB && is20Bit(c+d)) {
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break
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}
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v.reset(OpS390XMOVDaddr)
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@ -6101,7 +6102,7 @@ func rewriteValueS390X_OpS390XADDconst(v *Value, config *Config) bool {
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return true
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}
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// match: (ADDconst [c] (MOVDaddridx [d] {s} x y))
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// cond: is32Bit(c+d)
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// cond: is20Bit(c+d)
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// result: (MOVDaddridx [c+d] {s} x y)
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for {
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c := v.AuxInt
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@ -6113,7 +6114,7 @@ func rewriteValueS390X_OpS390XADDconst(v *Value, config *Config) bool {
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s := v_0.Aux
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x := v_0.Args[0]
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y := v_0.Args[1]
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if !(is32Bit(c + d)) {
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if !(is20Bit(c + d)) {
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break
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}
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v.reset(OpS390XMOVDaddridx)
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@ -7171,8 +7172,8 @@ func rewriteValueS390X_OpS390XCMPconst(v *Value, config *Config) bool {
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func rewriteValueS390X_OpS390XFMOVDload(v *Value, config *Config) bool {
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b := v.Block
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_ = b
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// match: (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem)
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// cond: is32Bit(off1+off2)
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// match: (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem)
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// cond: is20Bit(off1+off2)
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// result: (FMOVDload [off1+off2] {sym} ptr mem)
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for {
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off1 := v.AuxInt
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@ -7184,7 +7185,7 @@ func rewriteValueS390X_OpS390XFMOVDload(v *Value, config *Config) bool {
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off2 := v_0.AuxInt
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ptr := v_0.Args[0]
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mem := v.Args[1]
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if !(is32Bit(off1 + off2)) {
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if !(is20Bit(off1 + off2)) {
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break
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}
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v.reset(OpS390XFMOVDload)
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@ -7323,7 +7324,7 @@ func rewriteValueS390X_OpS390XFMOVDstore(v *Value, config *Config) bool {
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b := v.Block
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_ = b
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// match: (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem)
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// cond: is32Bit(off1+off2)
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// cond: is20Bit(off1+off2)
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// result: (FMOVDstore [off1+off2] {sym} ptr val mem)
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for {
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off1 := v.AuxInt
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@ -7336,7 +7337,7 @@ func rewriteValueS390X_OpS390XFMOVDstore(v *Value, config *Config) bool {
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ptr := v_0.Args[0]
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val := v.Args[1]
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mem := v.Args[2]
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if !(is32Bit(off1 + off2)) {
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if !(is20Bit(off1 + off2)) {
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break
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}
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v.reset(OpS390XFMOVDstore)
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@ -7485,8 +7486,8 @@ func rewriteValueS390X_OpS390XFMOVDstoreidx(v *Value, config *Config) bool {
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func rewriteValueS390X_OpS390XFMOVSload(v *Value, config *Config) bool {
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b := v.Block
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_ = b
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// match: (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem)
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// cond: is32Bit(off1+off2)
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// match: (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem)
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// cond: is20Bit(off1+off2)
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// result: (FMOVSload [off1+off2] {sym} ptr mem)
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for {
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off1 := v.AuxInt
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@ -7498,7 +7499,7 @@ func rewriteValueS390X_OpS390XFMOVSload(v *Value, config *Config) bool {
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off2 := v_0.AuxInt
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ptr := v_0.Args[0]
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mem := v.Args[1]
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if !(is32Bit(off1 + off2)) {
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if !(is20Bit(off1 + off2)) {
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break
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}
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v.reset(OpS390XFMOVSload)
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@ -7637,7 +7638,7 @@ func rewriteValueS390X_OpS390XFMOVSstore(v *Value, config *Config) bool {
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b := v.Block
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_ = b
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// match: (FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem)
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// cond: is32Bit(off1+off2)
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// cond: is20Bit(off1+off2)
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// result: (FMOVSstore [off1+off2] {sym} ptr val mem)
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for {
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off1 := v.AuxInt
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@ -7650,7 +7651,7 @@ func rewriteValueS390X_OpS390XFMOVSstore(v *Value, config *Config) bool {
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ptr := v_0.Args[0]
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val := v.Args[1]
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mem := v.Args[2]
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if !(is32Bit(off1 + off2)) {
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if !(is20Bit(off1 + off2)) {
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break
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}
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v.reset(OpS390XFMOVSstore)
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@ -7823,8 +7824,8 @@ func rewriteValueS390X_OpS390XMOVBZload(v *Value, config *Config) bool {
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return true
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}
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// match: (MOVBZload [off1] {sym} (ADDconst [off2] ptr) mem)
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// cond: is32Bit(off1+off2)
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// result: (MOVBZload [off1+off2] {sym} ptr mem)
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// cond: is20Bit(off1+off2)
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// result: (MOVBZload [off1+off2] {sym} ptr mem)
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for {
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off1 := v.AuxInt
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sym := v.Aux
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@ -7835,7 +7836,7 @@ func rewriteValueS390X_OpS390XMOVBZload(v *Value, config *Config) bool {
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off2 := v_0.AuxInt
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ptr := v_0.Args[0]
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mem := v.Args[1]
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if !(is32Bit(off1 + off2)) {
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if !(is20Bit(off1 + off2)) {
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break
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}
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v.reset(OpS390XMOVBZload)
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@ -8294,6 +8295,29 @@ func rewriteValueS390X_OpS390XMOVBZreg(v *Value, config *Config) bool {
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func rewriteValueS390X_OpS390XMOVBload(v *Value, config *Config) bool {
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b := v.Block
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_ = b
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// match: (MOVBload [off1] {sym} (ADDconst [off2] ptr) mem)
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// cond: is20Bit(off1+off2)
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// result: (MOVBload [off1+off2] {sym} ptr mem)
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for {
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off1 := v.AuxInt
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sym := v.Aux
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v_0 := v.Args[0]
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if v_0.Op != OpS390XADDconst {
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break
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}
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off2 := v_0.AuxInt
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ptr := v_0.Args[0]
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mem := v.Args[1]
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if !(is20Bit(off1 + off2)) {
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break
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}
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v.reset(OpS390XMOVBload)
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v.AuxInt = off1 + off2
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v.Aux = sym
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v.AddArg(ptr)
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v.AddArg(mem)
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return true
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}
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// match: (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem)
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// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
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// result: (MOVBload [off1+off2] {mergeSym(sym1,sym2)} base mem)
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@ -8452,7 +8476,7 @@ func rewriteValueS390X_OpS390XMOVBstore(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
// match: (MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem)
|
||||
// cond: is32Bit(off1+off2)
|
||||
// cond: is20Bit(off1+off2)
|
||||
// result: (MOVBstore [off1+off2] {sym} ptr val mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
@ -8465,7 +8489,7 @@ func rewriteValueS390X_OpS390XMOVBstore(v *Value, config *Config) bool {
|
||||
ptr := v_0.Args[0]
|
||||
val := v.Args[1]
|
||||
mem := v.Args[2]
|
||||
if !(is32Bit(off1 + off2)) {
|
||||
if !(is20Bit(off1 + off2)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpS390XMOVBstore)
|
||||
@ -9867,126 +9891,11 @@ func rewriteValueS390X_OpS390XMOVDNE(v *Value, config *Config) bool {
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValueS390X_OpS390XMOVDaddr(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (MOVDaddr [c] {s} (ADDconst [d] x))
|
||||
// cond: ((c+d)&1 == 0) && is32Bit(c+d)
|
||||
// result: (MOVDaddr [c+d] {s} x)
|
||||
for {
|
||||
c := v.AuxInt
|
||||
s := v.Aux
|
||||
v_0 := v.Args[0]
|
||||
if v_0.Op != OpS390XADDconst {
|
||||
break
|
||||
}
|
||||
d := v_0.AuxInt
|
||||
x := v_0.Args[0]
|
||||
if !(((c+d)&1 == 0) && is32Bit(c+d)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpS390XMOVDaddr)
|
||||
v.AuxInt = c + d
|
||||
v.Aux = s
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
// match: (MOVDaddr [c] {s} (ADDconst [d] x))
|
||||
// cond: x.Op != OpSB && is32Bit(c+d)
|
||||
// result: (MOVDaddr [c+d] {s} x)
|
||||
for {
|
||||
c := v.AuxInt
|
||||
s := v.Aux
|
||||
v_0 := v.Args[0]
|
||||
if v_0.Op != OpS390XADDconst {
|
||||
break
|
||||
}
|
||||
d := v_0.AuxInt
|
||||
x := v_0.Args[0]
|
||||
if !(x.Op != OpSB && is32Bit(c+d)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpS390XMOVDaddr)
|
||||
v.AuxInt = c + d
|
||||
v.Aux = s
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
// match: (MOVDaddr [c] {s} (ADD x y))
|
||||
// cond: x.Op != OpSB && y.Op != OpSB
|
||||
// result: (MOVDaddridx [c] {s} x y)
|
||||
for {
|
||||
c := v.AuxInt
|
||||
s := v.Aux
|
||||
v_0 := v.Args[0]
|
||||
if v_0.Op != OpS390XADD {
|
||||
break
|
||||
}
|
||||
x := v_0.Args[0]
|
||||
y := v_0.Args[1]
|
||||
if !(x.Op != OpSB && y.Op != OpSB) {
|
||||
break
|
||||
}
|
||||
v.reset(OpS390XMOVDaddridx)
|
||||
v.AuxInt = c
|
||||
v.Aux = s
|
||||
v.AddArg(x)
|
||||
v.AddArg(y)
|
||||
return true
|
||||
}
|
||||
// match: (MOVDaddr [off1] {sym1} (MOVDaddr [off2] {sym2} x))
|
||||
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
|
||||
// result: (MOVDaddr [off1+off2] {mergeSym(sym1,sym2)} x)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym1 := v.Aux
|
||||
v_0 := v.Args[0]
|
||||
if v_0.Op != OpS390XMOVDaddr {
|
||||
break
|
||||
}
|
||||
off2 := v_0.AuxInt
|
||||
sym2 := v_0.Aux
|
||||
x := v_0.Args[0]
|
||||
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpS390XMOVDaddr)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = mergeSym(sym1, sym2)
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
// match: (MOVDaddr [off1] {sym1} (MOVDaddridx [off2] {sym2} x y))
|
||||
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
|
||||
// result: (MOVDaddridx [off1+off2] {mergeSym(sym1,sym2)} x y)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym1 := v.Aux
|
||||
v_0 := v.Args[0]
|
||||
if v_0.Op != OpS390XMOVDaddridx {
|
||||
break
|
||||
}
|
||||
off2 := v_0.AuxInt
|
||||
sym2 := v_0.Aux
|
||||
x := v_0.Args[0]
|
||||
y := v_0.Args[1]
|
||||
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpS390XMOVDaddridx)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = mergeSym(sym1, sym2)
|
||||
v.AddArg(x)
|
||||
v.AddArg(y)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValueS390X_OpS390XMOVDaddridx(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (MOVDaddridx [c] {s} (ADDconst [d] x) y)
|
||||
// cond: is32Bit(c+d) && x.Op != OpSB
|
||||
// cond: is20Bit(c+d) && x.Op != OpSB
|
||||
// result: (MOVDaddridx [c+d] {s} x y)
|
||||
for {
|
||||
c := v.AuxInt
|
||||
@ -9998,7 +9907,7 @@ func rewriteValueS390X_OpS390XMOVDaddridx(v *Value, config *Config) bool {
|
||||
d := v_0.AuxInt
|
||||
x := v_0.Args[0]
|
||||
y := v.Args[1]
|
||||
if !(is32Bit(c+d) && x.Op != OpSB) {
|
||||
if !(is20Bit(c+d) && x.Op != OpSB) {
|
||||
break
|
||||
}
|
||||
v.reset(OpS390XMOVDaddridx)
|
||||
@ -10009,7 +9918,7 @@ func rewriteValueS390X_OpS390XMOVDaddridx(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
// match: (MOVDaddridx [c] {s} x (ADDconst [d] y))
|
||||
// cond: is32Bit(c+d) && y.Op != OpSB
|
||||
// cond: is20Bit(c+d) && y.Op != OpSB
|
||||
// result: (MOVDaddridx [c+d] {s} x y)
|
||||
for {
|
||||
c := v.AuxInt
|
||||
@ -10021,7 +9930,7 @@ func rewriteValueS390X_OpS390XMOVDaddridx(v *Value, config *Config) bool {
|
||||
}
|
||||
d := v_1.AuxInt
|
||||
y := v_1.Args[0]
|
||||
if !(is32Bit(c+d) && y.Op != OpSB) {
|
||||
if !(is20Bit(c+d) && y.Op != OpSB) {
|
||||
break
|
||||
}
|
||||
v.reset(OpS390XMOVDaddridx)
|
||||
@ -10107,8 +10016,8 @@ func rewriteValueS390X_OpS390XMOVDload(v *Value, config *Config) bool {
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
// match: (MOVDload [off1] {sym} (ADDconst [off2] ptr) mem)
|
||||
// cond: is32Bit(off1+off2)
|
||||
// match: (MOVDload [off1] {sym} (ADDconst [off2] ptr) mem)
|
||||
// cond: is20Bit(off1+off2)
|
||||
// result: (MOVDload [off1+off2] {sym} ptr mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
@ -10120,7 +10029,7 @@ func rewriteValueS390X_OpS390XMOVDload(v *Value, config *Config) bool {
|
||||
off2 := v_0.AuxInt
|
||||
ptr := v_0.Args[0]
|
||||
mem := v.Args[1]
|
||||
if !(is32Bit(off1 + off2)) {
|
||||
if !(is20Bit(off1 + off2)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpS390XMOVDload)
|
||||
@ -10259,7 +10168,7 @@ func rewriteValueS390X_OpS390XMOVDstore(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem)
|
||||
// cond: is32Bit(off1+off2)
|
||||
// cond: is20Bit(off1+off2)
|
||||
// result: (MOVDstore [off1+off2] {sym} ptr val mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
@ -10272,7 +10181,7 @@ func rewriteValueS390X_OpS390XMOVDstore(v *Value, config *Config) bool {
|
||||
ptr := v_0.Args[0]
|
||||
val := v.Args[1]
|
||||
mem := v.Args[2]
|
||||
if !(is32Bit(off1 + off2)) {
|
||||
if !(is20Bit(off1 + off2)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpS390XMOVDstore)
|
||||
@ -11025,8 +10934,8 @@ func rewriteValueS390X_OpS390XMOVHZload(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
// match: (MOVHZload [off1] {sym} (ADDconst [off2] ptr) mem)
|
||||
// cond: is32Bit(off1+off2)
|
||||
// result: (MOVHZload [off1+off2] {sym} ptr mem)
|
||||
// cond: is20Bit(off1+off2)
|
||||
// result: (MOVHZload [off1+off2] {sym} ptr mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym := v.Aux
|
||||
@ -11037,7 +10946,7 @@ func rewriteValueS390X_OpS390XMOVHZload(v *Value, config *Config) bool {
|
||||
off2 := v_0.AuxInt
|
||||
ptr := v_0.Args[0]
|
||||
mem := v.Args[1]
|
||||
if !(is32Bit(off1 + off2)) {
|
||||
if !(is20Bit(off1 + off2)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpS390XMOVHZload)
|
||||
@ -11314,6 +11223,29 @@ func rewriteValueS390X_OpS390XMOVHZreg(v *Value, config *Config) bool {
|
||||
func rewriteValueS390X_OpS390XMOVHload(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (MOVHload [off1] {sym} (ADDconst [off2] ptr) mem)
|
||||
// cond: is20Bit(off1+off2)
|
||||
// result: (MOVHload [off1+off2] {sym} ptr mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym := v.Aux
|
||||
v_0 := v.Args[0]
|
||||
if v_0.Op != OpS390XADDconst {
|
||||
break
|
||||
}
|
||||
off2 := v_0.AuxInt
|
||||
ptr := v_0.Args[0]
|
||||
mem := v.Args[1]
|
||||
if !(is20Bit(off1 + off2)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpS390XMOVHload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = sym
|
||||
v.AddArg(ptr)
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
// match: (MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem)
|
||||
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
|
||||
// result: (MOVHload [off1+off2] {mergeSym(sym1,sym2)} base mem)
|
||||
@ -11524,7 +11456,7 @@ func rewriteValueS390X_OpS390XMOVHstore(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
// match: (MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem)
|
||||
// cond: is32Bit(off1+off2)
|
||||
// cond: is20Bit(off1+off2)
|
||||
// result: (MOVHstore [off1+off2] {sym} ptr val mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
@ -11537,7 +11469,7 @@ func rewriteValueS390X_OpS390XMOVHstore(v *Value, config *Config) bool {
|
||||
ptr := v_0.Args[0]
|
||||
val := v.Args[1]
|
||||
mem := v.Args[2]
|
||||
if !(is32Bit(off1 + off2)) {
|
||||
if !(is20Bit(off1 + off2)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpS390XMOVHstore)
|
||||
@ -12400,8 +12332,8 @@ func rewriteValueS390X_OpS390XMOVWZload(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
// match: (MOVWZload [off1] {sym} (ADDconst [off2] ptr) mem)
|
||||
// cond: is32Bit(off1+off2)
|
||||
// result: (MOVWZload [off1+off2] {sym} ptr mem)
|
||||
// cond: is20Bit(off1+off2)
|
||||
// result: (MOVWZload [off1+off2] {sym} ptr mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym := v.Aux
|
||||
@ -12412,7 +12344,7 @@ func rewriteValueS390X_OpS390XMOVWZload(v *Value, config *Config) bool {
|
||||
off2 := v_0.AuxInt
|
||||
ptr := v_0.Args[0]
|
||||
mem := v.Args[1]
|
||||
if !(is32Bit(off1 + off2)) {
|
||||
if !(is20Bit(off1 + off2)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpS390XMOVWZload)
|
||||
@ -12715,6 +12647,29 @@ func rewriteValueS390X_OpS390XMOVWZreg(v *Value, config *Config) bool {
|
||||
func rewriteValueS390X_OpS390XMOVWload(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (MOVWload [off1] {sym} (ADDconst [off2] ptr) mem)
|
||||
// cond: is20Bit(off1+off2)
|
||||
// result: (MOVWload [off1+off2] {sym} ptr mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym := v.Aux
|
||||
v_0 := v.Args[0]
|
||||
if v_0.Op != OpS390XADDconst {
|
||||
break
|
||||
}
|
||||
off2 := v_0.AuxInt
|
||||
ptr := v_0.Args[0]
|
||||
mem := v.Args[1]
|
||||
if !(is20Bit(off1 + off2)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpS390XMOVWload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = sym
|
||||
v.AddArg(ptr)
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
// match: (MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} base) mem)
|
||||
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
|
||||
// result: (MOVWload [off1+off2] {mergeSym(sym1,sym2)} base mem)
|
||||
@ -12977,7 +12932,7 @@ func rewriteValueS390X_OpS390XMOVWstore(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
// match: (MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem)
|
||||
// cond: is32Bit(off1+off2)
|
||||
// cond: is20Bit(off1+off2)
|
||||
// result: (MOVWstore [off1+off2] {sym} ptr val mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
@ -12990,7 +12945,7 @@ func rewriteValueS390X_OpS390XMOVWstore(v *Value, config *Config) bool {
|
||||
ptr := v_0.Args[0]
|
||||
val := v.Args[1]
|
||||
mem := v.Args[2]
|
||||
if !(is32Bit(off1 + off2)) {
|
||||
if !(is20Bit(off1 + off2)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpS390XMOVWstore)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user