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https://github.com/golang/go
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cmd/internal/obj: instructions and registers for RISC-V
Start implementing an assembler for RISC-V - this provides register definitions and instruction mnemonics as defined in the RISC-V Instruction Set Manual, along with instruction encoding. The instruction encoding is generated by the parse_opcodes script with the "opcodes" and "opcodes-pseudo" files from (`make inst.go`): https://github.com/riscv/riscv-opcodes This is based on the riscv-go port: https://github.com/riscv/riscv-go Contributors to the riscv-go port are: Amol Bhave <ammubhave@gmail.com> Benjamin Barenblat <bbaren@google.com> Josh Bleecher Snyder <josharian@gmail.com> Michael Pratt <michael@pratt.im> Michael Yenik <myenik@google.com> Ronald G. Minnich <rminnich@gmail.com> Stefan O'Rear <sorear2@gmail.com> This port has been updated to Go 1.13: https://github.com/4a6f656c/riscv-go Updates #27532 Change-Id: I257b6de87e9864df61a2b0ce9be15968c1227b49 Reviewed-on: https://go-review.googlesource.com/c/go/+/193677 Run-TryBot: Brad Fitzpatrick <bradfitz@golang.org> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Cherry Zhang <cherryyz@google.com>
This commit is contained in:
Joel Sing
parent
112a72a020
commit
7ef890db91
@ -369,6 +369,7 @@ const (
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ABasePPC64
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ABaseARM64
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ABaseMIPS
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ABaseRISCV
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ABaseS390X
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ABaseWasm
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244
src/cmd/internal/obj/riscv/anames.go
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244
src/cmd/internal/obj/riscv/anames.go
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@ -0,0 +1,244 @@
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// Code generated by stringer -i cpu.go -o anames.go -p riscv; DO NOT EDIT.
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package riscv
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import "cmd/internal/obj"
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var Anames = []string{
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obj.A_ARCHSPECIFIC: "SLLIRV32",
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"SRLIRV32",
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"SRAIRV32",
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"JAL",
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"JALR",
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"BEQ",
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"BNE",
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"BLT",
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"BLTU",
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"BGE",
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"BGEU",
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"FENCE",
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"FENCEI",
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"FENCETSO",
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"ADDI",
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"SLTI",
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"SLTIU",
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"ANDI",
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"ORI",
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"XORI",
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"SLLI",
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"SRLI",
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"SRAI",
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"LUI",
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"AUIPC",
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"ADD",
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"SLT",
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"SLTU",
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"AND",
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"OR",
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"XOR",
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"SLL",
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"SRL",
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"SUB",
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"SRA",
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"ADDIW",
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"SLLIW",
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"SRLIW",
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"SRAIW",
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"ADDW",
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"SLLW",
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"SRLW",
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"SUBW",
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"SRAW",
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"LD",
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"LW",
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"LWU",
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"LH",
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"LHU",
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"LB",
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"LBU",
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"SD",
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"SW",
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"SH",
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"SB",
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"RDCYCLE",
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"RDCYCLEH",
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"RDTIME",
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"RDTIMEH",
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"RDINSTRET",
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"RDINSTRETH",
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"MUL",
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"MULH",
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"MULHU",
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"MULHSU",
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"MULW",
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"DIV",
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"DIVU",
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"REM",
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"REMU",
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"DIVW",
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"DIVUW",
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"REMW",
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"REMUW",
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"LRD",
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"SCD",
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"LRW",
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"SCW",
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"AMOSWAPD",
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"AMOADDD",
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"AMOANDD",
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"AMOORD",
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"AMOXORD",
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"AMOMAXD",
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"AMOMAXUD",
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"AMOMIND",
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"AMOMINUD",
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"AMOSWAPW",
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"AMOADDW",
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"AMOANDW",
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"AMOORW",
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"AMOXORW",
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"AMOMAXW",
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"AMOMAXUW",
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"AMOMINW",
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"AMOMINUW",
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"FRCSR",
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"FSCSR",
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"FRRM",
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"FSRM",
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"FRFLAGS",
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"FSFLAGS",
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"FSRMI",
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"FSFLAGSI",
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"FLW",
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"FSW",
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"FADDS",
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"FSUBS",
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"FMULS",
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"FDIVS",
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"FMINS",
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"FMAXS",
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"FSQRTS",
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"FMADDS",
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"FMSUBS",
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"FNMADDS",
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"FNMSUBS",
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"FCVTWS",
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"FCVTLS",
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"FCVTSW",
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"FCVTSL",
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"FCVTWUS",
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"FCVTLUS",
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"FCVTSWU",
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"FCVTSLU",
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"FSGNJS",
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"FSGNJNS",
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"FSGNJXS",
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"FMVSX",
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"FMVXS",
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"FMVWX",
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"FMVXW",
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"FEQS",
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"FLTS",
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"FLES",
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"FCLASSS",
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"FLD",
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"FSD",
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"FADDD",
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"FSUBD",
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"FMULD",
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"FDIVD",
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"FMIND",
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"FMAXD",
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"FSQRTD",
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"FMADDD",
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"FMSUBD",
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"FNMADDD",
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"FNMSUBD",
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"FCVTWD",
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"FCVTLD",
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"FCVTDW",
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"FCVTDL",
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"FCVTWUD",
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"FCVTLUD",
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"FCVTDWU",
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"FCVTDLU",
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"FCVTSD",
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"FCVTDS",
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"FSGNJD",
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"FSGNJND",
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"FSGNJXD",
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"FMVXD",
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"FMVDX",
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"FEQD",
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"FLTD",
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"FLED",
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"FCLASSD",
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"FLQ",
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"FSQ",
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"FADDQ",
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"FSUBQ",
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"FMULQ",
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"FDIVQ",
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"FMINQ",
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"FMAXQ",
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"FSQRTQ",
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"FMADDQ",
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"FMSUBQ",
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"FNMADDQ",
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"FNMSUBQ",
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"FCVTWQ",
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"FCVTLQ",
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"FCVTSQ",
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"FCVTDQ",
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"FCVTQW",
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"FCVTQL",
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"FCVTQS",
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"FCVTQD",
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"FCVTWUQ",
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"FCVTLUQ",
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"FCVTQWU",
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"FCVTQLU",
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"FSGNJQ",
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"FSGNJNQ",
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"FSGNJXQ",
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"FMVXQ",
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"FMVQX",
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"FEQQ",
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"FLEQ",
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"FLTQ",
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"FCLASSQ",
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"CSRRW",
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"CSRRS",
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"CSRRC",
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"CSRRWI",
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"CSRRSI",
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"CSRRCI",
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"ECALL",
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"SCALL",
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"EBREAK",
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"SBREAK",
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"MRET",
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"SRET",
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"URET",
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"DRET",
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"WFI",
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"SFENCEVMA",
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"HFENCEGVMA",
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"HFENCEVVMA",
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"WORD",
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"FNEGD",
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"FNEGS",
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"FNED",
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"FNES",
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"MOV",
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"MOVB",
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"MOVBU",
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"MOVF",
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"MOVD",
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"MOVH",
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"MOVHU",
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"MOVW",
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"MOVWU",
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"SEQZ",
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"SNEZ",
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}
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551
src/cmd/internal/obj/riscv/cpu.go
Normal file
551
src/cmd/internal/obj/riscv/cpu.go
Normal file
@ -0,0 +1,551 @@
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// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
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// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
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// Portions Copyright © 1997-1999 Vita Nuova Limited
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// Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
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// Portions Copyright © 2004,2006 Bruce Ellis
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// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
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// Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
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// Portions Copyright © 2009 The Go Authors. All rights reserved.
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// Portions Copyright © 2019 The Go Authors. All rights reserved.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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package riscv
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import "cmd/internal/obj"
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//go:generate go run ../stringer.go -i $GOFILE -o anames.go -p riscv
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const (
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// Base register numberings.
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REG_X0 = obj.RBaseRISCV + iota
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REG_X1
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REG_X2
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REG_X3
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REG_X4
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REG_X5
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REG_X6
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REG_X7
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REG_X8
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REG_X9
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REG_X10
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REG_X11
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REG_X12
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REG_X13
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REG_X14
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REG_X15
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REG_X16
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REG_X17
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REG_X18
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REG_X19
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REG_X20
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REG_X21
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REG_X22
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REG_X23
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REG_X24
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REG_X25
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REG_X26
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REG_X27
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REG_X28
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REG_X29
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REG_X30
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REG_X31
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// FP register numberings.
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REG_F0
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REG_F1
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REG_F2
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REG_F3
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REG_F4
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REG_F5
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REG_F6
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REG_F7
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REG_F8
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REG_F9
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REG_F10
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REG_F11
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REG_F12
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REG_F13
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REG_F14
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REG_F15
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REG_F16
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REG_F17
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REG_F18
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REG_F19
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REG_F20
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REG_F21
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REG_F22
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REG_F23
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REG_F24
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REG_F25
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REG_F26
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REG_F27
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REG_F28
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REG_F29
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REG_F30
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REG_F31
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// This marks the end of the register numbering.
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REG_END
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// General registers reassigned to ABI names.
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REG_ZERO = REG_X0
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REG_RA = REG_X1
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REG_SP = REG_X2
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REG_GP = REG_X3 // aka REG_SB
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REG_TP = REG_X4 // aka REG_G
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REG_T0 = REG_X5
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REG_T1 = REG_X6
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REG_T2 = REG_X7
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REG_S0 = REG_X8
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REG_S1 = REG_X9
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REG_A0 = REG_X10
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REG_A1 = REG_X11
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REG_A2 = REG_X12
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REG_A3 = REG_X13
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REG_A4 = REG_X14
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REG_A5 = REG_X15
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REG_A6 = REG_X16
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REG_A7 = REG_X17
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REG_S2 = REG_X18
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REG_S3 = REG_X19
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REG_S4 = REG_X20
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REG_S5 = REG_X21
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REG_S6 = REG_X22
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REG_S7 = REG_X23
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REG_S8 = REG_X24
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REG_S9 = REG_X25
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REG_S10 = REG_X26
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REG_S11 = REG_X27
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REG_T3 = REG_X28
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REG_T4 = REG_X29
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REG_T5 = REG_X30
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REG_T6 = REG_X31
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// Go runtime register names.
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REG_G = REG_TP // G pointer.
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REG_CTXT = REG_S4 // Context for closures.
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REG_TMP = REG_T6 // Reserved for assembler use.
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// ABI names for floating point registers.
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REG_FT0 = REG_F0
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REG_FT1 = REG_F1
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REG_FT2 = REG_F2
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REG_FT3 = REG_F3
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REG_FT4 = REG_F4
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REG_FT5 = REG_F5
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REG_FT6 = REG_F6
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REG_FT7 = REG_F7
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REG_FS0 = REG_F8
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REG_FS1 = REG_F9
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REG_FA0 = REG_F10
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REG_FA1 = REG_F11
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REG_FA2 = REG_F12
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REG_FA3 = REG_F13
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REG_FA4 = REG_F14
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REG_FA5 = REG_F15
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REG_FA6 = REG_F16
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REG_FA7 = REG_F17
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REG_FS2 = REG_F18
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REG_FS3 = REG_F19
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REG_FS4 = REG_F20
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REG_FS5 = REG_F21
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REG_FS6 = REG_F22
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REG_FS7 = REG_F23
|
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REG_FS8 = REG_F24
|
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REG_FS9 = REG_F25
|
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REG_FS10 = REG_F26
|
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REG_FS11 = REG_F27
|
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REG_FT8 = REG_F28
|
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REG_FT9 = REG_F29
|
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REG_FT10 = REG_F30
|
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REG_FT11 = REG_F31
|
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|
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// Names generated by the SSA compiler.
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REGSP = REG_SP
|
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REGG = REG_G
|
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)
|
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// Prog.Mark flags.
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const (
|
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// NEED_PCREL_ITYPE_RELOC is set on AUIPC instructions to indicate that
|
||||
// it is the first instruction in an AUIPC + I-type pair that needs a
|
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// R_RISCV_PCREL_ITYPE relocation.
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NEED_PCREL_ITYPE_RELOC = 1 << 0
|
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|
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// NEED_PCREL_STYPE_RELOC is set on AUIPC instructions to indicate that
|
||||
// it is the first instruction in an AUIPC + S-type pair that needs a
|
||||
// R_RISCV_PCREL_STYPE relocation.
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NEED_PCREL_STYPE_RELOC = 1 << 1
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)
|
||||
|
||||
// RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files
|
||||
// from:
|
||||
//
|
||||
// https://github.com/riscv/riscv-opcodes
|
||||
//
|
||||
// As well as some pseudo-mnemonics (e.g. MOV) used only in the assembler.
|
||||
//
|
||||
// See also "The RISC-V Instruction Set Manual" at:
|
||||
//
|
||||
// https://riscv.org/specifications/
|
||||
//
|
||||
// If you modify this table, you MUST run 'go generate' to regenerate anames.go!
|
||||
const (
|
||||
// Unprivileged ISA (Document Version 20190608-Base-Ratified)
|
||||
|
||||
// 2.4: Integer Computational Instructions
|
||||
ASLLIRV32 = obj.ABaseRISCV + obj.A_ARCHSPECIFIC + iota
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||||
ASRLIRV32
|
||||
ASRAIRV32
|
||||
|
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// 2.5: Control Transfer Instructions
|
||||
AJAL
|
||||
AJALR
|
||||
ABEQ
|
||||
ABNE
|
||||
ABLT
|
||||
ABLTU
|
||||
ABGE
|
||||
ABGEU
|
||||
|
||||
// 2.7: Memory Ordering Instructions
|
||||
AFENCE
|
||||
AFENCEI
|
||||
AFENCETSO
|
||||
|
||||
// 5.2: Integer Computational Instructions
|
||||
AADDI
|
||||
ASLTI
|
||||
ASLTIU
|
||||
AANDI
|
||||
AORI
|
||||
AXORI
|
||||
ASLLI
|
||||
ASRLI
|
||||
ASRAI
|
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ALUI
|
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AAUIPC
|
||||
AADD
|
||||
ASLT
|
||||
ASLTU
|
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AAND
|
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AOR
|
||||
AXOR
|
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ASLL
|
||||
ASRL
|
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ASUB
|
||||
ASRA
|
||||
AADDIW
|
||||
ASLLIW
|
||||
ASRLIW
|
||||
ASRAIW
|
||||
AADDW
|
||||
ASLLW
|
||||
ASRLW
|
||||
ASUBW
|
||||
ASRAW
|
||||
|
||||
// 5.3: Load and Store Instructions
|
||||
ALD
|
||||
ALW
|
||||
ALWU
|
||||
ALH
|
||||
ALHU
|
||||
ALB
|
||||
ALBU
|
||||
ASD
|
||||
ASW
|
||||
ASH
|
||||
ASB
|
||||
|
||||
// 7.1: Multiplication Operations
|
||||
AMUL
|
||||
AMULH
|
||||
AMULHU
|
||||
AMULHSU
|
||||
AMULW
|
||||
ADIV
|
||||
ADIVU
|
||||
AREM
|
||||
AREMU
|
||||
ADIVW
|
||||
ADIVUW
|
||||
AREMW
|
||||
AREMUW
|
||||
|
||||
// 8.2: Load-Reserved/Store-Conditional Instructions
|
||||
ALRD
|
||||
ASCD
|
||||
ALRW
|
||||
ASCW
|
||||
|
||||
// 8.3: Atomic Memory Operations
|
||||
AAMOSWAPD
|
||||
AAMOADDD
|
||||
AAMOANDD
|
||||
AAMOORD
|
||||
AAMOXORD
|
||||
AAMOMAXD
|
||||
AAMOMAXUD
|
||||
AAMOMIND
|
||||
AAMOMINUD
|
||||
AAMOSWAPW
|
||||
AAMOADDW
|
||||
AAMOANDW
|
||||
AAMOORW
|
||||
AAMOXORW
|
||||
AAMOMAXW
|
||||
AAMOMAXUW
|
||||
AAMOMINW
|
||||
AAMOMINUW
|
||||
|
||||
// 10.1: Base Counters and Timers
|
||||
ARDCYCLE
|
||||
ARDCYCLEH
|
||||
ARDTIME
|
||||
ARDTIMEH
|
||||
ARDINSTRET
|
||||
ARDINSTRETH
|
||||
|
||||
// 11.2: Floating-Point Control and Status Register
|
||||
AFRCSR
|
||||
AFSCSR
|
||||
AFRRM
|
||||
AFSRM
|
||||
AFRFLAGS
|
||||
AFSFLAGS
|
||||
AFSRMI
|
||||
AFSFLAGSI
|
||||
|
||||
// 11.5: Single-Precision Load and Store Instructions
|
||||
AFLW
|
||||
AFSW
|
||||
|
||||
// 11.6: Single-Precision Floating-Point Computational Instructions
|
||||
AFADDS
|
||||
AFSUBS
|
||||
AFMULS
|
||||
AFDIVS
|
||||
AFMINS
|
||||
AFMAXS
|
||||
AFSQRTS
|
||||
AFMADDS
|
||||
AFMSUBS
|
||||
AFNMADDS
|
||||
AFNMSUBS
|
||||
|
||||
// 11.7: Single-Precision Floating-Point Conversion and Move Instructions
|
||||
AFCVTWS
|
||||
AFCVTLS
|
||||
AFCVTSW
|
||||
AFCVTSL
|
||||
AFCVTWUS
|
||||
AFCVTLUS
|
||||
AFCVTSWU
|
||||
AFCVTSLU
|
||||
AFSGNJS
|
||||
AFSGNJNS
|
||||
AFSGNJXS
|
||||
AFMVSX
|
||||
AFMVXS
|
||||
AFMVWX
|
||||
AFMVXW
|
||||
|
||||
// 11.8: Single-Precision Floating-Point Compare Instructions
|
||||
AFEQS
|
||||
AFLTS
|
||||
AFLES
|
||||
|
||||
// 11.9: Single-Precision Floating-Point Classify Instruction
|
||||
AFCLASSS
|
||||
|
||||
// 12.3: Double-Precision Load and Store Instructions
|
||||
AFLD
|
||||
AFSD
|
||||
|
||||
// 12.4: Double-Precision Floating-Point Computational Instructions
|
||||
AFADDD
|
||||
AFSUBD
|
||||
AFMULD
|
||||
AFDIVD
|
||||
AFMIND
|
||||
AFMAXD
|
||||
AFSQRTD
|
||||
AFMADDD
|
||||
AFMSUBD
|
||||
AFNMADDD
|
||||
AFNMSUBD
|
||||
|
||||
// 12.5: Double-Precision Floating-Point Conversion and Move Instructions
|
||||
AFCVTWD
|
||||
AFCVTLD
|
||||
AFCVTDW
|
||||
AFCVTDL
|
||||
AFCVTWUD
|
||||
AFCVTLUD
|
||||
AFCVTDWU
|
||||
AFCVTDLU
|
||||
AFCVTSD
|
||||
AFCVTDS
|
||||
AFSGNJD
|
||||
AFSGNJND
|
||||
AFSGNJXD
|
||||
AFMVXD
|
||||
AFMVDX
|
||||
|
||||
// 12.6: Double-Precision Floating-Point Compare Instructions
|
||||
AFEQD
|
||||
AFLTD
|
||||
AFLED
|
||||
|
||||
// 12.7: Double-Precision Floating-Point Classify Instruction
|
||||
AFCLASSD
|
||||
|
||||
// 13.1 Quad-Precision Load and Store Instructions
|
||||
AFLQ
|
||||
AFSQ
|
||||
|
||||
// 13.2: Quad-Precision Computational Instructions
|
||||
AFADDQ
|
||||
AFSUBQ
|
||||
AFMULQ
|
||||
AFDIVQ
|
||||
AFMINQ
|
||||
AFMAXQ
|
||||
AFSQRTQ
|
||||
AFMADDQ
|
||||
AFMSUBQ
|
||||
AFNMADDQ
|
||||
AFNMSUBQ
|
||||
|
||||
// 13.3 Quad-Precision Convert and Move Instructions
|
||||
AFCVTWQ
|
||||
AFCVTLQ
|
||||
AFCVTSQ
|
||||
AFCVTDQ
|
||||
AFCVTQW
|
||||
AFCVTQL
|
||||
AFCVTQS
|
||||
AFCVTQD
|
||||
AFCVTWUQ
|
||||
AFCVTLUQ
|
||||
AFCVTQWU
|
||||
AFCVTQLU
|
||||
AFSGNJQ
|
||||
AFSGNJNQ
|
||||
AFSGNJXQ
|
||||
AFMVXQ
|
||||
AFMVQX
|
||||
|
||||
// 13.4 Quad-Precision Floating-Point Compare Instructions
|
||||
AFEQQ
|
||||
AFLEQ
|
||||
AFLTQ
|
||||
|
||||
// 13.5 Quad-Precision Floating-Point Classify Instruction
|
||||
AFCLASSQ
|
||||
|
||||
// Privileged ISA (Version 20190608-Priv-MSU-Ratified)
|
||||
|
||||
// 3.1.9: Instructions to Access CSRs
|
||||
ACSRRW
|
||||
ACSRRS
|
||||
ACSRRC
|
||||
ACSRRWI
|
||||
ACSRRSI
|
||||
ACSRRCI
|
||||
|
||||
// 3.2.1: Environment Call and Breakpoint
|
||||
AECALL
|
||||
ASCALL
|
||||
AEBREAK
|
||||
ASBREAK
|
||||
|
||||
// 3.2.2: Trap-Return Instructions
|
||||
AMRET
|
||||
ASRET
|
||||
AURET
|
||||
ADRET
|
||||
|
||||
// 3.2.3: Wait for Interrupt
|
||||
AWFI
|
||||
|
||||
// 4.2.1: Supervisor Memory-Management Fence Instruction
|
||||
ASFENCEVMA
|
||||
|
||||
// Hypervisor Memory-Management Instructions
|
||||
AHFENCEGVMA
|
||||
AHFENCEVVMA
|
||||
|
||||
// The escape hatch. Inserts a single 32-bit word.
|
||||
AWORD
|
||||
|
||||
// Pseudo-instructions. These get translated by the assembler into other
|
||||
// instructions, based on their operands.
|
||||
AFNEGD
|
||||
AFNEGS
|
||||
AFNED
|
||||
AFNES
|
||||
AMOV
|
||||
AMOVB
|
||||
AMOVBU
|
||||
AMOVF
|
||||
AMOVD
|
||||
AMOVH
|
||||
AMOVHU
|
||||
AMOVW
|
||||
AMOVWU
|
||||
ASEQZ
|
||||
ASNEZ
|
||||
)
|
||||
|
||||
// All unary instructions which write to their arguments (as opposed to reading
|
||||
// from them) go here. The assembly parser uses this information to populate
|
||||
// its AST in a semantically reasonable way.
|
||||
//
|
||||
// Any instructions not listed here are assumed to either be non-unary or to read
|
||||
// from its argument.
|
||||
var unaryDst = map[obj.As]bool{
|
||||
ARDCYCLE: true,
|
||||
ARDCYCLEH: true,
|
||||
ARDTIME: true,
|
||||
ARDTIMEH: true,
|
||||
ARDINSTRET: true,
|
||||
ARDINSTRETH: true,
|
||||
}
|
||||
|
||||
// Instruction encoding masks.
|
||||
const (
|
||||
// ITypeImmMask is a mask including only the immediate portion of
|
||||
// I-type instructions.
|
||||
ITypeImmMask = 0xfff00000
|
||||
|
||||
// STypeImmMask is a mask including only the immediate portion of
|
||||
// S-type instructions.
|
||||
STypeImmMask = 0xfe000f80
|
||||
|
||||
// UTypeImmMask is a mask including only the immediate portion of
|
||||
// U-type instructions.
|
||||
UTypeImmMask = 0xfffff000
|
||||
|
||||
// UJTypeImmMask is a mask including only the immediate portion of
|
||||
// UJ-type instructions.
|
||||
UJTypeImmMask = UTypeImmMask
|
||||
)
|
||||
459
src/cmd/internal/obj/riscv/inst.go
Normal file
459
src/cmd/internal/obj/riscv/inst.go
Normal file
@ -0,0 +1,459 @@
|
||||
// Code generated by parse_opcodes -go; DO NOT EDIT.
|
||||
|
||||
package riscv
|
||||
|
||||
import "cmd/internal/obj"
|
||||
|
||||
type inst struct {
|
||||
opcode uint32
|
||||
funct3 uint32
|
||||
rs2 uint32
|
||||
csr int64
|
||||
funct7 uint32
|
||||
}
|
||||
|
||||
func encode(a obj.As) *inst {
|
||||
switch a {
|
||||
case ABEQ:
|
||||
return &inst{0x63, 0x0, 0x0, 0, 0x0}
|
||||
case ABNE:
|
||||
return &inst{0x63, 0x1, 0x0, 0, 0x0}
|
||||
case ABLT:
|
||||
return &inst{0x63, 0x4, 0x0, 0, 0x0}
|
||||
case ABGE:
|
||||
return &inst{0x63, 0x5, 0x0, 0, 0x0}
|
||||
case ABLTU:
|
||||
return &inst{0x63, 0x6, 0x0, 0, 0x0}
|
||||
case ABGEU:
|
||||
return &inst{0x63, 0x7, 0x0, 0, 0x0}
|
||||
case AJALR:
|
||||
return &inst{0x67, 0x0, 0x0, 0, 0x0}
|
||||
case AJAL:
|
||||
return &inst{0x6f, 0x0, 0x0, 0, 0x0}
|
||||
case ALUI:
|
||||
return &inst{0x37, 0x0, 0x0, 0, 0x0}
|
||||
case AAUIPC:
|
||||
return &inst{0x17, 0x0, 0x0, 0, 0x0}
|
||||
case AADDI:
|
||||
return &inst{0x13, 0x0, 0x0, 0, 0x0}
|
||||
case ASLLI:
|
||||
return &inst{0x13, 0x1, 0x0, 0, 0x0}
|
||||
case ASLTI:
|
||||
return &inst{0x13, 0x2, 0x0, 0, 0x0}
|
||||
case ASLTIU:
|
||||
return &inst{0x13, 0x3, 0x0, 0, 0x0}
|
||||
case AXORI:
|
||||
return &inst{0x13, 0x4, 0x0, 0, 0x0}
|
||||
case ASRLI:
|
||||
return &inst{0x13, 0x5, 0x0, 0, 0x0}
|
||||
case ASRAI:
|
||||
return &inst{0x13, 0x5, 0x0, 1024, 0x20}
|
||||
case AORI:
|
||||
return &inst{0x13, 0x6, 0x0, 0, 0x0}
|
||||
case AANDI:
|
||||
return &inst{0x13, 0x7, 0x0, 0, 0x0}
|
||||
case AADD:
|
||||
return &inst{0x33, 0x0, 0x0, 0, 0x0}
|
||||
case ASUB:
|
||||
return &inst{0x33, 0x0, 0x0, 1024, 0x20}
|
||||
case ASLL:
|
||||
return &inst{0x33, 0x1, 0x0, 0, 0x0}
|
||||
case ASLT:
|
||||
return &inst{0x33, 0x2, 0x0, 0, 0x0}
|
||||
case ASLTU:
|
||||
return &inst{0x33, 0x3, 0x0, 0, 0x0}
|
||||
case AXOR:
|
||||
return &inst{0x33, 0x4, 0x0, 0, 0x0}
|
||||
case ASRL:
|
||||
return &inst{0x33, 0x5, 0x0, 0, 0x0}
|
||||
case ASRA:
|
||||
return &inst{0x33, 0x5, 0x0, 1024, 0x20}
|
||||
case AOR:
|
||||
return &inst{0x33, 0x6, 0x0, 0, 0x0}
|
||||
case AAND:
|
||||
return &inst{0x33, 0x7, 0x0, 0, 0x0}
|
||||
case AADDIW:
|
||||
return &inst{0x1b, 0x0, 0x0, 0, 0x0}
|
||||
case ASLLIW:
|
||||
return &inst{0x1b, 0x1, 0x0, 0, 0x0}
|
||||
case ASRLIW:
|
||||
return &inst{0x1b, 0x5, 0x0, 0, 0x0}
|
||||
case ASRAIW:
|
||||
return &inst{0x1b, 0x5, 0x0, 1024, 0x20}
|
||||
case AADDW:
|
||||
return &inst{0x3b, 0x0, 0x0, 0, 0x0}
|
||||
case ASUBW:
|
||||
return &inst{0x3b, 0x0, 0x0, 1024, 0x20}
|
||||
case ASLLW:
|
||||
return &inst{0x3b, 0x1, 0x0, 0, 0x0}
|
||||
case ASRLW:
|
||||
return &inst{0x3b, 0x5, 0x0, 0, 0x0}
|
||||
case ASRAW:
|
||||
return &inst{0x3b, 0x5, 0x0, 1024, 0x20}
|
||||
case ALB:
|
||||
return &inst{0x3, 0x0, 0x0, 0, 0x0}
|
||||
case ALH:
|
||||
return &inst{0x3, 0x1, 0x0, 0, 0x0}
|
||||
case ALW:
|
||||
return &inst{0x3, 0x2, 0x0, 0, 0x0}
|
||||
case ALD:
|
||||
return &inst{0x3, 0x3, 0x0, 0, 0x0}
|
||||
case ALBU:
|
||||
return &inst{0x3, 0x4, 0x0, 0, 0x0}
|
||||
case ALHU:
|
||||
return &inst{0x3, 0x5, 0x0, 0, 0x0}
|
||||
case ALWU:
|
||||
return &inst{0x3, 0x6, 0x0, 0, 0x0}
|
||||
case ASB:
|
||||
return &inst{0x23, 0x0, 0x0, 0, 0x0}
|
||||
case ASH:
|
||||
return &inst{0x23, 0x1, 0x0, 0, 0x0}
|
||||
case ASW:
|
||||
return &inst{0x23, 0x2, 0x0, 0, 0x0}
|
||||
case ASD:
|
||||
return &inst{0x23, 0x3, 0x0, 0, 0x0}
|
||||
case AFENCE:
|
||||
return &inst{0xf, 0x0, 0x0, 0, 0x0}
|
||||
case AFENCEI:
|
||||
return &inst{0xf, 0x1, 0x0, 0, 0x0}
|
||||
case AMUL:
|
||||
return &inst{0x33, 0x0, 0x0, 32, 0x1}
|
||||
case AMULH:
|
||||
return &inst{0x33, 0x1, 0x0, 32, 0x1}
|
||||
case AMULHSU:
|
||||
return &inst{0x33, 0x2, 0x0, 32, 0x1}
|
||||
case AMULHU:
|
||||
return &inst{0x33, 0x3, 0x0, 32, 0x1}
|
||||
case ADIV:
|
||||
return &inst{0x33, 0x4, 0x0, 32, 0x1}
|
||||
case ADIVU:
|
||||
return &inst{0x33, 0x5, 0x0, 32, 0x1}
|
||||
case AREM:
|
||||
return &inst{0x33, 0x6, 0x0, 32, 0x1}
|
||||
case AREMU:
|
||||
return &inst{0x33, 0x7, 0x0, 32, 0x1}
|
||||
case AMULW:
|
||||
return &inst{0x3b, 0x0, 0x0, 32, 0x1}
|
||||
case ADIVW:
|
||||
return &inst{0x3b, 0x4, 0x0, 32, 0x1}
|
||||
case ADIVUW:
|
||||
return &inst{0x3b, 0x5, 0x0, 32, 0x1}
|
||||
case AREMW:
|
||||
return &inst{0x3b, 0x6, 0x0, 32, 0x1}
|
||||
case AREMUW:
|
||||
return &inst{0x3b, 0x7, 0x0, 32, 0x1}
|
||||
case AAMOADDW:
|
||||
return &inst{0x2f, 0x2, 0x0, 0, 0x0}
|
||||
case AAMOXORW:
|
||||
return &inst{0x2f, 0x2, 0x0, 512, 0x10}
|
||||
case AAMOORW:
|
||||
return &inst{0x2f, 0x2, 0x0, 1024, 0x20}
|
||||
case AAMOANDW:
|
||||
return &inst{0x2f, 0x2, 0x0, 1536, 0x30}
|
||||
case AAMOMINW:
|
||||
return &inst{0x2f, 0x2, 0x0, -2048, 0x40}
|
||||
case AAMOMAXW:
|
||||
return &inst{0x2f, 0x2, 0x0, -1536, 0x50}
|
||||
case AAMOMINUW:
|
||||
return &inst{0x2f, 0x2, 0x0, -1024, 0x60}
|
||||
case AAMOMAXUW:
|
||||
return &inst{0x2f, 0x2, 0x0, -512, 0x70}
|
||||
case AAMOSWAPW:
|
||||
return &inst{0x2f, 0x2, 0x0, 128, 0x4}
|
||||
case ALRW:
|
||||
return &inst{0x2f, 0x2, 0x0, 256, 0x8}
|
||||
case ASCW:
|
||||
return &inst{0x2f, 0x2, 0x0, 384, 0xc}
|
||||
case AAMOADDD:
|
||||
return &inst{0x2f, 0x3, 0x0, 0, 0x0}
|
||||
case AAMOXORD:
|
||||
return &inst{0x2f, 0x3, 0x0, 512, 0x10}
|
||||
case AAMOORD:
|
||||
return &inst{0x2f, 0x3, 0x0, 1024, 0x20}
|
||||
case AAMOANDD:
|
||||
return &inst{0x2f, 0x3, 0x0, 1536, 0x30}
|
||||
case AAMOMIND:
|
||||
return &inst{0x2f, 0x3, 0x0, -2048, 0x40}
|
||||
case AAMOMAXD:
|
||||
return &inst{0x2f, 0x3, 0x0, -1536, 0x50}
|
||||
case AAMOMINUD:
|
||||
return &inst{0x2f, 0x3, 0x0, -1024, 0x60}
|
||||
case AAMOMAXUD:
|
||||
return &inst{0x2f, 0x3, 0x0, -512, 0x70}
|
||||
case AAMOSWAPD:
|
||||
return &inst{0x2f, 0x3, 0x0, 128, 0x4}
|
||||
case ALRD:
|
||||
return &inst{0x2f, 0x3, 0x0, 256, 0x8}
|
||||
case ASCD:
|
||||
return &inst{0x2f, 0x3, 0x0, 384, 0xc}
|
||||
case AECALL:
|
||||
return &inst{0x73, 0x0, 0x0, 0, 0x0}
|
||||
case AEBREAK:
|
||||
return &inst{0x73, 0x0, 0x1, 1, 0x0}
|
||||
case AURET:
|
||||
return &inst{0x73, 0x0, 0x2, 2, 0x0}
|
||||
case ASRET:
|
||||
return &inst{0x73, 0x0, 0x2, 258, 0x8}
|
||||
case AMRET:
|
||||
return &inst{0x73, 0x0, 0x2, 770, 0x18}
|
||||
case ADRET:
|
||||
return &inst{0x73, 0x0, 0x12, 1970, 0x3d}
|
||||
case ASFENCEVMA:
|
||||
return &inst{0x73, 0x0, 0x0, 288, 0x9}
|
||||
case AWFI:
|
||||
return &inst{0x73, 0x0, 0x5, 261, 0x8}
|
||||
case ACSRRW:
|
||||
return &inst{0x73, 0x1, 0x0, 0, 0x0}
|
||||
case ACSRRS:
|
||||
return &inst{0x73, 0x2, 0x0, 0, 0x0}
|
||||
case ACSRRC:
|
||||
return &inst{0x73, 0x3, 0x0, 0, 0x0}
|
||||
case ACSRRWI:
|
||||
return &inst{0x73, 0x5, 0x0, 0, 0x0}
|
||||
case ACSRRSI:
|
||||
return &inst{0x73, 0x6, 0x0, 0, 0x0}
|
||||
case ACSRRCI:
|
||||
return &inst{0x73, 0x7, 0x0, 0, 0x0}
|
||||
case AHFENCEVVMA:
|
||||
return &inst{0x73, 0x0, 0x0, 544, 0x11}
|
||||
case AHFENCEGVMA:
|
||||
return &inst{0x73, 0x0, 0x0, 1568, 0x31}
|
||||
case AFADDS:
|
||||
return &inst{0x53, 0x0, 0x0, 0, 0x0}
|
||||
case AFSUBS:
|
||||
return &inst{0x53, 0x0, 0x0, 128, 0x4}
|
||||
case AFMULS:
|
||||
return &inst{0x53, 0x0, 0x0, 256, 0x8}
|
||||
case AFDIVS:
|
||||
return &inst{0x53, 0x0, 0x0, 384, 0xc}
|
||||
case AFSGNJS:
|
||||
return &inst{0x53, 0x0, 0x0, 512, 0x10}
|
||||
case AFSGNJNS:
|
||||
return &inst{0x53, 0x1, 0x0, 512, 0x10}
|
||||
case AFSGNJXS:
|
||||
return &inst{0x53, 0x2, 0x0, 512, 0x10}
|
||||
case AFMINS:
|
||||
return &inst{0x53, 0x0, 0x0, 640, 0x14}
|
||||
case AFMAXS:
|
||||
return &inst{0x53, 0x1, 0x0, 640, 0x14}
|
||||
case AFSQRTS:
|
||||
return &inst{0x53, 0x0, 0x0, 1408, 0x2c}
|
||||
case AFADDD:
|
||||
return &inst{0x53, 0x0, 0x0, 32, 0x1}
|
||||
case AFSUBD:
|
||||
return &inst{0x53, 0x0, 0x0, 160, 0x5}
|
||||
case AFMULD:
|
||||
return &inst{0x53, 0x0, 0x0, 288, 0x9}
|
||||
case AFDIVD:
|
||||
return &inst{0x53, 0x0, 0x0, 416, 0xd}
|
||||
case AFSGNJD:
|
||||
return &inst{0x53, 0x0, 0x0, 544, 0x11}
|
||||
case AFSGNJND:
|
||||
return &inst{0x53, 0x1, 0x0, 544, 0x11}
|
||||
case AFSGNJXD:
|
||||
return &inst{0x53, 0x2, 0x0, 544, 0x11}
|
||||
case AFMIND:
|
||||
return &inst{0x53, 0x0, 0x0, 672, 0x15}
|
||||
case AFMAXD:
|
||||
return &inst{0x53, 0x1, 0x0, 672, 0x15}
|
||||
case AFCVTSD:
|
||||
return &inst{0x53, 0x0, 0x1, 1025, 0x20}
|
||||
case AFCVTDS:
|
||||
return &inst{0x53, 0x0, 0x0, 1056, 0x21}
|
||||
case AFSQRTD:
|
||||
return &inst{0x53, 0x0, 0x0, 1440, 0x2d}
|
||||
case AFADDQ:
|
||||
return &inst{0x53, 0x0, 0x0, 96, 0x3}
|
||||
case AFSUBQ:
|
||||
return &inst{0x53, 0x0, 0x0, 224, 0x7}
|
||||
case AFMULQ:
|
||||
return &inst{0x53, 0x0, 0x0, 352, 0xb}
|
||||
case AFDIVQ:
|
||||
return &inst{0x53, 0x0, 0x0, 480, 0xf}
|
||||
case AFSGNJQ:
|
||||
return &inst{0x53, 0x0, 0x0, 608, 0x13}
|
||||
case AFSGNJNQ:
|
||||
return &inst{0x53, 0x1, 0x0, 608, 0x13}
|
||||
case AFSGNJXQ:
|
||||
return &inst{0x53, 0x2, 0x0, 608, 0x13}
|
||||
case AFMINQ:
|
||||
return &inst{0x53, 0x0, 0x0, 736, 0x17}
|
||||
case AFMAXQ:
|
||||
return &inst{0x53, 0x1, 0x0, 736, 0x17}
|
||||
case AFCVTSQ:
|
||||
return &inst{0x53, 0x0, 0x3, 1027, 0x20}
|
||||
case AFCVTQS:
|
||||
return &inst{0x53, 0x0, 0x0, 1120, 0x23}
|
||||
case AFCVTDQ:
|
||||
return &inst{0x53, 0x0, 0x3, 1059, 0x21}
|
||||
case AFCVTQD:
|
||||
return &inst{0x53, 0x0, 0x1, 1121, 0x23}
|
||||
case AFSQRTQ:
|
||||
return &inst{0x53, 0x0, 0x0, 1504, 0x2f}
|
||||
case AFLES:
|
||||
return &inst{0x53, 0x0, 0x0, -1536, 0x50}
|
||||
case AFLTS:
|
||||
return &inst{0x53, 0x1, 0x0, -1536, 0x50}
|
||||
case AFEQS:
|
||||
return &inst{0x53, 0x2, 0x0, -1536, 0x50}
|
||||
case AFLED:
|
||||
return &inst{0x53, 0x0, 0x0, -1504, 0x51}
|
||||
case AFLTD:
|
||||
return &inst{0x53, 0x1, 0x0, -1504, 0x51}
|
||||
case AFEQD:
|
||||
return &inst{0x53, 0x2, 0x0, -1504, 0x51}
|
||||
case AFLEQ:
|
||||
return &inst{0x53, 0x0, 0x0, -1440, 0x53}
|
||||
case AFLTQ:
|
||||
return &inst{0x53, 0x1, 0x0, -1440, 0x53}
|
||||
case AFEQQ:
|
||||
return &inst{0x53, 0x2, 0x0, -1440, 0x53}
|
||||
case AFCVTWS:
|
||||
return &inst{0x53, 0x0, 0x0, -1024, 0x60}
|
||||
case AFCVTWUS:
|
||||
return &inst{0x53, 0x0, 0x1, -1023, 0x60}
|
||||
case AFCVTLS:
|
||||
return &inst{0x53, 0x0, 0x2, -1022, 0x60}
|
||||
case AFCVTLUS:
|
||||
return &inst{0x53, 0x0, 0x3, -1021, 0x60}
|
||||
case AFMVXW:
|
||||
return &inst{0x53, 0x0, 0x0, -512, 0x70}
|
||||
case AFCLASSS:
|
||||
return &inst{0x53, 0x1, 0x0, -512, 0x70}
|
||||
case AFCVTWD:
|
||||
return &inst{0x53, 0x0, 0x0, -992, 0x61}
|
||||
case AFCVTWUD:
|
||||
return &inst{0x53, 0x0, 0x1, -991, 0x61}
|
||||
case AFCVTLD:
|
||||
return &inst{0x53, 0x0, 0x2, -990, 0x61}
|
||||
case AFCVTLUD:
|
||||
return &inst{0x53, 0x0, 0x3, -989, 0x61}
|
||||
case AFMVXD:
|
||||
return &inst{0x53, 0x0, 0x0, -480, 0x71}
|
||||
case AFCLASSD:
|
||||
return &inst{0x53, 0x1, 0x0, -480, 0x71}
|
||||
case AFCVTWQ:
|
||||
return &inst{0x53, 0x0, 0x0, -928, 0x63}
|
||||
case AFCVTWUQ:
|
||||
return &inst{0x53, 0x0, 0x1, -927, 0x63}
|
||||
case AFCVTLQ:
|
||||
return &inst{0x53, 0x0, 0x2, -926, 0x63}
|
||||
case AFCVTLUQ:
|
||||
return &inst{0x53, 0x0, 0x3, -925, 0x63}
|
||||
case AFMVXQ:
|
||||
return &inst{0x53, 0x0, 0x0, -416, 0x73}
|
||||
case AFCLASSQ:
|
||||
return &inst{0x53, 0x1, 0x0, -416, 0x73}
|
||||
case AFCVTSW:
|
||||
return &inst{0x53, 0x0, 0x0, -768, 0x68}
|
||||
case AFCVTSWU:
|
||||
return &inst{0x53, 0x0, 0x1, -767, 0x68}
|
||||
case AFCVTSL:
|
||||
return &inst{0x53, 0x0, 0x2, -766, 0x68}
|
||||
case AFCVTSLU:
|
||||
return &inst{0x53, 0x0, 0x3, -765, 0x68}
|
||||
case AFMVWX:
|
||||
return &inst{0x53, 0x0, 0x0, -256, 0x78}
|
||||
case AFCVTDW:
|
||||
return &inst{0x53, 0x0, 0x0, -736, 0x69}
|
||||
case AFCVTDWU:
|
||||
return &inst{0x53, 0x0, 0x1, -735, 0x69}
|
||||
case AFCVTDL:
|
||||
return &inst{0x53, 0x0, 0x2, -734, 0x69}
|
||||
case AFCVTDLU:
|
||||
return &inst{0x53, 0x0, 0x3, -733, 0x69}
|
||||
case AFMVDX:
|
||||
return &inst{0x53, 0x0, 0x0, -224, 0x79}
|
||||
case AFCVTQW:
|
||||
return &inst{0x53, 0x0, 0x0, -672, 0x6b}
|
||||
case AFCVTQWU:
|
||||
return &inst{0x53, 0x0, 0x1, -671, 0x6b}
|
||||
case AFCVTQL:
|
||||
return &inst{0x53, 0x0, 0x2, -670, 0x6b}
|
||||
case AFCVTQLU:
|
||||
return &inst{0x53, 0x0, 0x3, -669, 0x6b}
|
||||
case AFMVQX:
|
||||
return &inst{0x53, 0x0, 0x0, -160, 0x7b}
|
||||
case AFLW:
|
||||
return &inst{0x7, 0x2, 0x0, 0, 0x0}
|
||||
case AFLD:
|
||||
return &inst{0x7, 0x3, 0x0, 0, 0x0}
|
||||
case AFLQ:
|
||||
return &inst{0x7, 0x4, 0x0, 0, 0x0}
|
||||
case AFSW:
|
||||
return &inst{0x27, 0x2, 0x0, 0, 0x0}
|
||||
case AFSD:
|
||||
return &inst{0x27, 0x3, 0x0, 0, 0x0}
|
||||
case AFSQ:
|
||||
return &inst{0x27, 0x4, 0x0, 0, 0x0}
|
||||
case AFMADDS:
|
||||
return &inst{0x43, 0x0, 0x0, 0, 0x0}
|
||||
case AFMSUBS:
|
||||
return &inst{0x47, 0x0, 0x0, 0, 0x0}
|
||||
case AFNMSUBS:
|
||||
return &inst{0x4b, 0x0, 0x0, 0, 0x0}
|
||||
case AFNMADDS:
|
||||
return &inst{0x4f, 0x0, 0x0, 0, 0x0}
|
||||
case AFMADDD:
|
||||
return &inst{0x43, 0x0, 0x0, 32, 0x1}
|
||||
case AFMSUBD:
|
||||
return &inst{0x47, 0x0, 0x0, 32, 0x1}
|
||||
case AFNMSUBD:
|
||||
return &inst{0x4b, 0x0, 0x0, 32, 0x1}
|
||||
case AFNMADDD:
|
||||
return &inst{0x4f, 0x0, 0x0, 32, 0x1}
|
||||
case AFMADDQ:
|
||||
return &inst{0x43, 0x0, 0x0, 96, 0x3}
|
||||
case AFMSUBQ:
|
||||
return &inst{0x47, 0x0, 0x0, 96, 0x3}
|
||||
case AFNMSUBQ:
|
||||
return &inst{0x4b, 0x0, 0x0, 96, 0x3}
|
||||
case AFNMADDQ:
|
||||
return &inst{0x4f, 0x0, 0x0, 96, 0x3}
|
||||
case ASLLIRV32:
|
||||
return &inst{0x13, 0x1, 0x0, 0, 0x0}
|
||||
case ASRLIRV32:
|
||||
return &inst{0x13, 0x5, 0x0, 0, 0x0}
|
||||
case ASRAIRV32:
|
||||
return &inst{0x13, 0x5, 0x0, 1024, 0x20}
|
||||
case AFRFLAGS:
|
||||
return &inst{0x73, 0x2, 0x1, 1, 0x0}
|
||||
case AFSFLAGS:
|
||||
return &inst{0x73, 0x1, 0x1, 1, 0x0}
|
||||
case AFSFLAGSI:
|
||||
return &inst{0x73, 0x5, 0x1, 1, 0x0}
|
||||
case AFRRM:
|
||||
return &inst{0x73, 0x2, 0x2, 2, 0x0}
|
||||
case AFSRM:
|
||||
return &inst{0x73, 0x1, 0x2, 2, 0x0}
|
||||
case AFSRMI:
|
||||
return &inst{0x73, 0x5, 0x2, 2, 0x0}
|
||||
case AFSCSR:
|
||||
return &inst{0x73, 0x1, 0x3, 3, 0x0}
|
||||
case AFRCSR:
|
||||
return &inst{0x73, 0x2, 0x3, 3, 0x0}
|
||||
case ARDCYCLE:
|
||||
return &inst{0x73, 0x2, 0x0, -1024, 0x60}
|
||||
case ARDTIME:
|
||||
return &inst{0x73, 0x2, 0x1, -1023, 0x60}
|
||||
case ARDINSTRET:
|
||||
return &inst{0x73, 0x2, 0x2, -1022, 0x60}
|
||||
case ARDCYCLEH:
|
||||
return &inst{0x73, 0x2, 0x0, -896, 0x64}
|
||||
case ARDTIMEH:
|
||||
return &inst{0x73, 0x2, 0x1, -895, 0x64}
|
||||
case ARDINSTRETH:
|
||||
return &inst{0x73, 0x2, 0x2, -894, 0x64}
|
||||
case ASCALL:
|
||||
return &inst{0x73, 0x0, 0x0, 0, 0x0}
|
||||
case ASBREAK:
|
||||
return &inst{0x73, 0x0, 0x1, 1, 0x0}
|
||||
case AFMVXS:
|
||||
return &inst{0x53, 0x0, 0x0, -512, 0x70}
|
||||
case AFMVSX:
|
||||
return &inst{0x53, 0x0, 0x0, -256, 0x78}
|
||||
case AFENCETSO:
|
||||
return &inst{0xf, 0x0, 0x13, -1997, 0x41}
|
||||
}
|
||||
return nil
|
||||
}
|
||||
@ -457,6 +457,7 @@ const (
|
||||
RBaseARM64 = 8 * 1024 // range [8k, 13k)
|
||||
RBaseMIPS = 13 * 1024 // range [13k, 14k)
|
||||
RBaseS390X = 14 * 1024 // range [14k, 15k)
|
||||
RBaseRISCV = 15 * 1024 // range [15k, 16k)
|
||||
RBaseWasm = 16 * 1024
|
||||
)
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user