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[dev.ssa] cmd/compile/internal/ssa: remove cgen pass
Code generation is now done in genssa. Also remove the asm field in opInfo. It's no longer used. Change-Id: I65fffac267e138fd424b2ef8aa7ed79f0ebb63d5 Reviewed-on: https://go-review.googlesource.com/10539 Reviewed-by: Keith Randall <khr@golang.org>
This commit is contained in:
Michael Matloob
Keith Randall
parent
067e8dfd82
commit
7bdecbf840
@ -25,7 +25,6 @@ Values
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Opcodes
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- Rename ops to prevent cross-arch conflicts. MOVQ -> MOVQamd64 (or
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MOVQ6?). Other option: build opcode table in Config instead of globally.
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- Remove asm string from opinfo, no longer needed.
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- It's annoying to list the opcode both in the opcode list and an
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opInfo map entry. Specify it one place and use go:generate to
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produce both?
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@ -1,135 +0,0 @@
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// Copyright 2015 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package ssa
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import (
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"bytes"
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"fmt"
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"os"
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)
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// cgen selects machine instructions for the function.
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// This pass generates assembly output for now, but should
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// TODO(khr): generate binary output (via liblink?) instead of text.
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func cgen(f *Func) {
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fmt.Printf("TEXT %s(SB),0,$0\n", f.Name) // TODO: frame size / arg size
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// TODO: prolog, allocate stack frame
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for idx, b := range f.Blocks {
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fmt.Printf("%d:\n", b.ID)
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for _, v := range b.Values {
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var buf bytes.Buffer
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asm := opcodeTable[v.Op].asm
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buf.WriteString(" ")
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for i := 0; i < len(asm); i++ {
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switch asm[i] {
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default:
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buf.WriteByte(asm[i])
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case '\t':
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buf.WriteByte(' ')
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for buf.Len()%8 != 0 {
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buf.WriteByte(' ')
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}
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case '%':
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i++
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switch asm[i] {
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case '%':
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buf.WriteByte('%')
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case 'I':
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i++
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n := asm[i] - '0'
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if f.RegAlloc[v.Args[n].ID] != nil {
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buf.WriteString(f.RegAlloc[v.Args[n].ID].Name())
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} else {
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fmt.Fprintf(&buf, "v%d", v.Args[n].ID)
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}
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case 'O':
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i++
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n := asm[i] - '0'
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if n != 0 {
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panic("can only handle 1 output for now")
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}
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if f.RegAlloc[v.ID] != nil {
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buf.WriteString(f.RegAlloc[v.ID].Name())
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} else {
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fmt.Fprintf(&buf, "v%d", v.ID)
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}
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case 'A':
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fmt.Fprint(&buf, v.Aux)
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}
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}
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}
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for buf.Len() < 40 {
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buf.WriteByte(' ')
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}
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buf.WriteString("; ")
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buf.WriteString(v.LongString())
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buf.WriteByte('\n')
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os.Stdout.Write(buf.Bytes())
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}
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// find next block in layout sequence
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var next *Block
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if idx < len(f.Blocks)-1 {
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next = f.Blocks[idx+1]
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}
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// emit end of block code
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// TODO: this is machine specific
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switch b.Kind {
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case BlockPlain:
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if b.Succs[0] != next {
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fmt.Printf("\tJMP\t%d\n", b.Succs[0].ID)
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}
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case BlockExit:
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// TODO: run defers (if any)
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// TODO: deallocate frame
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fmt.Println("\tRET")
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case BlockCall:
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// nothing to emit - call instruction already happened
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case BlockEQ:
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if b.Succs[0] == next {
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fmt.Printf("\tJNE\t%d\n", b.Succs[1].ID)
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} else if b.Succs[1] == next {
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fmt.Printf("\tJEQ\t%d\n", b.Succs[0].ID)
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} else {
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fmt.Printf("\tJEQ\t%d\n", b.Succs[0].ID)
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fmt.Printf("\tJMP\t%d\n", b.Succs[1].ID)
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}
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case BlockNE:
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if b.Succs[0] == next {
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fmt.Printf("\tJEQ\t%d\n", b.Succs[1].ID)
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} else if b.Succs[1] == next {
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fmt.Printf("\tJNE\t%d\n", b.Succs[0].ID)
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} else {
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fmt.Printf("\tJNE\t%d\n", b.Succs[0].ID)
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fmt.Printf("\tJMP\t%d\n", b.Succs[1].ID)
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}
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case BlockLT:
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if b.Succs[0] == next {
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fmt.Printf("\tJGE\t%d\n", b.Succs[1].ID)
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} else if b.Succs[1] == next {
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fmt.Printf("\tJLT\t%d\n", b.Succs[0].ID)
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} else {
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fmt.Printf("\tJLT\t%d\n", b.Succs[0].ID)
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fmt.Printf("\tJMP\t%d\n", b.Succs[1].ID)
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}
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case BlockULT:
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if b.Succs[0] == next {
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fmt.Printf("\tJAE\t%d\n", b.Succs[1].ID)
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} else if b.Succs[1] == next {
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fmt.Printf("\tJB\t%d\n", b.Succs[0].ID)
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} else {
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fmt.Printf("\tJB\t%d\n", b.Succs[0].ID)
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fmt.Printf("\tJMP\t%d\n", b.Succs[1].ID)
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}
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default:
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fmt.Printf("\t%s ->", b.Kind.String())
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for _, s := range b.Succs {
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fmt.Printf(" %d", s.ID)
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}
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fmt.Printf("\n")
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}
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}
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}
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@ -65,7 +65,6 @@ var passes = [...]pass{
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{"schedule", schedule}, // schedule values
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{"regalloc", regalloc},
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{"stackalloc", stackalloc},
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{"cgen", cgen},
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}
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// Double-check phase ordering constraints.
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@ -85,8 +84,6 @@ var passOrder = [...]constraint{
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{"schedule", "regalloc"},
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// stack allocation requires register allocation
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{"regalloc", "stackalloc"},
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// code generation requires stack allocation
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{"stackalloc", "cgen"},
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}
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func init() {
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@ -118,12 +118,6 @@ func (g GlobalOffset) String() string {
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type opInfo struct {
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flags int32
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// assembly template
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// %In: location of input n
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// %On: location of output n
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// %A: print aux with fmt.Print
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asm string
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// returns a reg constraint for the instruction. [0] gives a reg constraint
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// for each input, [1] gives a reg constraint for each output. (Values have
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// exactly one output for now)
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@ -123,39 +123,39 @@ var (
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// Opcodes that appear in an output amd64 program
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var amd64Table = map[Op]opInfo{
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OpADDQ: {flags: OpFlagCommutative, asm: "ADDQ\t%I0,%I1,%O0", reg: gp21}, // TODO: overwrite
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OpADDQconst: {asm: "ADDQ\t$%A,%I0,%O0", reg: gp11}, // aux = int64 constant to add
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OpSUBQ: {asm: "SUBQ\t%I0,%I1,%O0", reg: gp21},
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OpSUBQconst: {asm: "SUBQ\t$%A,%I0,%O0", reg: gp11},
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OpMULQ: {asm: "MULQ\t%I0,%I1,%O0", reg: gp21},
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OpMULQconst: {asm: "IMULQ\t$%A,%I0,%O0", reg: gp11},
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OpSHLQ: {asm: "SHLQ\t%I0,%I1,%O0", reg: gp21},
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OpSHLQconst: {asm: "SHLQ\t$%A,%I0,%O0", reg: gp11},
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OpADDQ: {flags: OpFlagCommutative, reg: gp21}, // TODO: overwrite
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OpADDQconst: {reg: gp11}, // aux = int64 constant to add
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OpSUBQ: {reg: gp21},
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OpSUBQconst: {reg: gp11},
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OpMULQ: {reg: gp21},
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OpMULQconst: {reg: gp11},
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OpSHLQ: {reg: gp21},
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OpSHLQconst: {reg: gp11},
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OpCMPQ: {asm: "CMPQ\t%I0,%I1", reg: gp2_flags}, // compute arg[0]-arg[1] and produce flags
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OpCMPQconst: {asm: "CMPQ\t$%A,%I0", reg: gp1_flags},
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OpTESTQ: {asm: "TESTQ\t%I0,%I1", reg: gp2_flags},
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OpTESTB: {asm: "TESTB\t%I0,%I1", reg: gp2_flags},
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OpCMPQ: {reg: gp2_flags}, // compute arg[0]-arg[1] and produce flags
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OpCMPQconst: {reg: gp1_flags},
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OpTESTQ: {reg: gp2_flags},
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OpTESTB: {reg: gp2_flags},
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OpLEAQ: {flags: OpFlagCommutative, asm: "LEAQ\t%A(%I0)(%I1*1),%O0", reg: gp21}, // aux = int64 constant to add
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OpLEAQ2: {asm: "LEAQ\t%A(%I0)(%I1*2),%O0"},
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OpLEAQ4: {asm: "LEAQ\t%A(%I0)(%I1*4),%O0"},
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OpLEAQ8: {asm: "LEAQ\t%A(%I0)(%I1*8),%O0"},
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OpLEAQglobal: {asm: "LEAQ\t%A(SB),%O0", reg: gp01},
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OpLEAQ: {flags: OpFlagCommutative, reg: gp21}, // aux = int64 constant to add
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OpLEAQ2: {},
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OpLEAQ4: {},
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OpLEAQ8: {},
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OpLEAQglobal: {reg: gp01},
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// loads and stores
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OpMOVBload: {asm: "MOVB\t%A(%I0),%O0", reg: gpload},
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OpMOVQload: {asm: "MOVQ\t%A(%I0),%O0", reg: gpload},
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OpMOVQstore: {asm: "MOVQ\t%I1,%A(%I0)", reg: gpstore},
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OpMOVQloadidx8: {asm: "MOVQ\t%A(%I0)(%I1*8),%O0", reg: gploadidx},
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OpMOVQstoreidx8: {asm: "MOVQ\t%I2,%A(%I0)(%I1*8)", reg: gpstoreidx},
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OpMOVBload: {reg: gpload},
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OpMOVQload: {reg: gpload},
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OpMOVQstore: {reg: gpstore},
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OpMOVQloadidx8: {reg: gploadidx},
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OpMOVQstoreidx8: {reg: gpstoreidx},
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OpMOVQconst: {asm: "MOVQ\t$%A,%O0", reg: gp01},
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OpMOVQconst: {reg: gp01},
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OpStaticCall: {asm: "CALL\t%A(SB)"},
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OpStaticCall: {},
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OpCopy: {asm: "MOVQ\t%I0,%O0", reg: gp11}, // TODO: make arch-specific
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OpConvNop: {asm: "MOVQ\t%I0,%O0", reg: gp11}, // TODO: make arch-specific. Or get rid of this altogether.
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OpCopy: {reg: gp11}, // TODO: make arch-specific
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OpConvNop: {reg: gp11}, // TODO: make arch-specific. Or get rid of this altogether.
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// convert from flags back to boolean
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OpSETL: {},
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@ -164,10 +164,10 @@ var amd64Table = map[Op]opInfo{
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// unlike regular loads & stores, these take no memory argument.
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// They are just like OpCopy but we use them during register allocation.
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// TODO: different widths, float
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OpLoadReg8: {asm: "MOVQ\t%I0,%O0"},
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OpStoreReg8: {asm: "MOVQ\t%I0,%O0"},
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OpLoadReg8: {},
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OpStoreReg8: {},
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OpREPMOVSB: {asm: "REP MOVSB", reg: [2][]regMask{{di, si, cx, 0}, {0}}}, // TODO: record that si/di/cx are clobbered
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OpREPMOVSB: {reg: [2][]regMask{{di, si, cx, 0}, {0}}}, // TODO: record that si/di/cx are clobbered
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}
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func init() {
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