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[dev.ssa] cmd/compile: some improvements to PPC codegen
Runs fibonacci for all integer types. Fold addressing arithmetic into stores. Updates #16010. Change-Id: I257982c82c00c80b00679757c3da345045968022 Reviewed-on: https://go-review.googlesource.com/25103 Reviewed-by: Cherry Zhang <cherryyz@google.com> Run-TryBot: David Chase <drchase@google.com>
This commit is contained in:
David Chase
parent
df2f813bd2
commit
7bca2c599d
@ -162,6 +162,39 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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}
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p.To.Type = obj.TYPE_REG
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p.To.Reg = gc.SSARegNum(v)
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case ssa.OpPPC64MOVDaddr:
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p := gc.Prog(ppc64.AMOVD)
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p.From.Type = obj.TYPE_ADDR
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p.To.Type = obj.TYPE_REG
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p.To.Reg = gc.SSARegNum(v)
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var wantreg string
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// Suspect comment, copied from ARM code
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// MOVD $sym+off(base), R
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// the assembler expands it as the following:
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// - base is SP: add constant offset to SP
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// when constant is large, tmp register (R11) may be used
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// - base is SB: load external address from constant pool (use relocation)
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switch v.Aux.(type) {
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default:
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v.Fatalf("aux is of unknown type %T", v.Aux)
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case *ssa.ExternSymbol:
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wantreg = "SB"
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gc.AddAux(&p.From, v)
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case *ssa.ArgSymbol, *ssa.AutoSymbol:
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wantreg = "SP"
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gc.AddAux(&p.From, v)
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case nil:
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// No sym, just MOVD $off(SP), R
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wantreg = "SP"
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p.From.Reg = ppc64.REGSP
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p.From.Offset = v.AuxInt
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}
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if reg := gc.SSAReg(v.Args[0]); reg.Name() != wantreg {
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v.Fatalf("bad reg %s for symbol type %T, want %s", reg.Name(), v.Aux, wantreg)
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}
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case ssa.OpPPC64MOVDconst, ssa.OpPPC64MOVWconst, ssa.OpPPC64MOVHconst, ssa.OpPPC64MOVBconst, ssa.OpPPC64FMOVDconst, ssa.OpPPC64FMOVSconst:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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@ -169,32 +202,26 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.To.Type = obj.TYPE_REG
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p.To.Reg = gc.SSARegNum(v)
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case ssa.OpPPC64FCMPU:
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case ssa.OpPPC64FCMPU, ssa.OpPPC64CMP, ssa.OpPPC64CMPW, ssa.OpPPC64CMPU, ssa.OpPPC64CMPWU:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = gc.SSARegNum(v.Args[1])
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p.Reg = gc.SSARegNum(v.Args[0])
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case ssa.OpPPC64CMP, ssa.OpPPC64CMPW, ssa.OpPPC64CMPU, ssa.OpPPC64CMPWU:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = gc.SSARegNum(v.Args[1])
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p.Reg = gc.SSARegNum(v.Args[0])
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p.From.Reg = gc.SSARegNum(v.Args[0])
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p.To.Type = obj.TYPE_REG
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p.To.Reg = gc.SSARegNum(v.Args[0])
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p.To.Reg = gc.SSARegNum(v.Args[1])
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case ssa.OpPPC64CMPconst:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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p.Reg = gc.SSARegNum(v.Args[0])
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p.From.Type = obj.TYPE_REG
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p.From.Reg = gc.SSARegNum(v.Args[0])
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p.To.Type = obj.TYPE_CONST
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p.To.Offset = v.AuxInt
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case ssa.OpPPC64MOVBreg, ssa.OpPPC64MOVBZreg, ssa.OpPPC64MOVHreg, ssa.OpPPC64MOVHZreg, ssa.OpPPC64MOVWreg, ssa.OpPPC64MOVWZreg:
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// Shift in register to required size
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = gc.SSARegNum(v.Args[0])
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p.To.Reg = gc.SSARegNum(v.Args[0])
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p.To.Reg = gc.SSARegNum(v)
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p.To.Type = obj.TYPE_REG
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case ssa.OpPPC64MOVDload, ssa.OpPPC64MOVWload, ssa.OpPPC64MOVBload, ssa.OpPPC64MOVHload, ssa.OpPPC64MOVWZload, ssa.OpPPC64MOVBZload, ssa.OpPPC64MOVHZload:
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@ -212,6 +239,7 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.To.Type = obj.TYPE_REG
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p.To.Reg = gc.SSARegNum(v)
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case ssa.OpPPC64MOVDstoreconst, ssa.OpPPC64MOVWstoreconst, ssa.OpPPC64MOVHstoreconst, ssa.OpPPC64MOVBstoreconst:
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// TODO: pretty sure this is bogus, PPC has no such instruction unless constant is zero.
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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sc := v.AuxValAndOff()
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@ -219,6 +247,7 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.To.Type = obj.TYPE_MEM
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p.To.Reg = gc.SSARegNum(v.Args[0])
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gc.AddAux2(&p.To, v, sc.Off())
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case ssa.OpPPC64MOVDstore, ssa.OpPPC64MOVWstore, ssa.OpPPC64MOVHstore, ssa.OpPPC64MOVBstore:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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@ -272,17 +301,79 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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}
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}
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var blockJump = [...]struct {
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asm, invasm obj.As
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}{
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ssa.BlockPPC64EQ: {ppc64.ABEQ, ppc64.ABNE},
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ssa.BlockPPC64NE: {ppc64.ABNE, ppc64.ABEQ},
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ssa.BlockPPC64LT: {ppc64.ABLT, ppc64.ABGE},
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ssa.BlockPPC64GE: {ppc64.ABGE, ppc64.ABLT},
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ssa.BlockPPC64LE: {ppc64.ABLE, ppc64.ABGT},
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ssa.BlockPPC64GT: {ppc64.ABGT, ppc64.ABLE},
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ssa.BlockPPC64ULT: {ppc64.ABLT, ppc64.ABGE},
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ssa.BlockPPC64UGE: {ppc64.ABGE, ppc64.ABLT},
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ssa.BlockPPC64ULE: {ppc64.ABLE, ppc64.ABGT},
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ssa.BlockPPC64UGT: {ppc64.ABGT, ppc64.ABLE},
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}
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func ssaGenBlock(s *gc.SSAGenState, b, next *ssa.Block) {
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s.SetLineno(b.Line)
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switch b.Kind {
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case ssa.BlockCall:
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case ssa.BlockPlain, ssa.BlockCall, ssa.BlockCheck:
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if b.Succs[0].Block() != next {
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p := gc.Prog(obj.AJMP)
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p.To.Type = obj.TYPE_BRANCH
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s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[0].Block()})
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}
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case ssa.BlockExit:
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gc.Prog(obj.AUNDEF) // tell plive.go that we never reach here
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case ssa.BlockRet:
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gc.Prog(obj.ARET)
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case ssa.BlockPPC64EQ, ssa.BlockPPC64NE,
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ssa.BlockPPC64LT, ssa.BlockPPC64GE,
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ssa.BlockPPC64LE, ssa.BlockPPC64GT,
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ssa.BlockPPC64ULT, ssa.BlockPPC64UGT,
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ssa.BlockPPC64ULE, ssa.BlockPPC64UGE:
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jmp := blockJump[b.Kind]
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likely := b.Likely
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var p *obj.Prog
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switch next {
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case b.Succs[0].Block():
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p = gc.Prog(jmp.invasm)
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likely *= -1
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p.To.Type = obj.TYPE_BRANCH
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s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[1].Block()})
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case b.Succs[1].Block():
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p = gc.Prog(jmp.asm)
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p.To.Type = obj.TYPE_BRANCH
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s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[0].Block()})
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default:
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p = gc.Prog(jmp.asm)
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p.To.Type = obj.TYPE_BRANCH
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s.Branches = append(s.Branches, gc.Branch{P: p, B: b.Succs[0].Block()})
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q := gc.Prog(obj.AJMP)
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q.To.Type = obj.TYPE_BRANCH
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s.Branches = append(s.Branches, gc.Branch{P: q, B: b.Succs[1].Block()})
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}
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// liblink reorders the instruction stream as it sees fit.
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// Pass along what we know so liblink can make use of it.
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// TODO: Once we've fully switched to SSA,
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// make liblink leave our output alone.
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//switch likely {
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//case ssa.BranchUnlikely:
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// p.From.Type = obj.TYPE_CONST
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// p.From.Offset = 0
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//case ssa.BranchLikely:
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// p.From.Type = obj.TYPE_CONST
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// p.From.Offset = 1
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//}
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default:
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b.Unimplementedf("branch not implemented: %s. Control: %s", b.LongString(), b.Control.LongString())
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}
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}
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@ -39,7 +39,8 @@
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(ConstNil) -> (MOVDconst [0])
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(ConstBool [b]) -> (MOVBconst [b])
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(Addr {sym} base) -> (ADDconst {sym} base)
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(Addr {sym} base) -> (MOVDaddr {sym} base)
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// (Addr {sym} base) -> (ADDconst {sym} base)
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(OffPtr [off] ptr) -> (ADD (MOVDconst <config.Frontend().TypeInt64()> [off]) ptr)
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(StaticCall [argwid] {target} mem) -> (CALLstatic [argwid] {target} mem)
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@ -148,7 +149,7 @@
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(Load <t> ptr mem) && is32BitInt(t) && !isSigned(t) -> (MOVWZload ptr mem)
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(Load <t> ptr mem) && is16BitInt(t) && isSigned(t) -> (MOVHload ptr mem)
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(Load <t> ptr mem) && is16BitInt(t) && !isSigned(t) -> (MOVHZload ptr mem)
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(Load <t> ptr mem) && (t.IsBoolean() || (is8BitInt(t) && !isSigned(t))) -> (MOVBload ptr mem)
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(Load <t> ptr mem) && (t.IsBoolean() || (is8BitInt(t) && isSigned(t))) -> (MOVBload ptr mem)
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(Load <t> ptr mem) && is8BitInt(t) && !isSigned(t) -> (MOVBZload ptr mem)
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(Load <t> ptr mem) && is32BitFloat(t) -> (FMOVSload ptr mem)
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(Load <t> ptr mem) && is64BitFloat(t) -> (FMOVDload ptr mem)
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@ -210,6 +211,14 @@
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(ADD (MOVDconst [c]) x) -> (ADDconst [c] x)
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(ADD x (MOVDconst [c])) -> (ADDconst [c] x)
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(MOVDstore [off1] {sym} (ADDconst [off2] x) val mem) && is16Bit(off1+off2) -> (MOVDstore [off1+off2] {sym} x val mem)
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(MOVWstore [off1] {sym} (ADDconst [off2] x) val mem) && is16Bit(off1+off2) -> (MOVWstore [off1+off2] {sym} x val mem)
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(MOVHstore [off1] {sym} (ADDconst [off2] x) val mem) && is16Bit(off1+off2) -> (MOVHstore [off1+off2] {sym} x val mem)
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(MOVBstore [off1] {sym} (ADDconst [off2] x) val mem) && is16Bit(off1+off2) -> (MOVBstore [off1+off2] {sym} x val mem)
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// TODO MOV*storeconst is wrong for PPC
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// (MOVDstore ptr (MOVDconst [c]) mem) && c == 0 -> (MOVDstoreconst [c] ptr mem)
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// Lowering extension
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// Note: we always extend to 64 bits even though some ops don't need that many result bits.
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(SignExt8to16 x) -> (MOVBreg x)
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@ -96,27 +96,27 @@ func init() {
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gp = buildReg("R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29")
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fp = buildReg("F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26")
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sp = buildReg("SP")
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// sb = buildReg("SB")
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sb = buildReg("SB")
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// gg = buildReg("R30")
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cr = buildReg("CR")
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// tmp = buildReg("R31")
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// ctxt = buildReg("R11")
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// tls = buildReg("R13")
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gp01 = regInfo{inputs: []regMask{}, outputs: []regMask{gp}}
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gp11 = regInfo{inputs: []regMask{gp | sp}, outputs: []regMask{gp}}
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gp21 = regInfo{inputs: []regMask{gp | sp, gp | sp}, outputs: []regMask{gp}}
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gp1cr = regInfo{inputs: []regMask{gp | sp}, outputs: []regMask{cr}}
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gp2cr = regInfo{inputs: []regMask{gp | sp, gp | sp}, outputs: []regMask{cr}}
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gp11 = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp}}
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gp21 = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{gp}}
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gp1cr = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{cr}}
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gp2cr = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{cr}}
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crgp = regInfo{inputs: []regMask{cr}, outputs: []regMask{gp}}
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gpload = regInfo{inputs: []regMask{gp | sp}, outputs: []regMask{gp}}
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gpstore = regInfo{inputs: []regMask{gp | sp, gp | sp}, outputs: []regMask{}}
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gpstoreconst = regInfo{inputs: []regMask{gp | sp, 0}, outputs: []regMask{}}
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gpload = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp}}
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gpstore = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{}}
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gpstoreconst = regInfo{inputs: []regMask{gp | sp | sb, 0}, outputs: []regMask{}}
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fp01 = regInfo{inputs: []regMask{}, outputs: []regMask{fp}}
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// fp11 = regInfo{inputs: []regMask{fp}, outputs: []regMask{fp}}
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fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{fp}}
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fp2cr = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{cr}}
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fpload = regInfo{inputs: []regMask{gp | sp}, outputs: []regMask{fp}}
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fpstore = regInfo{inputs: []regMask{fp, gp | sp}, outputs: []regMask{}}
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fpload = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{fp}}
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fpstore = regInfo{inputs: []regMask{gp | sp | sb, fp}, outputs: []regMask{}}
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callerSave = regMask(gp | fp)
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)
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ops := []opData{
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@ -167,6 +167,8 @@ func init() {
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{name: "MOVWstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVW", aux: "SymValAndOff", typ: "Mem"}, // store low 4 bytes of ...
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{name: "MOVDstoreconst", argLength: 2, reg: gpstoreconst, asm: "MOVD", aux: "SymValAndOff", typ: "Mem"}, // store 8 bytes of ...
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{name: "MOVDaddr", argLength: 1, reg: regInfo{inputs: []regMask{sp | sb}, outputs: []regMask{gp}}, aux: "SymOff", asm: "MOVD", rematerializeable: true}, // arg0 + auxInt + aux.(*gc.Sym), arg0=SP/SB
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{name: "MOVDconst", argLength: 0, reg: gp01, aux: "Int64", asm: "MOVD", rematerializeable: true}, //
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{name: "MOVWconst", argLength: 0, reg: gp01, aux: "Int32", asm: "MOVW", rematerializeable: true}, // 32 low bits of auxint
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{name: "MOVHconst", argLength: 0, reg: gp01, aux: "Int16", asm: "MOVH", rematerializeable: true}, // 16 low bits of auxint
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@ -819,6 +819,7 @@ const (
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OpPPC64MOVHstoreconst
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OpPPC64MOVWstoreconst
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OpPPC64MOVDstoreconst
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OpPPC64MOVDaddr
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OpPPC64MOVDconst
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OpPPC64MOVWconst
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OpPPC64MOVHconst
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@ -9827,8 +9828,8 @@ var opcodeTable = [...]opInfo{
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asm: ppc64.AADD,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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{1, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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outputs: []outputInfo{
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{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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@ -9842,7 +9843,7 @@ var opcodeTable = [...]opInfo{
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asm: ppc64.AADD,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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},
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outputs: []outputInfo{
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{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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@ -9885,8 +9886,8 @@ var opcodeTable = [...]opInfo{
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asm: ppc64.ASUB,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
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{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
@ -9928,8 +9929,8 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AMULLD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
@ -9943,8 +9944,8 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AMULLW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
@ -10016,8 +10017,8 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AAND,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
@ -10031,7 +10032,7 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AAND,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
@ -10045,8 +10046,8 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AOR,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
@ -10060,7 +10061,7 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AOR,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
@ -10074,8 +10075,8 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AXOR,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
@ -10089,7 +10090,7 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AXOR,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
@ -10102,7 +10103,7 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.ANEG,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
@ -10115,7 +10116,7 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AMOVB,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
@ -10128,7 +10129,7 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AMOVBZ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
@ -10141,7 +10142,7 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AMOVH,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
@ -10154,7 +10155,7 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AMOVHZ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
@ -10167,7 +10168,7 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AMOVW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
@ -10180,7 +10181,7 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AMOVWZ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
@ -10193,7 +10194,7 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AMOVB,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
@ -10206,7 +10207,7 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AMOVBZ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
@ -10219,7 +10220,7 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AMOVH,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
@ -10232,7 +10233,7 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AMOVHZ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
@ -10245,7 +10246,7 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AMOVW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
@ -10258,7 +10259,7 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AMOVWZ,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
@ -10271,7 +10272,7 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AMOVD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
@ -10284,7 +10285,7 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AFMOVD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
||||
@ -10297,7 +10298,7 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AFMOVS,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
||||
@ -10311,8 +10312,8 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AMOVB,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
},
|
||||
},
|
||||
@ -10323,8 +10324,8 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AMOVH,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
},
|
||||
},
|
||||
@ -10335,8 +10336,8 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AMOVW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
},
|
||||
},
|
||||
@ -10347,8 +10348,8 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AMOVD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
},
|
||||
},
|
||||
@ -10359,8 +10360,8 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AFMOVD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
||||
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
},
|
||||
},
|
||||
@ -10371,8 +10372,8 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AFMOVS,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
||||
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
},
|
||||
},
|
||||
@ -10383,7 +10384,7 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AMOVB,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
},
|
||||
},
|
||||
@ -10394,7 +10395,7 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AMOVH,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
},
|
||||
},
|
||||
@ -10405,7 +10406,7 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AMOVW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
},
|
||||
},
|
||||
@ -10416,7 +10417,22 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.AMOVD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
},
|
||||
},
|
||||
{
|
||||
name: "MOVDaddr",
|
||||
auxType: auxSymOff,
|
||||
argLen: 1,
|
||||
rematerializeable: true,
|
||||
asm: ppc64.AMOVD,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 6}, // SP SB
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 1073731576}, // R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
},
|
||||
},
|
||||
@ -10512,8 +10528,8 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.ACMP,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 576460752303423488}, // CR
|
||||
@ -10526,8 +10542,8 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.ACMPU,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 576460752303423488}, // CR
|
||||
@ -10540,8 +10556,8 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.ACMPW,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 576460752303423488}, // CR
|
||||
@ -10554,8 +10570,8 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.ACMPWU,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{1, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 576460752303423488}, // CR
|
||||
@ -10569,7 +10585,7 @@ var opcodeTable = [...]opInfo{
|
||||
asm: ppc64.ACMP,
|
||||
reg: regInfo{
|
||||
inputs: []inputInfo{
|
||||
{0, 1073731578}, // SP R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
{0, 1073731582}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
|
||||
},
|
||||
outputs: []outputInfo{
|
||||
{0, 576460752303423488}, // CR
|
||||
|
||||
@ -205,6 +205,11 @@ func is32Bit(n int64) bool {
|
||||
return n == int64(int32(n))
|
||||
}
|
||||
|
||||
// is16Bit reports whether n can be represented as a signed 16 bit integer.
|
||||
func is16Bit(n int64) bool {
|
||||
return n == int64(int16(n))
|
||||
}
|
||||
|
||||
// b2i translates a boolean value to 0 or 1 for assigning to auxInt.
|
||||
func b2i(b bool) int64 {
|
||||
if b {
|
||||
|
||||
@ -136,6 +136,14 @@ func rewriteValuePPC64(v *Value, config *Config) bool {
|
||||
return rewriteValuePPC64_OpLess8U(v, config)
|
||||
case OpLoad:
|
||||
return rewriteValuePPC64_OpLoad(v, config)
|
||||
case OpPPC64MOVBstore:
|
||||
return rewriteValuePPC64_OpPPC64MOVBstore(v, config)
|
||||
case OpPPC64MOVDstore:
|
||||
return rewriteValuePPC64_OpPPC64MOVDstore(v, config)
|
||||
case OpPPC64MOVHstore:
|
||||
return rewriteValuePPC64_OpPPC64MOVHstore(v, config)
|
||||
case OpPPC64MOVWstore:
|
||||
return rewriteValuePPC64_OpPPC64MOVWstore(v, config)
|
||||
case OpMul16:
|
||||
return rewriteValuePPC64_OpMul16(v, config)
|
||||
case OpMul32:
|
||||
@ -402,11 +410,11 @@ func rewriteValuePPC64_OpAddr(v *Value, config *Config) bool {
|
||||
_ = b
|
||||
// match: (Addr {sym} base)
|
||||
// cond:
|
||||
// result: (ADDconst {sym} base)
|
||||
// result: (MOVDaddr {sym} base)
|
||||
for {
|
||||
sym := v.Aux
|
||||
base := v.Args[0]
|
||||
v.reset(OpPPC64ADDconst)
|
||||
v.reset(OpPPC64MOVDaddr)
|
||||
v.Aux = sym
|
||||
v.AddArg(base)
|
||||
return true
|
||||
@ -1448,13 +1456,13 @@ func rewriteValuePPC64_OpLoad(v *Value, config *Config) bool {
|
||||
return true
|
||||
}
|
||||
// match: (Load <t> ptr mem)
|
||||
// cond: (t.IsBoolean() || (is8BitInt(t) && !isSigned(t)))
|
||||
// cond: (t.IsBoolean() || (is8BitInt(t) && isSigned(t)))
|
||||
// result: (MOVBload ptr mem)
|
||||
for {
|
||||
t := v.Type
|
||||
ptr := v.Args[0]
|
||||
mem := v.Args[1]
|
||||
if !(t.IsBoolean() || (is8BitInt(t) && !isSigned(t))) {
|
||||
if !(t.IsBoolean() || (is8BitInt(t) && isSigned(t))) {
|
||||
break
|
||||
}
|
||||
v.reset(OpPPC64MOVBload)
|
||||
@ -1509,6 +1517,126 @@ func rewriteValuePPC64_OpLoad(v *Value, config *Config) bool {
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValuePPC64_OpPPC64MOVBstore(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (MOVBstore [off1] {sym} (ADDconst [off2] x) val mem)
|
||||
// cond: is16Bit(off1+off2)
|
||||
// result: (MOVBstore [off1+off2] {sym} x val mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym := v.Aux
|
||||
v_0 := v.Args[0]
|
||||
if v_0.Op != OpPPC64ADDconst {
|
||||
break
|
||||
}
|
||||
off2 := v_0.AuxInt
|
||||
x := v_0.Args[0]
|
||||
val := v.Args[1]
|
||||
mem := v.Args[2]
|
||||
if !(is16Bit(off1 + off2)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpPPC64MOVBstore)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = sym
|
||||
v.AddArg(x)
|
||||
v.AddArg(val)
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValuePPC64_OpPPC64MOVDstore(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (MOVDstore [off1] {sym} (ADDconst [off2] x) val mem)
|
||||
// cond: is16Bit(off1+off2)
|
||||
// result: (MOVDstore [off1+off2] {sym} x val mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym := v.Aux
|
||||
v_0 := v.Args[0]
|
||||
if v_0.Op != OpPPC64ADDconst {
|
||||
break
|
||||
}
|
||||
off2 := v_0.AuxInt
|
||||
x := v_0.Args[0]
|
||||
val := v.Args[1]
|
||||
mem := v.Args[2]
|
||||
if !(is16Bit(off1 + off2)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpPPC64MOVDstore)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = sym
|
||||
v.AddArg(x)
|
||||
v.AddArg(val)
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValuePPC64_OpPPC64MOVHstore(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (MOVHstore [off1] {sym} (ADDconst [off2] x) val mem)
|
||||
// cond: is16Bit(off1+off2)
|
||||
// result: (MOVHstore [off1+off2] {sym} x val mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym := v.Aux
|
||||
v_0 := v.Args[0]
|
||||
if v_0.Op != OpPPC64ADDconst {
|
||||
break
|
||||
}
|
||||
off2 := v_0.AuxInt
|
||||
x := v_0.Args[0]
|
||||
val := v.Args[1]
|
||||
mem := v.Args[2]
|
||||
if !(is16Bit(off1 + off2)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpPPC64MOVHstore)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = sym
|
||||
v.AddArg(x)
|
||||
v.AddArg(val)
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValuePPC64_OpPPC64MOVWstore(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (MOVWstore [off1] {sym} (ADDconst [off2] x) val mem)
|
||||
// cond: is16Bit(off1+off2)
|
||||
// result: (MOVWstore [off1+off2] {sym} x val mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym := v.Aux
|
||||
v_0 := v.Args[0]
|
||||
if v_0.Op != OpPPC64ADDconst {
|
||||
break
|
||||
}
|
||||
off2 := v_0.AuxInt
|
||||
x := v_0.Args[0]
|
||||
val := v.Args[1]
|
||||
mem := v.Args[2]
|
||||
if !(is16Bit(off1 + off2)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpPPC64MOVWstore)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = sym
|
||||
v.AddArg(x)
|
||||
v.AddArg(val)
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValuePPC64_OpMul16(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
|
||||
Loading…
Reference in New Issue
Block a user