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[dev.ssa] cmd/compile/internal/ssa/gen: fold Mul8 properly.
Mul8 is lowered to MULW, but the rules for constant folding do not handle the fact that the operands are int8. Change-Id: I2c336686d86249393a8079a471c6ff74e6228f3d Reviewed-on: https://go-review.googlesource.com/13642 Reviewed-by: Keith Randall <khr@golang.org>
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@ -1909,7 +1909,7 @@ func genValue(v *ssa.Value) {
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ssa.OpAMD64ANDQ, ssa.OpAMD64ANDL, ssa.OpAMD64ANDW, ssa.OpAMD64ANDB,
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ssa.OpAMD64ORQ, ssa.OpAMD64ORL, ssa.OpAMD64ORW, ssa.OpAMD64ORB,
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ssa.OpAMD64XORQ, ssa.OpAMD64XORL, ssa.OpAMD64XORW, ssa.OpAMD64XORB,
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ssa.OpAMD64MULQ, ssa.OpAMD64MULL, ssa.OpAMD64MULW:
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ssa.OpAMD64MULQ, ssa.OpAMD64MULL, ssa.OpAMD64MULW, ssa.OpAMD64MULB:
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r := regnum(v)
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x := regnum(v.Args[0])
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y := regnum(v.Args[1])
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@ -1996,7 +1996,7 @@ func genValue(v *ssa.Value) {
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p.From.Offset = v.AuxInt
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p.To.Type = obj.TYPE_REG
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p.To.Reg = regnum(v)
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case ssa.OpAMD64MULQconst, ssa.OpAMD64MULLconst, ssa.OpAMD64MULWconst:
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case ssa.OpAMD64MULQconst, ssa.OpAMD64MULLconst, ssa.OpAMD64MULWconst, ssa.OpAMD64MULBconst:
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r := regnum(v)
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x := regnum(v.Args[0])
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if r != x {
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@ -25,10 +25,7 @@
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(MulPtr x y) -> (MULQ x y)
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(Mul32 x y) -> (MULL x y)
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(Mul16 x y) -> (MULW x y)
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// Note: we use 16-bit multiply instructions for 8-bit multiplies because
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// the 16-bit multiply instructions are more forgiving (they operate on
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// any register instead of just AX/DX).
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(Mul8 x y) -> (MULW x y)
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(Mul8 x y) -> (MULB x y)
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(And64 x y) -> (ANDQ x y)
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(And32 x y) -> (ANDL x y)
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@ -294,6 +291,8 @@
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(MULL (MOVLconst [c]) x) -> (MULLconst [c] x)
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(MULW x (MOVWconst [c])) -> (MULWconst [c] x)
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(MULW (MOVWconst [c]) x) -> (MULWconst [c] x)
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(MULB x (MOVBconst [c])) -> (MULBconst [c] x)
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(MULB (MOVBconst [c]) x) -> (MULBconst [c] x)
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(ANDQ x (MOVQconst [c])) && is32Bit(c) -> (ANDQconst [c] x)
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(ANDQ (MOVQconst [c]) x) && is32Bit(c) -> (ANDQconst [c] x)
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@ -498,6 +497,7 @@
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(MULQconst [c] (MOVQconst [d])) -> (MOVQconst [c*d])
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(MULLconst [c] (MOVLconst [d])) -> (MOVLconst [c*d])
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(MULWconst [c] (MOVWconst [d])) -> (MOVWconst [c*d])
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(MULBconst [c] (MOVBconst [d])) -> (MOVBconst [c*d])
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(ANDQconst [c] (MOVQconst [d])) -> (MOVQconst [c&d])
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(ANDLconst [c] (MOVLconst [d])) -> (MOVLconst [c&d])
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(ANDWconst [c] (MOVWconst [d])) -> (MOVWconst [c&d])
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@ -133,9 +133,11 @@ func init() {
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{name: "MULQ", reg: gp21, asm: "IMULQ"}, // arg0 * arg1
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{name: "MULL", reg: gp21, asm: "IMULL"}, // arg0 * arg1
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{name: "MULW", reg: gp21, asm: "IMULW"}, // arg0 * arg1
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{name: "MULB", reg: gp21, asm: "IMULW"}, // arg0 * arg1
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{name: "MULQconst", reg: gp11, asm: "IMULQ"}, // arg0 * auxint
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{name: "MULLconst", reg: gp11, asm: "IMULL"}, // arg0 * auxint
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{name: "MULWconst", reg: gp11, asm: "IMULW"}, // arg0 * auxint
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{name: "MULBconst", reg: gp11, asm: "IMULW"}, // arg0 * auxint
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{name: "ANDQ", reg: gp21, asm: "ANDQ"}, // arg0 & arg1
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{name: "ANDL", reg: gp21, asm: "ANDL"}, // arg0 & arg1
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@ -70,9 +70,11 @@ const (
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OpAMD64MULQ
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OpAMD64MULL
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OpAMD64MULW
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OpAMD64MULB
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OpAMD64MULQconst
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OpAMD64MULLconst
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OpAMD64MULWconst
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OpAMD64MULBconst
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OpAMD64ANDQ
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OpAMD64ANDL
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OpAMD64ANDW
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@ -630,6 +632,19 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "MULB",
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asm: x86.AIMULW,
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reg: regInfo{
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inputs: []regMask{
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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},
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{
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name: "MULQconst",
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asm: x86.AIMULQ,
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@ -666,6 +681,18 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "MULBconst",
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asm: x86.AIMULW,
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reg: regInfo{
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inputs: []regMask{
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65535, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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outputs: []regMask{
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65519, // .AX .CX .DX .BX .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15
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},
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},
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},
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{
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name: "ANDQ",
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asm: x86.AANDQ,
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@ -3511,6 +3511,67 @@ func rewriteValueAMD64(v *Value, config *Config) bool {
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goto end4e7df15ee55bdd73d8ecd61b759134d4
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end4e7df15ee55bdd73d8ecd61b759134d4:
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;
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case OpAMD64MULB:
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// match: (MULB x (MOVBconst [c]))
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// cond:
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// result: (MULBconst [c] x)
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{
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x := v.Args[0]
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if v.Args[1].Op != OpAMD64MOVBconst {
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goto end66c6419213ddeb52b1c53fb589a70e5f
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}
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c := v.Args[1].AuxInt
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v.Op = OpAMD64MULBconst
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AuxInt = c
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v.AddArg(x)
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return true
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}
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goto end66c6419213ddeb52b1c53fb589a70e5f
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end66c6419213ddeb52b1c53fb589a70e5f:
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;
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// match: (MULB (MOVBconst [c]) x)
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// cond:
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// result: (MULBconst [c] x)
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{
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if v.Args[0].Op != OpAMD64MOVBconst {
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goto end7e82c8dbbba265b78035ca7df394bb06
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}
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c := v.Args[0].AuxInt
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x := v.Args[1]
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v.Op = OpAMD64MULBconst
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AuxInt = c
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v.AddArg(x)
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return true
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}
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goto end7e82c8dbbba265b78035ca7df394bb06
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end7e82c8dbbba265b78035ca7df394bb06:
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;
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case OpAMD64MULBconst:
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// match: (MULBconst [c] (MOVBconst [d]))
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// cond:
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// result: (MOVBconst [c*d])
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{
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c := v.AuxInt
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if v.Args[0].Op != OpAMD64MOVBconst {
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goto endf2db9f96016085f8cb4082b4af01b2aa
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}
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d := v.Args[0].AuxInt
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v.Op = OpAMD64MOVBconst
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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v.AuxInt = c * d
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return true
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}
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goto endf2db9f96016085f8cb4082b4af01b2aa
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endf2db9f96016085f8cb4082b4af01b2aa:
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;
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case OpAMD64MULL:
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// match: (MULL x (MOVLconst [c]))
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// cond:
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@ -3913,11 +3974,11 @@ func rewriteValueAMD64(v *Value, config *Config) bool {
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case OpMul8:
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// match: (Mul8 x y)
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// cond:
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// result: (MULW x y)
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// result: (MULB x y)
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{
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x := v.Args[0]
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y := v.Args[1]
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v.Op = OpAMD64MULW
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v.Op = OpAMD64MULB
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v.AuxInt = 0
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v.Aux = nil
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v.resetArgs()
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@ -3925,8 +3986,8 @@ func rewriteValueAMD64(v *Value, config *Config) bool {
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v.AddArg(y)
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return true
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}
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goto end861428e804347e8489a6424f2e6ce71c
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end861428e804347e8489a6424f2e6ce71c:
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goto endd876d6bc42a2285b801f42dadbd8757c
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endd876d6bc42a2285b801f42dadbd8757c:
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;
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case OpMulPtr:
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// match: (MulPtr x y)
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