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cmd/asm: add 128-bit FLDPQ and FSTPQ instructions for arm64
This CL adds assembly support for 128-bit FLDPQ and FSTPQ instructions.
This CL also deletes some wrong pre/post-indexed LDP and STP instructions,
such as {ALDP, C_UAUTO4K, C_NONE, C_NONE, C_PAIR, 74, 8, REGSP, 0, C_XPRE},
because when the offset type is C_UAUTO4K, pre and post don't work.
Change-Id: Ifd901d4440eb06eb9e86c9dd17518749fdf32848
Reviewed-on: https://go-review.googlesource.com/c/go/+/273668
Trust: eric fang <eric.fang@arm.com>
Run-TryBot: eric fang <eric.fang@arm.com>
TryBot-Result: Go Bot <gobot@golang.org>
Reviewed-by: eric fang <eric.fang@arm.com>
Reviewed-by: Cherry Zhang <cherryyz@google.com>
This commit is contained in:
eric fang
parent
12bb256cb3
commit
79beddc773
48
src/cmd/asm/internal/asm/testdata/arm64.s
vendored
48
src/cmd/asm/internal/asm/testdata/arm64.s
vendored
@ -982,6 +982,54 @@ again:
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FSTPS (F3, F4), x(SB)
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FSTPS (F3, F4), x+8(SB)
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// FLDPQ/FSTPQ
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FLDPQ -4000(R0), (F1, F2) // 1b803ed1610b40ad
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FLDPQ -1024(R0), (F1, F2) // 010860ad
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FLDPQ (R0), (F1, F2) // 010840ad
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FLDPQ 16(R0), (F1, F2) // 018840ad
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FLDPQ -16(R0), (F1, F2) // 01887fad
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FLDPQ.W 32(R0), (F1, F2) // 0108c1ad
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FLDPQ.P 32(R0), (F1, F2) // 0108c1ac
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FLDPQ 11(R0), (F1, F2) // 1b2c0091610b40ad
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FLDPQ 1024(R0), (F1, F2) // 1b001091610b40ad
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FLDPQ 4104(R0), (F1, F2)
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FLDPQ -4000(RSP), (F1, F2) // fb833ed1610b40ad
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FLDPQ -1024(RSP), (F1, F2) // e10b60ad
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FLDPQ (RSP), (F1, F2) // e10b40ad
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FLDPQ 16(RSP), (F1, F2) // e18b40ad
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FLDPQ -16(RSP), (F1, F2) // e18b7fad
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FLDPQ.W 32(RSP), (F1, F2) // e10bc1ad
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FLDPQ.P 32(RSP), (F1, F2) // e10bc1ac
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FLDPQ 11(RSP), (F1, F2) // fb2f0091610b40ad
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FLDPQ 1024(RSP), (F1, F2) // fb031091610b40ad
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FLDPQ 4104(RSP), (F1, F2)
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FLDPQ -31(R0), (F1, F2) // 1b7c00d1610b40ad
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FLDPQ -4(R0), (F1, F2) // 1b1000d1610b40ad
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FLDPQ x(SB), (F1, F2)
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FLDPQ x+8(SB), (F1, F2)
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FSTPQ (F3, F4), -4000(R5) // bb803ed1631300ad
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FSTPQ (F3, F4), -1024(R5) // a31020ad
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FSTPQ (F3, F4), (R5) // a31000ad
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FSTPQ (F3, F4), 16(R5) // a39000ad
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FSTPQ (F3, F4), -16(R5) // a3903fad
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FSTPQ.W (F3, F4), 32(R5) // a31081ad
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FSTPQ.P (F3, F4), 32(R5) // a31081ac
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FSTPQ (F3, F4), 11(R5) // bb2c0091631300ad
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FSTPQ (F3, F4), 1024(R5) // bb001091631300ad
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FSTPQ (F3, F4), 4104(R5)
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FSTPQ (F3, F4), -4000(RSP) // fb833ed1631300ad
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FSTPQ (F3, F4), -1024(RSP) // e31320ad
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FSTPQ (F3, F4), (RSP) // e31300ad
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FSTPQ (F3, F4), 16(RSP) // e39300ad
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FSTPQ (F3, F4), -16(RSP) // e3933fad
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FSTPQ.W (F3, F4), 32(RSP) // e31381ad
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FSTPQ.P (F3, F4), 32(RSP) // e31381ac
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FSTPQ (F3, F4), 11(RSP) // fb2f0091631300ad
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FSTPQ (F3, F4), 1024(RSP) // fb031091631300ad
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FSTPQ (F3, F4), 4104(RSP)
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FSTPQ (F3, F4), x(SB)
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FSTPQ (F3, F4), x+8(SB)
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// System Register
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MSR $1, SPSel // bf4100d5
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MSR $9, DAIFSet // df4903d5
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@ -109,6 +109,9 @@ TEXT errors(SB),$0
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VREV16 V1.D1, V2.D1 // ERROR "invalid arrangement"
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VREV16 V1.B8, V2.B16 // ERROR "invalid arrangement"
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VREV16 V1.H4, V2.H4 // ERROR "invalid arrangement"
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FLDPQ (R0), (R1, R2) // ERROR "invalid register pair"
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FLDPQ (R1), (F2, F2) // ERROR "constrained unpredictable behavior"
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FSTPQ (R1, R2), (R0) // ERROR "invalid register pair"
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FLDPD (R0), (R1, R2) // ERROR "invalid register pair"
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FLDPD (R1), (F2, F2) // ERROR "constrained unpredictable behavior"
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FLDPS (R2), (F3, F3) // ERROR "constrained unpredictable behavior"
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@ -420,16 +420,21 @@ const (
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C_LBRA
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C_ZAUTO // 0(RSP)
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C_NSAUTO_16 // -256 <= x < 0, 0 mod 16
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C_NSAUTO_8 // -256 <= x < 0, 0 mod 8
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C_NSAUTO_4 // -256 <= x < 0, 0 mod 4
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C_NSAUTO // -256 <= x < 0
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C_NPAUTO_16 // -512 <= x < 0, 0 mod 16
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C_NPAUTO // -512 <= x < 0, 0 mod 8
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C_NQAUTO_16 // -1024 <= x < 0, 0 mod 16
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C_NAUTO4K // -4095 <= x < 0
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C_PSAUTO_16 // 0 to 255, 0 mod 16
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C_PSAUTO_8 // 0 to 255, 0 mod 8
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C_PSAUTO_4 // 0 to 255, 0 mod 4
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C_PSAUTO // 0 to 255
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C_PPAUTO_16 // 0 to 504, 0 mod 16
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C_PPAUTO // 0 to 504, 0 mod 8
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C_PQAUTO_16 // 0 to 1008, 0 mod 16
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C_UAUTO4K_16 // 0 to 4095, 0 mod 16
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C_UAUTO4K_8 // 0 to 4095, 0 mod 8
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C_UAUTO4K_4 // 0 to 4095, 0 mod 4
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@ -454,17 +459,22 @@ const (
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C_SEXT16 // 0 to 65520
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C_LEXT
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C_ZOREG // 0(R)
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C_NSOREG_8 // must mirror C_NSAUTO_8, etc
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C_ZOREG // 0(R)
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C_NSOREG_16 // must mirror C_NSAUTO_16, etc
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C_NSOREG_8
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C_NSOREG_4
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C_NSOREG
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C_NPOREG_16
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C_NPOREG
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C_NQOREG_16
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C_NOREG4K
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C_PSOREG_16
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C_PSOREG_8
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C_PSOREG_4
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C_PSOREG
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C_PPOREG_16
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C_PPOREG
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C_PQOREG_16
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C_UOREG4K_16
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C_UOREG4K_8
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C_UOREG4K_4
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@ -898,6 +908,7 @@ const (
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AFDIVD
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AFDIVS
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AFLDPD
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AFLDPQ
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AFLDPS
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AFMOVQ
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AFMOVD
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@ -912,6 +923,7 @@ const (
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AFSQRTD
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AFSQRTS
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AFSTPD
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AFSTPQ
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AFSTPS
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AFSUBD
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AFSUBS
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@ -392,6 +392,7 @@ var Anames = []string{
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"FDIVD",
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"FDIVS",
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"FLDPD",
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"FLDPQ",
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"FLDPS",
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"FMOVQ",
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"FMOVD",
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@ -406,6 +407,7 @@ var Anames = []string{
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"FSQRTD",
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"FSQRTS",
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"FSTPD",
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"FSTPQ",
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"FSTPS",
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"FSUBD",
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"FSUBS",
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@ -42,15 +42,21 @@ var cnames7 = []string{
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"SBRA",
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"LBRA",
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"ZAUTO",
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"NSAUTO_16",
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"NSAUTO_8",
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"NSAUTO_4",
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"NSAUTO",
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"NPAUTO_16",
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"NPAUTO",
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"NQAUTO_16",
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"NAUTO4K",
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"PSAUTO_16",
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"PSAUTO_8",
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"PSAUTO_4",
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"PSAUTO",
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"PPAUTO_16",
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"PPAUTO",
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"PQAUTO_16",
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"UAUTO4K_16",
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"UAUTO4K_8",
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"UAUTO4K_4",
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@ -74,15 +80,21 @@ var cnames7 = []string{
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"SEXT16",
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"LEXT",
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"ZOREG",
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"NSOREG_16",
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"NSOREG_8",
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"NSOREG_4",
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"NSOREG",
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"NPOREG_16",
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"NPOREG",
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"NQOREG_16",
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"NOREG4K",
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"PSOREG_16",
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"PSOREG_8",
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"PSOREG_4",
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"PSOREG",
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"PPOREG_16",
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"PPOREG",
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"PQOREG_16",
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"UOREG4K_16",
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"UOREG4K_8",
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"UOREG4K_4",
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@ -689,6 +689,46 @@ var optab = []Optab{
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/* pre/post-indexed/signed-offset load/store register pair
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(unscaled, signed 10-bit quad-aligned and long offset) */
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{AFLDPQ, C_NQAUTO_16, C_NONE, C_NONE, C_PAIR, 66, 4, REGSP, 0, 0},
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{AFLDPQ, C_NQAUTO_16, C_NONE, C_NONE, C_PAIR, 66, 4, REGSP, 0, C_XPRE},
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{AFLDPQ, C_NQAUTO_16, C_NONE, C_NONE, C_PAIR, 66, 4, REGSP, 0, C_XPOST},
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{AFLDPQ, C_PQAUTO_16, C_NONE, C_NONE, C_PAIR, 66, 4, REGSP, 0, 0},
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{AFLDPQ, C_PQAUTO_16, C_NONE, C_NONE, C_PAIR, 66, 4, REGSP, 0, C_XPRE},
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{AFLDPQ, C_PQAUTO_16, C_NONE, C_NONE, C_PAIR, 66, 4, REGSP, 0, C_XPOST},
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{AFLDPQ, C_UAUTO4K, C_NONE, C_NONE, C_PAIR, 74, 8, REGSP, 0, 0},
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{AFLDPQ, C_NAUTO4K, C_NONE, C_NONE, C_PAIR, 74, 8, REGSP, 0, 0},
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{AFLDPQ, C_LAUTO, C_NONE, C_NONE, C_PAIR, 75, 12, REGSP, LFROM, 0},
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{AFLDPQ, C_NQOREG_16, C_NONE, C_NONE, C_PAIR, 66, 4, 0, 0, 0},
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{AFLDPQ, C_NQOREG_16, C_NONE, C_NONE, C_PAIR, 66, 4, 0, 0, C_XPRE},
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{AFLDPQ, C_NQOREG_16, C_NONE, C_NONE, C_PAIR, 66, 4, 0, 0, C_XPOST},
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{AFLDPQ, C_PQOREG_16, C_NONE, C_NONE, C_PAIR, 66, 4, 0, 0, 0},
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{AFLDPQ, C_PQOREG_16, C_NONE, C_NONE, C_PAIR, 66, 4, 0, 0, C_XPRE},
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{AFLDPQ, C_PQOREG_16, C_NONE, C_NONE, C_PAIR, 66, 4, 0, 0, C_XPOST},
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{AFLDPQ, C_UOREG4K, C_NONE, C_NONE, C_PAIR, 74, 8, 0, 0, 0},
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{AFLDPQ, C_NOREG4K, C_NONE, C_NONE, C_PAIR, 74, 8, 0, 0, 0},
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{AFLDPQ, C_LOREG, C_NONE, C_NONE, C_PAIR, 75, 12, 0, LFROM, 0},
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{AFLDPQ, C_ADDR, C_NONE, C_NONE, C_PAIR, 88, 12, 0, 0, 0},
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{AFSTPQ, C_PAIR, C_NONE, C_NONE, C_NQAUTO_16, 67, 4, REGSP, 0, 0},
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{AFSTPQ, C_PAIR, C_NONE, C_NONE, C_NQAUTO_16, 67, 4, REGSP, 0, C_XPRE},
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{AFSTPQ, C_PAIR, C_NONE, C_NONE, C_NQAUTO_16, 67, 4, REGSP, 0, C_XPOST},
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{AFSTPQ, C_PAIR, C_NONE, C_NONE, C_PQAUTO_16, 67, 4, REGSP, 0, 0},
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{AFSTPQ, C_PAIR, C_NONE, C_NONE, C_PQAUTO_16, 67, 4, REGSP, 0, C_XPRE},
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{AFSTPQ, C_PAIR, C_NONE, C_NONE, C_PQAUTO_16, 67, 4, REGSP, 0, C_XPOST},
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{AFSTPQ, C_PAIR, C_NONE, C_NONE, C_UAUTO4K, 76, 8, REGSP, 0, 0},
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{AFSTPQ, C_PAIR, C_NONE, C_NONE, C_NAUTO4K, 76, 12, REGSP, 0, 0},
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{AFSTPQ, C_PAIR, C_NONE, C_NONE, C_LAUTO, 77, 12, REGSP, LTO, 0},
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{AFSTPQ, C_PAIR, C_NONE, C_NONE, C_NQOREG_16, 67, 4, 0, 0, 0},
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{AFSTPQ, C_PAIR, C_NONE, C_NONE, C_NQOREG_16, 67, 4, 0, 0, C_XPRE},
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{AFSTPQ, C_PAIR, C_NONE, C_NONE, C_NQOREG_16, 67, 4, 0, 0, C_XPOST},
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{AFSTPQ, C_PAIR, C_NONE, C_NONE, C_PQOREG_16, 67, 4, 0, 0, 0},
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{AFSTPQ, C_PAIR, C_NONE, C_NONE, C_PQOREG_16, 67, 4, 0, 0, C_XPRE},
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{AFSTPQ, C_PAIR, C_NONE, C_NONE, C_PQOREG_16, 67, 4, 0, 0, C_XPOST},
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{AFSTPQ, C_PAIR, C_NONE, C_NONE, C_UOREG4K, 76, 8, 0, 0, 0},
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{AFSTPQ, C_PAIR, C_NONE, C_NONE, C_NOREG4K, 76, 8, 0, 0, 0},
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{AFSTPQ, C_PAIR, C_NONE, C_NONE, C_LOREG, 77, 12, 0, LTO, 0},
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{AFSTPQ, C_PAIR, C_NONE, C_NONE, C_ADDR, 87, 12, 0, 0, 0},
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{ALDP, C_NPAUTO, C_NONE, C_NONE, C_PAIR, 66, 4, REGSP, 0, 0},
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{ALDP, C_NPAUTO, C_NONE, C_NONE, C_PAIR, 66, 4, REGSP, 0, C_XPRE},
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{ALDP, C_NPAUTO, C_NONE, C_NONE, C_PAIR, 66, 4, REGSP, 0, C_XPOST},
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@ -696,14 +736,8 @@ var optab = []Optab{
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{ALDP, C_PPAUTO, C_NONE, C_NONE, C_PAIR, 66, 4, REGSP, 0, C_XPRE},
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{ALDP, C_PPAUTO, C_NONE, C_NONE, C_PAIR, 66, 4, REGSP, 0, C_XPOST},
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{ALDP, C_UAUTO4K, C_NONE, C_NONE, C_PAIR, 74, 8, REGSP, 0, 0},
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{ALDP, C_UAUTO4K, C_NONE, C_NONE, C_PAIR, 74, 8, REGSP, 0, C_XPRE},
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{ALDP, C_UAUTO4K, C_NONE, C_NONE, C_PAIR, 74, 8, REGSP, 0, C_XPOST},
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{ALDP, C_NAUTO4K, C_NONE, C_NONE, C_PAIR, 74, 8, REGSP, 0, 0},
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{ALDP, C_NAUTO4K, C_NONE, C_NONE, C_PAIR, 74, 8, REGSP, 0, C_XPRE},
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{ALDP, C_NAUTO4K, C_NONE, C_NONE, C_PAIR, 74, 8, REGSP, 0, C_XPOST},
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{ALDP, C_LAUTO, C_NONE, C_NONE, C_PAIR, 75, 12, REGSP, LFROM, 0},
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{ALDP, C_LAUTO, C_NONE, C_NONE, C_PAIR, 75, 12, REGSP, LFROM, C_XPRE},
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{ALDP, C_LAUTO, C_NONE, C_NONE, C_PAIR, 75, 12, REGSP, LFROM, C_XPOST},
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{ALDP, C_NPOREG, C_NONE, C_NONE, C_PAIR, 66, 4, 0, 0, 0},
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{ALDP, C_NPOREG, C_NONE, C_NONE, C_PAIR, 66, 4, 0, 0, C_XPRE},
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{ALDP, C_NPOREG, C_NONE, C_NONE, C_PAIR, 66, 4, 0, 0, C_XPOST},
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@ -711,14 +745,8 @@ var optab = []Optab{
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{ALDP, C_PPOREG, C_NONE, C_NONE, C_PAIR, 66, 4, 0, 0, C_XPRE},
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{ALDP, C_PPOREG, C_NONE, C_NONE, C_PAIR, 66, 4, 0, 0, C_XPOST},
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{ALDP, C_UOREG4K, C_NONE, C_NONE, C_PAIR, 74, 8, 0, 0, 0},
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{ALDP, C_UOREG4K, C_NONE, C_NONE, C_PAIR, 74, 8, 0, 0, C_XPRE},
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{ALDP, C_UOREG4K, C_NONE, C_NONE, C_PAIR, 74, 8, 0, 0, C_XPOST},
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{ALDP, C_NOREG4K, C_NONE, C_NONE, C_PAIR, 74, 8, 0, 0, 0},
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{ALDP, C_NOREG4K, C_NONE, C_NONE, C_PAIR, 74, 8, 0, 0, C_XPRE},
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{ALDP, C_NOREG4K, C_NONE, C_NONE, C_PAIR, 74, 8, 0, 0, C_XPOST},
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{ALDP, C_LOREG, C_NONE, C_NONE, C_PAIR, 75, 12, 0, LFROM, 0},
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{ALDP, C_LOREG, C_NONE, C_NONE, C_PAIR, 75, 12, 0, LFROM, C_XPRE},
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{ALDP, C_LOREG, C_NONE, C_NONE, C_PAIR, 75, 12, 0, LFROM, C_XPOST},
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{ALDP, C_ADDR, C_NONE, C_NONE, C_PAIR, 88, 12, 0, 0, 0},
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{ASTP, C_PAIR, C_NONE, C_NONE, C_NPAUTO, 67, 4, REGSP, 0, 0},
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@ -728,14 +756,8 @@ var optab = []Optab{
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{ASTP, C_PAIR, C_NONE, C_NONE, C_PPAUTO, 67, 4, REGSP, 0, C_XPRE},
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{ASTP, C_PAIR, C_NONE, C_NONE, C_PPAUTO, 67, 4, REGSP, 0, C_XPOST},
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{ASTP, C_PAIR, C_NONE, C_NONE, C_UAUTO4K, 76, 8, REGSP, 0, 0},
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{ASTP, C_PAIR, C_NONE, C_NONE, C_UAUTO4K, 76, 8, REGSP, 0, C_XPRE},
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{ASTP, C_PAIR, C_NONE, C_NONE, C_UAUTO4K, 76, 8, REGSP, 0, C_XPOST},
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{ASTP, C_PAIR, C_NONE, C_NONE, C_NAUTO4K, 76, 12, REGSP, 0, 0},
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{ASTP, C_PAIR, C_NONE, C_NONE, C_NAUTO4K, 76, 12, REGSP, 0, C_XPRE},
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{ASTP, C_PAIR, C_NONE, C_NONE, C_NAUTO4K, 76, 12, REGSP, 0, C_XPOST},
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{ASTP, C_PAIR, C_NONE, C_NONE, C_LAUTO, 77, 12, REGSP, LTO, 0},
|
||||
{ASTP, C_PAIR, C_NONE, C_NONE, C_LAUTO, 77, 12, REGSP, LTO, C_XPRE},
|
||||
{ASTP, C_PAIR, C_NONE, C_NONE, C_LAUTO, 77, 12, REGSP, LTO, C_XPOST},
|
||||
{ASTP, C_PAIR, C_NONE, C_NONE, C_NPOREG, 67, 4, 0, 0, 0},
|
||||
{ASTP, C_PAIR, C_NONE, C_NONE, C_NPOREG, 67, 4, 0, 0, C_XPRE},
|
||||
{ASTP, C_PAIR, C_NONE, C_NONE, C_NPOREG, 67, 4, 0, 0, C_XPOST},
|
||||
@ -743,14 +765,8 @@ var optab = []Optab{
|
||||
{ASTP, C_PAIR, C_NONE, C_NONE, C_PPOREG, 67, 4, 0, 0, C_XPRE},
|
||||
{ASTP, C_PAIR, C_NONE, C_NONE, C_PPOREG, 67, 4, 0, 0, C_XPOST},
|
||||
{ASTP, C_PAIR, C_NONE, C_NONE, C_UOREG4K, 76, 8, 0, 0, 0},
|
||||
{ASTP, C_PAIR, C_NONE, C_NONE, C_UOREG4K, 76, 8, 0, 0, C_XPRE},
|
||||
{ASTP, C_PAIR, C_NONE, C_NONE, C_UOREG4K, 76, 8, 0, 0, C_XPOST},
|
||||
{ASTP, C_PAIR, C_NONE, C_NONE, C_NOREG4K, 76, 8, 0, 0, 0},
|
||||
{ASTP, C_PAIR, C_NONE, C_NONE, C_NOREG4K, 76, 8, 0, 0, C_XPRE},
|
||||
{ASTP, C_PAIR, C_NONE, C_NONE, C_NOREG4K, 76, 8, 0, 0, C_XPOST},
|
||||
{ASTP, C_PAIR, C_NONE, C_NONE, C_LOREG, 77, 12, 0, LTO, 0},
|
||||
{ASTP, C_PAIR, C_NONE, C_NONE, C_LOREG, 77, 12, 0, LTO, C_XPRE},
|
||||
{ASTP, C_PAIR, C_NONE, C_NONE, C_LOREG, 77, 12, 0, LTO, C_XPOST},
|
||||
{ASTP, C_PAIR, C_NONE, C_NONE, C_ADDR, 87, 12, 0, 0, 0},
|
||||
|
||||
// differ from LDP/STP for C_NSAUTO_4/C_PSAUTO_4/C_NSOREG_4/C_PSOREG_4
|
||||
@ -761,14 +777,8 @@ var optab = []Optab{
|
||||
{ALDPW, C_PSAUTO_4, C_NONE, C_NONE, C_PAIR, 66, 4, REGSP, 0, C_XPRE},
|
||||
{ALDPW, C_PSAUTO_4, C_NONE, C_NONE, C_PAIR, 66, 4, REGSP, 0, C_XPOST},
|
||||
{ALDPW, C_UAUTO4K, C_NONE, C_NONE, C_PAIR, 74, 8, REGSP, 0, 0},
|
||||
{ALDPW, C_UAUTO4K, C_NONE, C_NONE, C_PAIR, 74, 8, REGSP, 0, C_XPRE},
|
||||
{ALDPW, C_UAUTO4K, C_NONE, C_NONE, C_PAIR, 74, 8, REGSP, 0, C_XPOST},
|
||||
{ALDPW, C_NAUTO4K, C_NONE, C_NONE, C_PAIR, 74, 8, REGSP, 0, 0},
|
||||
{ALDPW, C_NAUTO4K, C_NONE, C_NONE, C_PAIR, 74, 8, REGSP, 0, C_XPRE},
|
||||
{ALDPW, C_NAUTO4K, C_NONE, C_NONE, C_PAIR, 74, 8, REGSP, 0, C_XPOST},
|
||||
{ALDPW, C_LAUTO, C_NONE, C_NONE, C_PAIR, 75, 12, REGSP, LFROM, 0},
|
||||
{ALDPW, C_LAUTO, C_NONE, C_NONE, C_PAIR, 75, 12, REGSP, LFROM, C_XPRE},
|
||||
{ALDPW, C_LAUTO, C_NONE, C_NONE, C_PAIR, 75, 12, REGSP, LFROM, C_XPOST},
|
||||
{ALDPW, C_NSOREG_4, C_NONE, C_NONE, C_PAIR, 66, 4, 0, 0, 0},
|
||||
{ALDPW, C_NSOREG_4, C_NONE, C_NONE, C_PAIR, 66, 4, 0, 0, C_XPRE},
|
||||
{ALDPW, C_NSOREG_4, C_NONE, C_NONE, C_PAIR, 66, 4, 0, 0, C_XPOST},
|
||||
@ -776,14 +786,8 @@ var optab = []Optab{
|
||||
{ALDPW, C_PSOREG_4, C_NONE, C_NONE, C_PAIR, 66, 4, 0, 0, C_XPRE},
|
||||
{ALDPW, C_PSOREG_4, C_NONE, C_NONE, C_PAIR, 66, 4, 0, 0, C_XPOST},
|
||||
{ALDPW, C_UOREG4K, C_NONE, C_NONE, C_PAIR, 74, 8, 0, 0, 0},
|
||||
{ALDPW, C_UOREG4K, C_NONE, C_NONE, C_PAIR, 74, 8, 0, 0, C_XPRE},
|
||||
{ALDPW, C_UOREG4K, C_NONE, C_NONE, C_PAIR, 74, 8, 0, 0, C_XPOST},
|
||||
{ALDPW, C_NOREG4K, C_NONE, C_NONE, C_PAIR, 74, 8, 0, 0, 0},
|
||||
{ALDPW, C_NOREG4K, C_NONE, C_NONE, C_PAIR, 74, 8, 0, 0, C_XPRE},
|
||||
{ALDPW, C_NOREG4K, C_NONE, C_NONE, C_PAIR, 74, 8, 0, 0, C_XPOST},
|
||||
{ALDPW, C_LOREG, C_NONE, C_NONE, C_PAIR, 75, 12, 0, LFROM, 0},
|
||||
{ALDPW, C_LOREG, C_NONE, C_NONE, C_PAIR, 75, 12, 0, LFROM, C_XPRE},
|
||||
{ALDPW, C_LOREG, C_NONE, C_NONE, C_PAIR, 75, 12, 0, LFROM, C_XPOST},
|
||||
{ALDPW, C_ADDR, C_NONE, C_NONE, C_PAIR, 88, 12, 0, 0, 0},
|
||||
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_NSAUTO_4, 67, 4, REGSP, 0, 0},
|
||||
@ -793,14 +797,8 @@ var optab = []Optab{
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_PSAUTO_4, 67, 4, REGSP, 0, C_XPRE},
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_PSAUTO_4, 67, 4, REGSP, 0, C_XPOST},
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_UAUTO4K, 76, 8, REGSP, 0, 0},
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_UAUTO4K, 76, 8, REGSP, 0, C_XPRE},
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_UAUTO4K, 76, 8, REGSP, 0, C_XPOST},
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_NAUTO4K, 76, 12, REGSP, 0, 0},
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_NAUTO4K, 76, 12, REGSP, 0, C_XPRE},
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_NAUTO4K, 76, 12, REGSP, 0, C_XPOST},
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_LAUTO, 77, 12, REGSP, LTO, 0},
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_LAUTO, 77, 12, REGSP, LTO, C_XPRE},
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_LAUTO, 77, 12, REGSP, LTO, C_XPOST},
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_NSOREG_4, 67, 4, 0, 0, 0},
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_NSOREG_4, 67, 4, 0, 0, C_XPRE},
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_NSOREG_4, 67, 4, 0, 0, C_XPOST},
|
||||
@ -808,14 +806,8 @@ var optab = []Optab{
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_PSOREG_4, 67, 4, 0, 0, C_XPRE},
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_PSOREG_4, 67, 4, 0, 0, C_XPOST},
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_UOREG4K, 76, 8, 0, 0, 0},
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_UOREG4K, 76, 8, 0, 0, C_XPRE},
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_UOREG4K, 76, 8, 0, 0, C_XPOST},
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_NOREG4K, 76, 8, 0, 0, 0},
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_NOREG4K, 76, 8, 0, 0, C_XPRE},
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_NOREG4K, 76, 8, 0, 0, C_XPOST},
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_LOREG, 77, 12, 0, LTO, 0},
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_LOREG, 77, 12, 0, LTO, C_XPRE},
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_LOREG, 77, 12, 0, LTO, C_XPOST},
|
||||
{ASTPW, C_PAIR, C_NONE, C_NONE, C_ADDR, 87, 12, 0, 0, 0},
|
||||
|
||||
{ASWPD, C_REG, C_NONE, C_NONE, C_ZOREG, 47, 4, 0, 0, 0}, // RegTo2=C_REG
|
||||
@ -1276,12 +1268,27 @@ func (c *ctxt7) addpool(p *obj.Prog, a *obj.Addr) {
|
||||
case C_ADDCON:
|
||||
fallthrough
|
||||
|
||||
case C_ZAUTO,
|
||||
C_PSAUTO,
|
||||
case C_ADDCON2,
|
||||
C_LCON,
|
||||
C_VCON,
|
||||
C_LACON,
|
||||
|
||||
C_ZAUTO,
|
||||
C_NSAUTO_16,
|
||||
C_NSAUTO_8,
|
||||
C_NSAUTO_4,
|
||||
C_NSAUTO,
|
||||
C_NPAUTO_16,
|
||||
C_NPAUTO,
|
||||
C_NQAUTO_16,
|
||||
C_NAUTO4K,
|
||||
C_PSAUTO_16,
|
||||
C_PSAUTO_8,
|
||||
C_PSAUTO_4,
|
||||
C_PSAUTO,
|
||||
C_PPAUTO_16,
|
||||
C_PPAUTO,
|
||||
C_PQAUTO_16,
|
||||
C_UAUTO4K_16,
|
||||
C_UAUTO4K_8,
|
||||
C_UAUTO4K_4,
|
||||
@ -1297,17 +1304,24 @@ func (c *ctxt7) addpool(p *obj.Prog, a *obj.Addr) {
|
||||
C_UAUTO32K_16,
|
||||
C_UAUTO32K,
|
||||
C_UAUTO64K,
|
||||
C_NSAUTO_8,
|
||||
C_NSAUTO_4,
|
||||
C_NSAUTO,
|
||||
C_NPAUTO,
|
||||
C_NAUTO4K,
|
||||
C_LAUTO,
|
||||
C_PSOREG,
|
||||
|
||||
C_ZOREG,
|
||||
C_NSOREG_16,
|
||||
C_NSOREG_8,
|
||||
C_NSOREG_4,
|
||||
C_NSOREG,
|
||||
C_NPOREG_16,
|
||||
C_NPOREG,
|
||||
C_NQOREG_16,
|
||||
C_NOREG4K,
|
||||
C_PSOREG_16,
|
||||
C_PSOREG_8,
|
||||
C_PSOREG_4,
|
||||
C_PSOREG,
|
||||
C_PPOREG_16,
|
||||
C_PPOREG,
|
||||
C_PQOREG_16,
|
||||
C_UOREG4K_16,
|
||||
C_UOREG4K_8,
|
||||
C_UOREG4K_4,
|
||||
@ -1323,16 +1337,7 @@ func (c *ctxt7) addpool(p *obj.Prog, a *obj.Addr) {
|
||||
C_UOREG32K_16,
|
||||
C_UOREG32K,
|
||||
C_UOREG64K,
|
||||
C_NSOREG_8,
|
||||
C_NSOREG_4,
|
||||
C_NSOREG,
|
||||
C_NPOREG,
|
||||
C_NOREG4K,
|
||||
C_LOREG,
|
||||
C_LACON,
|
||||
C_ADDCON2,
|
||||
C_LCON,
|
||||
C_VCON:
|
||||
C_LOREG:
|
||||
if a.Name == obj.NAME_EXTERN {
|
||||
fmt.Printf("addpool: %v in %v needs reloc\n", DRconv(cls), p)
|
||||
}
|
||||
@ -1590,6 +1595,9 @@ func autoclass(l int64) int {
|
||||
}
|
||||
|
||||
if l < 0 {
|
||||
if l >= -256 && (l&15) == 0 {
|
||||
return C_NSAUTO_16
|
||||
}
|
||||
if l >= -256 && (l&7) == 0 {
|
||||
return C_NSAUTO_8
|
||||
}
|
||||
@ -1599,9 +1607,15 @@ func autoclass(l int64) int {
|
||||
if l >= -256 {
|
||||
return C_NSAUTO
|
||||
}
|
||||
if l >= -512 && (l&15) == 0 {
|
||||
return C_NPAUTO_16
|
||||
}
|
||||
if l >= -512 && (l&7) == 0 {
|
||||
return C_NPAUTO
|
||||
}
|
||||
if l >= -1024 && (l&15) == 0 {
|
||||
return C_NQAUTO_16
|
||||
}
|
||||
if l >= -4095 {
|
||||
return C_NAUTO4K
|
||||
}
|
||||
@ -1609,6 +1623,9 @@ func autoclass(l int64) int {
|
||||
}
|
||||
|
||||
if l <= 255 {
|
||||
if (l & 15) == 0 {
|
||||
return C_PSAUTO_16
|
||||
}
|
||||
if (l & 7) == 0 {
|
||||
return C_PSAUTO_8
|
||||
}
|
||||
@ -1625,6 +1642,11 @@ func autoclass(l int64) int {
|
||||
return C_PPAUTO
|
||||
}
|
||||
}
|
||||
if l <= 1008 {
|
||||
if l&15 == 0 {
|
||||
return C_PQAUTO_16
|
||||
}
|
||||
}
|
||||
if l <= 4095 {
|
||||
if l&15 == 0 {
|
||||
return C_UAUTO4K_16
|
||||
@ -2193,64 +2215,99 @@ func cmp(a int, b int) bool {
|
||||
return true
|
||||
}
|
||||
|
||||
case C_NSAUTO_8:
|
||||
if b == C_NSAUTO_16 {
|
||||
return true
|
||||
}
|
||||
|
||||
case C_NSAUTO_4:
|
||||
if b == C_NSAUTO_8 {
|
||||
if b == C_NSAUTO_16 || b == C_NSAUTO_8 {
|
||||
return true
|
||||
}
|
||||
|
||||
case C_NSAUTO:
|
||||
switch b {
|
||||
case C_NSAUTO_4, C_NSAUTO_8:
|
||||
case C_NSAUTO_4, C_NSAUTO_8, C_NSAUTO_16:
|
||||
return true
|
||||
}
|
||||
|
||||
case C_NPAUTO_16:
|
||||
switch b {
|
||||
case C_NSAUTO_16:
|
||||
return true
|
||||
}
|
||||
|
||||
case C_NPAUTO:
|
||||
switch b {
|
||||
case C_NSAUTO_8:
|
||||
case C_NSAUTO_16, C_NSAUTO_8, C_NPAUTO_16:
|
||||
return true
|
||||
}
|
||||
|
||||
case C_NQAUTO_16:
|
||||
switch b {
|
||||
case C_NSAUTO_16, C_NPAUTO_16:
|
||||
return true
|
||||
}
|
||||
|
||||
case C_NAUTO4K:
|
||||
switch b {
|
||||
case C_NSAUTO_8, C_NSAUTO_4, C_NSAUTO, C_NPAUTO:
|
||||
case C_NSAUTO_16, C_NSAUTO_8, C_NSAUTO_4, C_NSAUTO, C_NPAUTO_16,
|
||||
C_NPAUTO, C_NQAUTO_16:
|
||||
return true
|
||||
}
|
||||
|
||||
case C_PSAUTO_16:
|
||||
if b == C_ZAUTO {
|
||||
return true
|
||||
}
|
||||
|
||||
case C_PSAUTO_8:
|
||||
if b == C_ZAUTO {
|
||||
if b == C_ZAUTO || b == C_PSAUTO_16 {
|
||||
return true
|
||||
}
|
||||
|
||||
case C_PSAUTO_4:
|
||||
switch b {
|
||||
case C_ZAUTO, C_PSAUTO_8:
|
||||
case C_ZAUTO, C_PSAUTO_16, C_PSAUTO_8:
|
||||
return true
|
||||
}
|
||||
|
||||
case C_PSAUTO:
|
||||
switch b {
|
||||
case C_ZAUTO, C_PSAUTO_8, C_PSAUTO_4:
|
||||
case C_ZAUTO, C_PSAUTO_16, C_PSAUTO_8, C_PSAUTO_4:
|
||||
return true
|
||||
}
|
||||
|
||||
case C_PPAUTO_16:
|
||||
switch b {
|
||||
case C_ZAUTO, C_PSAUTO_16:
|
||||
return true
|
||||
}
|
||||
|
||||
case C_PPAUTO:
|
||||
switch b {
|
||||
case C_ZAUTO, C_PSAUTO_8, C_PPAUTO_16:
|
||||
case C_ZAUTO, C_PSAUTO_16, C_PSAUTO_8, C_PPAUTO_16:
|
||||
return true
|
||||
}
|
||||
|
||||
case C_PQAUTO_16:
|
||||
switch b {
|
||||
case C_ZAUTO, C_PSAUTO_16, C_PPAUTO_16:
|
||||
return true
|
||||
}
|
||||
|
||||
case C_UAUTO4K:
|
||||
switch b {
|
||||
case C_ZAUTO, C_PSAUTO, C_PSAUTO_4, C_PSAUTO_8,
|
||||
C_PPAUTO, C_PPAUTO_16,
|
||||
case C_ZAUTO, C_PSAUTO, C_PSAUTO_4, C_PSAUTO_8, C_PSAUTO_16,
|
||||
C_PPAUTO, C_PPAUTO_16, C_PQAUTO_16,
|
||||
C_UAUTO4K_2, C_UAUTO4K_4, C_UAUTO4K_8, C_UAUTO4K_16:
|
||||
return true
|
||||
}
|
||||
|
||||
case C_UAUTO8K:
|
||||
switch b {
|
||||
case C_ZAUTO, C_PSAUTO, C_PSAUTO_4, C_PSAUTO_8,
|
||||
C_PPAUTO, C_PPAUTO_16,
|
||||
case C_ZAUTO, C_PSAUTO, C_PSAUTO_4, C_PSAUTO_8, C_PSAUTO_16,
|
||||
C_PPAUTO, C_PPAUTO_16, C_PQAUTO_16,
|
||||
C_UAUTO4K_2, C_UAUTO4K_4, C_UAUTO4K_8, C_UAUTO4K_16,
|
||||
C_UAUTO8K_4, C_UAUTO8K_8, C_UAUTO8K_16:
|
||||
return true
|
||||
@ -2258,8 +2315,8 @@ func cmp(a int, b int) bool {
|
||||
|
||||
case C_UAUTO16K:
|
||||
switch b {
|
||||
case C_ZAUTO, C_PSAUTO, C_PSAUTO_4, C_PSAUTO_8,
|
||||
C_PPAUTO, C_PPAUTO_16,
|
||||
case C_ZAUTO, C_PSAUTO, C_PSAUTO_4, C_PSAUTO_8, C_PSAUTO_16,
|
||||
C_PPAUTO, C_PPAUTO_16, C_PQAUTO_16,
|
||||
C_UAUTO4K_4, C_UAUTO4K_8, C_UAUTO4K_16,
|
||||
C_UAUTO8K_4, C_UAUTO8K_8, C_UAUTO8K_16,
|
||||
C_UAUTO16K_8, C_UAUTO16K_16:
|
||||
@ -2268,8 +2325,8 @@ func cmp(a int, b int) bool {
|
||||
|
||||
case C_UAUTO32K:
|
||||
switch b {
|
||||
case C_ZAUTO, C_PSAUTO, C_PSAUTO_4, C_PSAUTO_8,
|
||||
C_PPAUTO, C_PPAUTO_16,
|
||||
case C_ZAUTO, C_PSAUTO, C_PSAUTO_4, C_PSAUTO_8, C_PSAUTO_16,
|
||||
C_PPAUTO, C_PPAUTO_16, C_PQAUTO_16,
|
||||
C_UAUTO4K_8, C_UAUTO4K_16,
|
||||
C_UAUTO8K_8, C_UAUTO8K_16,
|
||||
C_UAUTO16K_8, C_UAUTO16K_16,
|
||||
@ -2279,17 +2336,17 @@ func cmp(a int, b int) bool {
|
||||
|
||||
case C_UAUTO64K:
|
||||
switch b {
|
||||
case C_ZAUTO, C_PSAUTO, C_PSAUTO_4, C_PSAUTO_8,
|
||||
C_PPAUTO_16, C_UAUTO4K_16, C_UAUTO8K_16, C_UAUTO16K_16,
|
||||
case C_ZAUTO, C_PSAUTO, C_PSAUTO_4, C_PSAUTO_8, C_PSAUTO_16,
|
||||
C_PPAUTO_16, C_PQAUTO_16, C_UAUTO4K_16, C_UAUTO8K_16, C_UAUTO16K_16,
|
||||
C_UAUTO32K_16:
|
||||
return true
|
||||
}
|
||||
|
||||
case C_LAUTO:
|
||||
switch b {
|
||||
case C_ZAUTO, C_NSAUTO, C_NSAUTO_4, C_NSAUTO_8, C_NPAUTO, C_NAUTO4K,
|
||||
C_PSAUTO, C_PSAUTO_4, C_PSAUTO_8,
|
||||
C_PPAUTO, C_PPAUTO_16,
|
||||
case C_ZAUTO, C_NSAUTO, C_NSAUTO_4, C_NSAUTO_8, C_NSAUTO_16, C_NPAUTO_16, C_NPAUTO, C_NQAUTO_16, C_NAUTO4K,
|
||||
C_PSAUTO, C_PSAUTO_4, C_PSAUTO_8, C_PSAUTO_16,
|
||||
C_PPAUTO, C_PPAUTO_16, C_PQAUTO_16,
|
||||
C_UAUTO4K, C_UAUTO4K_2, C_UAUTO4K_4, C_UAUTO4K_8, C_UAUTO4K_16,
|
||||
C_UAUTO8K, C_UAUTO8K_4, C_UAUTO8K_8, C_UAUTO8K_16,
|
||||
C_UAUTO16K, C_UAUTO16K_8, C_UAUTO16K_16,
|
||||
@ -2298,64 +2355,98 @@ func cmp(a int, b int) bool {
|
||||
return true
|
||||
}
|
||||
|
||||
case C_NSOREG_8:
|
||||
if b == C_NSOREG_16 {
|
||||
return true
|
||||
}
|
||||
|
||||
case C_NSOREG_4:
|
||||
if b == C_NSOREG_8 {
|
||||
if b == C_NSOREG_8 || b == C_NSOREG_16 {
|
||||
return true
|
||||
}
|
||||
|
||||
case C_NSOREG:
|
||||
switch b {
|
||||
case C_NSOREG_4, C_NSOREG_8:
|
||||
case C_NSOREG_4, C_NSOREG_8, C_NSOREG_16:
|
||||
return true
|
||||
}
|
||||
|
||||
case C_NPOREG_16:
|
||||
switch b {
|
||||
case C_NSOREG_16:
|
||||
return true
|
||||
}
|
||||
|
||||
case C_NPOREG:
|
||||
switch b {
|
||||
case C_NSOREG_8:
|
||||
case C_NSOREG_16, C_NSOREG_8, C_NPOREG_16:
|
||||
return true
|
||||
}
|
||||
|
||||
case C_NQOREG_16:
|
||||
switch b {
|
||||
case C_NSOREG_16, C_NPOREG_16:
|
||||
return true
|
||||
}
|
||||
|
||||
case C_NOREG4K:
|
||||
switch b {
|
||||
case C_NSOREG_8, C_NSOREG_4, C_NSOREG, C_NPOREG:
|
||||
case C_NSOREG_16, C_NSOREG_8, C_NSOREG_4, C_NSOREG, C_NPOREG_16, C_NPOREG, C_NQOREG_16:
|
||||
return true
|
||||
}
|
||||
|
||||
case C_PSOREG_16:
|
||||
if b == C_ZOREG {
|
||||
return true
|
||||
}
|
||||
|
||||
case C_PSOREG_8:
|
||||
if b == C_ZOREG {
|
||||
if b == C_ZOREG || b == C_PSOREG_16 {
|
||||
return true
|
||||
}
|
||||
|
||||
case C_PSOREG_4:
|
||||
switch b {
|
||||
case C_ZOREG, C_PSOREG_8:
|
||||
case C_ZOREG, C_PSOREG_16, C_PSOREG_8:
|
||||
return true
|
||||
}
|
||||
|
||||
case C_PSOREG:
|
||||
switch b {
|
||||
case C_ZOREG, C_PSOREG_8, C_PSOREG_4:
|
||||
case C_ZOREG, C_PSOREG_16, C_PSOREG_8, C_PSOREG_4:
|
||||
return true
|
||||
}
|
||||
|
||||
case C_PPOREG_16:
|
||||
switch b {
|
||||
case C_ZOREG, C_PSOREG_16:
|
||||
return true
|
||||
}
|
||||
|
||||
case C_PPOREG:
|
||||
switch b {
|
||||
case C_ZOREG, C_PSOREG_8, C_PPOREG_16:
|
||||
case C_ZOREG, C_PSOREG_16, C_PSOREG_8, C_PPOREG_16:
|
||||
return true
|
||||
}
|
||||
|
||||
case C_PQOREG_16:
|
||||
switch b {
|
||||
case C_ZOREG, C_PSOREG_16, C_PPOREG_16:
|
||||
return true
|
||||
}
|
||||
|
||||
case C_UOREG4K:
|
||||
switch b {
|
||||
case C_ZOREG, C_PSOREG, C_PSOREG_4, C_PSOREG_8,
|
||||
C_PPOREG, C_PPOREG_16,
|
||||
case C_ZOREG, C_PSOREG, C_PSOREG_4, C_PSOREG_8, C_PSOREG_16,
|
||||
C_PPOREG, C_PPOREG_16, C_PQOREG_16,
|
||||
C_UOREG4K_2, C_UOREG4K_4, C_UOREG4K_8, C_UOREG4K_16:
|
||||
return true
|
||||
}
|
||||
|
||||
case C_UOREG8K:
|
||||
switch b {
|
||||
case C_ZOREG, C_PSOREG, C_PSOREG_4, C_PSOREG_8,
|
||||
C_PPOREG, C_PPOREG_16,
|
||||
case C_ZOREG, C_PSOREG, C_PSOREG_4, C_PSOREG_8, C_PSOREG_16,
|
||||
C_PPOREG, C_PPOREG_16, C_PQOREG_16,
|
||||
C_UOREG4K_2, C_UOREG4K_4, C_UOREG4K_8, C_UOREG4K_16,
|
||||
C_UOREG8K_4, C_UOREG8K_8, C_UOREG8K_16:
|
||||
return true
|
||||
@ -2363,8 +2454,8 @@ func cmp(a int, b int) bool {
|
||||
|
||||
case C_UOREG16K:
|
||||
switch b {
|
||||
case C_ZOREG, C_PSOREG, C_PSOREG_4, C_PSOREG_8,
|
||||
C_PPOREG, C_PPOREG_16,
|
||||
case C_ZOREG, C_PSOREG, C_PSOREG_4, C_PSOREG_8, C_PSOREG_16,
|
||||
C_PPOREG, C_PPOREG_16, C_PQOREG_16,
|
||||
C_UOREG4K_4, C_UOREG4K_8, C_UOREG4K_16,
|
||||
C_UOREG8K_4, C_UOREG8K_8, C_UOREG8K_16,
|
||||
C_UOREG16K_8, C_UOREG16K_16:
|
||||
@ -2373,8 +2464,8 @@ func cmp(a int, b int) bool {
|
||||
|
||||
case C_UOREG32K:
|
||||
switch b {
|
||||
case C_ZOREG, C_PSOREG, C_PSOREG_4, C_PSOREG_8,
|
||||
C_PPOREG, C_PPOREG_16,
|
||||
case C_ZOREG, C_PSOREG, C_PSOREG_4, C_PSOREG_8, C_PSOREG_16,
|
||||
C_PPOREG, C_PPOREG_16, C_PQOREG_16,
|
||||
C_UOREG4K_8, C_UOREG4K_16,
|
||||
C_UOREG8K_8, C_UOREG8K_16,
|
||||
C_UOREG16K_8, C_UOREG16K_16,
|
||||
@ -2384,17 +2475,17 @@ func cmp(a int, b int) bool {
|
||||
|
||||
case C_UOREG64K:
|
||||
switch b {
|
||||
case C_ZOREG, C_PSOREG, C_PSOREG_4, C_PSOREG_8,
|
||||
C_PPOREG_16, C_UOREG4K_16, C_UOREG8K_16, C_UOREG16K_16,
|
||||
case C_ZOREG, C_PSOREG, C_PSOREG_4, C_PSOREG_8, C_PSOREG_16,
|
||||
C_PPOREG_16, C_PQOREG_16, C_UOREG4K_16, C_UOREG8K_16, C_UOREG16K_16,
|
||||
C_UOREG32K_16:
|
||||
return true
|
||||
}
|
||||
|
||||
case C_LOREG:
|
||||
switch b {
|
||||
case C_ZOREG, C_NSOREG, C_NSOREG_4, C_NSOREG_8, C_NPOREG, C_NOREG4K,
|
||||
C_PSOREG, C_PSOREG_4, C_PSOREG_8,
|
||||
C_PPOREG, C_PPOREG_16,
|
||||
case C_ZOREG, C_NSOREG, C_NSOREG_4, C_NSOREG_8, C_NSOREG_16, C_NPOREG, C_NPOREG_16, C_NQOREG_16, C_NOREG4K,
|
||||
C_PSOREG, C_PSOREG_4, C_PSOREG_8, C_PSOREG_16,
|
||||
C_PPOREG, C_PPOREG_16, C_PQOREG_16,
|
||||
C_UOREG4K, C_UOREG4K_2, C_UOREG4K_4, C_UOREG4K_8, C_UOREG4K_16,
|
||||
C_UOREG8K, C_UOREG8K_4, C_UOREG8K_8, C_UOREG8K_16,
|
||||
C_UOREG16K, C_UOREG16K_8, C_UOREG16K_16,
|
||||
@ -2722,6 +2813,10 @@ func buildop(ctxt *obj.Link) {
|
||||
obj.ATEXT:
|
||||
break
|
||||
|
||||
case AFLDPQ:
|
||||
break
|
||||
case AFSTPQ:
|
||||
break
|
||||
case ALDP:
|
||||
oprangeset(AFLDPD, t)
|
||||
|
||||
@ -7192,7 +7287,7 @@ func (c *ctxt7) opextr(p *obj.Prog, a obj.As, v int32, rn int, rm int, rt int) u
|
||||
return o
|
||||
}
|
||||
|
||||
/* genrate instruction encoding for LDP/LDPW/LDPSW/STP/STPW */
|
||||
/* genrate instruction encoding for ldp and stp series */
|
||||
func (c *ctxt7) opldpstp(p *obj.Prog, o *Optab, vo int32, rbase, rl, rh, ldp uint32) uint32 {
|
||||
wback := false
|
||||
if o.scond == C_XPOST || o.scond == C_XPRE {
|
||||
@ -7205,30 +7300,36 @@ func (c *ctxt7) opldpstp(p *obj.Prog, o *Optab, vo int32, rbase, rl, rh, ldp uin
|
||||
if wback == true {
|
||||
c.checkUnpredictable(p, false, true, p.To.Reg, p.From.Reg, int16(p.From.Offset))
|
||||
}
|
||||
case AFLDPD, AFLDPS:
|
||||
case AFLDPD, AFLDPQ, AFLDPS:
|
||||
c.checkUnpredictable(p, true, false, p.From.Reg, p.To.Reg, int16(p.To.Offset))
|
||||
}
|
||||
var ret uint32
|
||||
// check offset
|
||||
switch p.As {
|
||||
case AFLDPQ, AFSTPQ:
|
||||
if vo < -1024 || vo > 1008 || vo%16 != 0 {
|
||||
c.ctxt.Diag("invalid offset %v\n", p)
|
||||
}
|
||||
vo /= 16
|
||||
ret = 2<<30 | 1<<26
|
||||
case AFLDPD, AFSTPD:
|
||||
if vo < -512 || vo > 504 || vo%8 != 0 {
|
||||
c.ctxt.Diag("invalid offset %v\n", p)
|
||||
}
|
||||
vo /= 8
|
||||
ret = 1<<30 | 1<<26
|
||||
case ALDP, ASTP:
|
||||
if vo < -512 || vo > 504 || vo%8 != 0 {
|
||||
c.ctxt.Diag("invalid offset %v\n", p)
|
||||
}
|
||||
vo /= 8
|
||||
ret = 2 << 30
|
||||
case AFLDPS, AFSTPS:
|
||||
if vo < -256 || vo > 252 || vo%4 != 0 {
|
||||
c.ctxt.Diag("invalid offset %v\n", p)
|
||||
}
|
||||
vo /= 4
|
||||
ret = 1 << 26
|
||||
case ALDP, ASTP:
|
||||
if vo < -512 || vo > 504 || vo%8 != 0 {
|
||||
c.ctxt.Diag("invalid offset %v\n", p)
|
||||
}
|
||||
vo /= 8
|
||||
ret = 2 << 30
|
||||
case ALDPW, ASTPW:
|
||||
if vo < -256 || vo > 252 || vo%4 != 0 {
|
||||
c.ctxt.Diag("invalid offset %v\n", p)
|
||||
@ -7246,7 +7347,7 @@ func (c *ctxt7) opldpstp(p *obj.Prog, o *Optab, vo int32, rbase, rl, rh, ldp uin
|
||||
}
|
||||
// check register pair
|
||||
switch p.As {
|
||||
case AFLDPD, AFLDPS, AFSTPD, AFSTPS:
|
||||
case AFLDPQ, AFLDPD, AFLDPS, AFSTPQ, AFSTPD, AFSTPS:
|
||||
if rl < REG_F0 || REG_F31 < rl || rh < REG_F0 || REG_F31 < rh {
|
||||
c.ctxt.Diag("invalid register pair %v\n", p)
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user