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cmd/compile: intrinsify runtime/internal/atomic.{And,Or} on MIPS64x
This CL intrinsify atomic{And,Or} on mips64x, which already implemented on mipsx.
goos: linux
goarch: mips64le
pkg: runtime/internal/atomic
_ oldatomic _ newatomic _
_ sec/op _ sec/op vs base _
AtomicLoad64-4 27.96n _ 0% 28.02n _ 0% +0.20% (p=0.026 n=8)
AtomicStore64-4 29.14n _ 0% 29.21n _ 0% +0.22% (p=0.004 n=8)
AtomicLoad-4 27.96n _ 0% 28.02n _ 0% ~ (p=0.220 n=8)
AtomicStore-4 29.15n _ 0% 29.21n _ 0% +0.19% (p=0.002 n=8)
And8-4 53.09n _ 0% 41.71n _ 0% -21.44% (p=0.000 n=8)
And-4 49.87n _ 0% 39.93n _ 0% -19.93% (p=0.000 n=8)
And8Parallel-4 70.45n _ 0% 68.58n _ 0% -2.65% (p=0.000 n=8)
AndParallel-4 70.40n _ 0% 67.95n _ 0% -3.47% (p=0.000 n=8)
Or8-4 52.09n _ 0% 41.11n _ 0% -21.08% (p=0.000 n=8)
Or-4 49.80n _ 0% 39.87n _ 0% -19.93% (p=0.000 n=8)
Or8Parallel-4 70.43n _ 0% 68.25n _ 0% -3.08% (p=0.000 n=8)
OrParallel-4 70.42n _ 0% 67.94n _ 0% -3.51% (p=0.000 n=8)
Xadd-4 67.83n _ 0% 67.92n _ 0% +0.13% (p=0.003 n=8)
Xadd64-4 67.85n _ 0% 67.92n _ 0% +0.09% (p=0.021 n=8)
Cas-4 81.34n _ 0% 81.37n _ 0% ~ (p=0.859 n=8)
Cas64-4 81.43n _ 0% 81.53n _ 0% +0.13% (p=0.001 n=8)
Xchg-4 67.15n _ 0% 67.18n _ 0% ~ (p=0.367 n=8)
Xchg64-4 67.16n _ 0% 67.21n _ 0% +0.08% (p=0.008 n=8)
geomean 54.04n 51.01n -5.61%
Change-Id: I9a4353f4b14134f1e9cf0dcf99db3feb951328ed
Reviewed-on: https://go-review.googlesource.com/c/go/+/494875
Reviewed-by: Cherry Mui <cherryyz@google.com>
Reviewed-by: Keith Randall <khr@golang.org>
Reviewed-by: Keith Randall <khr@google.com>
Run-TryBot: Joel Sing <joel@sing.id.au>
Reviewed-by: Junxian Zhu <zhujunxian@oss.cipunited.com>
TryBot-Result: Gopher Robot <gobot@golang.org>
This commit is contained in:
Junxian Zhu
Joel Sing
parent
774f60223f
commit
75add1ce0e
@ -672,6 +672,43 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
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p4.Reg = v.Reg0()
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p4.To.Type = obj.TYPE_REG
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p4.To.Reg = v.Reg0()
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case ssa.OpMIPS64LoweredAtomicAnd32,
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ssa.OpMIPS64LoweredAtomicOr32:
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// SYNC
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// LL (Rarg0), Rtmp
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// AND/OR Rarg1, Rtmp
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// SC Rtmp, (Rarg0)
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// BEQ Rtmp, -3(PC)
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// SYNC
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s.Prog(mips.ASYNC)
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p := s.Prog(mips.ALL)
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = v.Args[0].Reg()
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p.To.Type = obj.TYPE_REG
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p.To.Reg = mips.REGTMP
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p1 := s.Prog(v.Op.Asm())
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p1.From.Type = obj.TYPE_REG
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p1.From.Reg = v.Args[1].Reg()
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p1.Reg = mips.REGTMP
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p1.To.Type = obj.TYPE_REG
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p1.To.Reg = mips.REGTMP
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p2 := s.Prog(mips.ASC)
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p2.From.Type = obj.TYPE_REG
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p2.From.Reg = mips.REGTMP
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p2.To.Type = obj.TYPE_MEM
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p2.To.Reg = v.Args[0].Reg()
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p3 := s.Prog(mips.ABEQ)
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p3.From.Type = obj.TYPE_REG
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p3.From.Reg = mips.REGTMP
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p3.To.Type = obj.TYPE_BRANCH
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p3.To.SetTarget(p)
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s.Prog(mips.ASYNC)
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case ssa.OpMIPS64LoweredAtomicCas32, ssa.OpMIPS64LoweredAtomicCas64:
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// MOVV $0, Rout
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// SYNC
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@ -399,6 +399,46 @@
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(AtomicCompareAndSwap32 ptr old new mem) => (LoweredAtomicCas32 ptr (SignExt32to64 old) new mem)
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(AtomicCompareAndSwap64 ...) => (LoweredAtomicCas64 ...)
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// AtomicOr8(ptr,val) => LoweredAtomicOr32(ptr&^3,uint32(val) << ((ptr & 3) * 8))
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(AtomicOr8 ptr val mem) && !config.BigEndian =>
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(LoweredAtomicOr32 (AND <typ.UInt32Ptr> (MOVVconst [^3]) ptr)
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(SLLV <typ.UInt32> (ZeroExt8to32 val)
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(SLLVconst <typ.UInt64> [3]
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(ANDconst <typ.UInt64> [3] ptr))) mem)
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// AtomicAnd8(ptr,val) => LoweredAtomicAnd32(ptr&^3,(uint32(val) << ((ptr & 3) * 8)) | ^(uint32(0xFF) << ((ptr & 3) * 8))))
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(AtomicAnd8 ptr val mem) && !config.BigEndian =>
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(LoweredAtomicAnd32 (AND <typ.UInt32Ptr> (MOVVconst [^3]) ptr)
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(OR <typ.UInt64> (SLLV <typ.UInt32> (ZeroExt8to32 val)
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(SLLVconst <typ.UInt64> [3]
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(ANDconst <typ.UInt64> [3] ptr)))
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(NORconst [0] <typ.UInt64> (SLLV <typ.UInt64>
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(MOVVconst [0xff]) (SLLVconst <typ.UInt64> [3]
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(ANDconst <typ.UInt64> [3] ptr))))) mem)
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// AtomicOr8(ptr,val) => LoweredAtomicOr32(ptr&^3,uint32(val) << (((ptr^3) & 3) * 8))
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(AtomicOr8 ptr val mem) && config.BigEndian =>
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(LoweredAtomicOr32 (AND <typ.UInt32Ptr> (MOVVconst [^3]) ptr)
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(SLLV <typ.UInt32> (ZeroExt8to32 val)
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(SLLVconst <typ.UInt64> [3]
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(ANDconst <typ.UInt64> [3]
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(XORconst <typ.UInt64> [3] ptr)))) mem)
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// AtomicAnd8(ptr,val) => LoweredAtomicAnd32(ptr&^3,(uint32(val) << (((ptr^3) & 3) * 8)) | ^(uint32(0xFF) << (((ptr^3) & 3) * 8))))
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(AtomicAnd8 ptr val mem) && config.BigEndian =>
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(LoweredAtomicAnd32 (AND <typ.UInt32Ptr> (MOVVconst [^3]) ptr)
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(OR <typ.UInt64> (SLLV <typ.UInt32> (ZeroExt8to32 val)
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(SLLVconst <typ.UInt64> [3]
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(ANDconst <typ.UInt64> [3]
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(XORconst <typ.UInt64> [3] ptr))))
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(NORconst [0] <typ.UInt64> (SLLV <typ.UInt64>
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(MOVVconst [0xff]) (SLLVconst <typ.UInt64> [3]
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(ANDconst <typ.UInt64> [3]
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(XORconst <typ.UInt64> [3] ptr)))))) mem)
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(AtomicAnd32 ...) => (LoweredAtomicAnd32 ...)
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(AtomicOr32 ...) => (LoweredAtomicOr32 ...)
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// checks
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(NilCheck ...) => (LoweredNilCheck ...)
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(IsNonNil ptr) => (SGTU ptr (MOVVconst [0]))
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@ -361,6 +361,17 @@ func init() {
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faultOnNilArg1: true,
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},
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// atomic and/or.
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// *arg0 &= (|=) arg1. arg2=mem. returns memory.
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// SYNC
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// LL (Rarg0), Rtmp
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// AND Rarg1, Rtmp
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// SC Rtmp, (Rarg0)
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// BEQ Rtmp, -3(PC)
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// SYNC
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{name: "LoweredAtomicAnd32", argLength: 3, reg: gpstore, asm: "AND", faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
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{name: "LoweredAtomicOr32", argLength: 3, reg: gpstore, asm: "OR", faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
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// atomic loads.
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// load from arg0. arg1=mem.
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// returns <value,memory> so they can be properly ordered with other loads.
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@ -2053,6 +2053,8 @@ const (
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OpMIPS64DUFFCOPY
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OpMIPS64LoweredZero
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OpMIPS64LoweredMove
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OpMIPS64LoweredAtomicAnd32
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OpMIPS64LoweredAtomicOr32
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OpMIPS64LoweredAtomicLoad8
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OpMIPS64LoweredAtomicLoad32
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OpMIPS64LoweredAtomicLoad64
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@ -27484,6 +27486,34 @@ var opcodeTable = [...]opInfo{
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clobbers: 6, // R1 R2
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},
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},
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{
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name: "LoweredAtomicAnd32",
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argLen: 3,
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faultOnNilArg0: true,
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hasSideEffects: true,
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unsafePoint: true,
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asm: mips.AAND,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
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{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
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},
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},
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},
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{
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name: "LoweredAtomicOr32",
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argLen: 3,
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faultOnNilArg0: true,
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hasSideEffects: true,
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unsafePoint: true,
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asm: mips.AOR,
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reg: regInfo{
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inputs: []inputInfo{
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{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
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{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
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},
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},
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},
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{
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name: "LoweredAtomicLoad8",
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argLen: 2,
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@ -53,6 +53,11 @@ func rewriteValueMIPS64(v *Value) bool {
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case OpAtomicAdd64:
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v.Op = OpMIPS64LoweredAtomicAdd64
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return true
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case OpAtomicAnd32:
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v.Op = OpMIPS64LoweredAtomicAnd32
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return true
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case OpAtomicAnd8:
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return rewriteValueMIPS64_OpAtomicAnd8(v)
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case OpAtomicCompareAndSwap32:
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return rewriteValueMIPS64_OpAtomicCompareAndSwap32(v)
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case OpAtomicCompareAndSwap64:
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@ -76,6 +81,11 @@ func rewriteValueMIPS64(v *Value) bool {
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case OpAtomicLoadPtr:
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v.Op = OpMIPS64LoweredAtomicLoad64
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return true
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case OpAtomicOr32:
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v.Op = OpMIPS64LoweredAtomicOr32
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return true
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case OpAtomicOr8:
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return rewriteValueMIPS64_OpAtomicOr8(v)
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case OpAtomicStore32:
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v.Op = OpMIPS64LoweredAtomicStore32
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return true
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@ -698,6 +708,92 @@ func rewriteValueMIPS64_OpAddr(v *Value) bool {
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return true
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}
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}
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func rewriteValueMIPS64_OpAtomicAnd8(v *Value) bool {
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v_2 := v.Args[2]
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v_1 := v.Args[1]
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v_0 := v.Args[0]
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b := v.Block
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config := b.Func.Config
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typ := &b.Func.Config.Types
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// match: (AtomicAnd8 ptr val mem)
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// cond: !config.BigEndian
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// result: (LoweredAtomicAnd32 (AND <typ.UInt32Ptr> (MOVVconst [^3]) ptr) (OR <typ.UInt64> (SLLV <typ.UInt32> (ZeroExt8to32 val) (SLLVconst <typ.UInt64> [3] (ANDconst <typ.UInt64> [3] ptr))) (NORconst [0] <typ.UInt64> (SLLV <typ.UInt64> (MOVVconst [0xff]) (SLLVconst <typ.UInt64> [3] (ANDconst <typ.UInt64> [3] ptr))))) mem)
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for {
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ptr := v_0
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val := v_1
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mem := v_2
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if !(!config.BigEndian) {
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break
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}
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v.reset(OpMIPS64LoweredAtomicAnd32)
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v0 := b.NewValue0(v.Pos, OpMIPS64AND, typ.UInt32Ptr)
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v1 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
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v1.AuxInt = int64ToAuxInt(^3)
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v0.AddArg2(v1, ptr)
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v2 := b.NewValue0(v.Pos, OpMIPS64OR, typ.UInt64)
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v3 := b.NewValue0(v.Pos, OpMIPS64SLLV, typ.UInt32)
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v4 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
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v4.AddArg(val)
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v5 := b.NewValue0(v.Pos, OpMIPS64SLLVconst, typ.UInt64)
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v5.AuxInt = int64ToAuxInt(3)
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v6 := b.NewValue0(v.Pos, OpMIPS64ANDconst, typ.UInt64)
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v6.AuxInt = int64ToAuxInt(3)
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v6.AddArg(ptr)
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v5.AddArg(v6)
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v3.AddArg2(v4, v5)
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v7 := b.NewValue0(v.Pos, OpMIPS64NORconst, typ.UInt64)
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v7.AuxInt = int64ToAuxInt(0)
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v8 := b.NewValue0(v.Pos, OpMIPS64SLLV, typ.UInt64)
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v9 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
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v9.AuxInt = int64ToAuxInt(0xff)
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v8.AddArg2(v9, v5)
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v7.AddArg(v8)
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v2.AddArg2(v3, v7)
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v.AddArg3(v0, v2, mem)
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return true
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}
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// match: (AtomicAnd8 ptr val mem)
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// cond: config.BigEndian
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// result: (LoweredAtomicAnd32 (AND <typ.UInt32Ptr> (MOVVconst [^3]) ptr) (OR <typ.UInt64> (SLLV <typ.UInt32> (ZeroExt8to32 val) (SLLVconst <typ.UInt64> [3] (ANDconst <typ.UInt64> [3] (XORconst <typ.UInt64> [3] ptr)))) (NORconst [0] <typ.UInt64> (SLLV <typ.UInt64> (MOVVconst [0xff]) (SLLVconst <typ.UInt64> [3] (ANDconst <typ.UInt64> [3] (XORconst <typ.UInt64> [3] ptr)))))) mem)
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for {
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ptr := v_0
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val := v_1
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mem := v_2
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if !(config.BigEndian) {
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break
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}
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v.reset(OpMIPS64LoweredAtomicAnd32)
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v0 := b.NewValue0(v.Pos, OpMIPS64AND, typ.UInt32Ptr)
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v1 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
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v1.AuxInt = int64ToAuxInt(^3)
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v0.AddArg2(v1, ptr)
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v2 := b.NewValue0(v.Pos, OpMIPS64OR, typ.UInt64)
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v3 := b.NewValue0(v.Pos, OpMIPS64SLLV, typ.UInt32)
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v4 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
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v4.AddArg(val)
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v5 := b.NewValue0(v.Pos, OpMIPS64SLLVconst, typ.UInt64)
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v5.AuxInt = int64ToAuxInt(3)
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v6 := b.NewValue0(v.Pos, OpMIPS64ANDconst, typ.UInt64)
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v6.AuxInt = int64ToAuxInt(3)
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v7 := b.NewValue0(v.Pos, OpMIPS64XORconst, typ.UInt64)
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v7.AuxInt = int64ToAuxInt(3)
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v7.AddArg(ptr)
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v6.AddArg(v7)
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v5.AddArg(v6)
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v3.AddArg2(v4, v5)
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v8 := b.NewValue0(v.Pos, OpMIPS64NORconst, typ.UInt64)
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v8.AuxInt = int64ToAuxInt(0)
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v9 := b.NewValue0(v.Pos, OpMIPS64SLLV, typ.UInt64)
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v10 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
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v10.AuxInt = int64ToAuxInt(0xff)
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v9.AddArg2(v10, v5)
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v8.AddArg(v9)
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v2.AddArg2(v3, v8)
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v.AddArg3(v0, v2, mem)
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return true
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}
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return false
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}
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func rewriteValueMIPS64_OpAtomicCompareAndSwap32(v *Value) bool {
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v_3 := v.Args[3]
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v_2 := v.Args[2]
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@ -719,6 +815,74 @@ func rewriteValueMIPS64_OpAtomicCompareAndSwap32(v *Value) bool {
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return true
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}
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}
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func rewriteValueMIPS64_OpAtomicOr8(v *Value) bool {
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v_2 := v.Args[2]
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v_1 := v.Args[1]
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v_0 := v.Args[0]
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b := v.Block
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config := b.Func.Config
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typ := &b.Func.Config.Types
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// match: (AtomicOr8 ptr val mem)
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// cond: !config.BigEndian
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// result: (LoweredAtomicOr32 (AND <typ.UInt32Ptr> (MOVVconst [^3]) ptr) (SLLV <typ.UInt32> (ZeroExt8to32 val) (SLLVconst <typ.UInt64> [3] (ANDconst <typ.UInt64> [3] ptr))) mem)
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for {
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ptr := v_0
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val := v_1
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mem := v_2
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if !(!config.BigEndian) {
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break
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}
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v.reset(OpMIPS64LoweredAtomicOr32)
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v0 := b.NewValue0(v.Pos, OpMIPS64AND, typ.UInt32Ptr)
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v1 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
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v1.AuxInt = int64ToAuxInt(^3)
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v0.AddArg2(v1, ptr)
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v2 := b.NewValue0(v.Pos, OpMIPS64SLLV, typ.UInt32)
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v3 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
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v3.AddArg(val)
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v4 := b.NewValue0(v.Pos, OpMIPS64SLLVconst, typ.UInt64)
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v4.AuxInt = int64ToAuxInt(3)
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v5 := b.NewValue0(v.Pos, OpMIPS64ANDconst, typ.UInt64)
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v5.AuxInt = int64ToAuxInt(3)
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v5.AddArg(ptr)
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v4.AddArg(v5)
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v2.AddArg2(v3, v4)
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v.AddArg3(v0, v2, mem)
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return true
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}
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// match: (AtomicOr8 ptr val mem)
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// cond: config.BigEndian
|
||||
// result: (LoweredAtomicOr32 (AND <typ.UInt32Ptr> (MOVVconst [^3]) ptr) (SLLV <typ.UInt32> (ZeroExt8to32 val) (SLLVconst <typ.UInt64> [3] (ANDconst <typ.UInt64> [3] (XORconst <typ.UInt64> [3] ptr)))) mem)
|
||||
for {
|
||||
ptr := v_0
|
||||
val := v_1
|
||||
mem := v_2
|
||||
if !(config.BigEndian) {
|
||||
break
|
||||
}
|
||||
v.reset(OpMIPS64LoweredAtomicOr32)
|
||||
v0 := b.NewValue0(v.Pos, OpMIPS64AND, typ.UInt32Ptr)
|
||||
v1 := b.NewValue0(v.Pos, OpMIPS64MOVVconst, typ.UInt64)
|
||||
v1.AuxInt = int64ToAuxInt(^3)
|
||||
v0.AddArg2(v1, ptr)
|
||||
v2 := b.NewValue0(v.Pos, OpMIPS64SLLV, typ.UInt32)
|
||||
v3 := b.NewValue0(v.Pos, OpZeroExt8to32, typ.UInt32)
|
||||
v3.AddArg(val)
|
||||
v4 := b.NewValue0(v.Pos, OpMIPS64SLLVconst, typ.UInt64)
|
||||
v4.AuxInt = int64ToAuxInt(3)
|
||||
v5 := b.NewValue0(v.Pos, OpMIPS64ANDconst, typ.UInt64)
|
||||
v5.AuxInt = int64ToAuxInt(3)
|
||||
v6 := b.NewValue0(v.Pos, OpMIPS64XORconst, typ.UInt64)
|
||||
v6.AuxInt = int64ToAuxInt(3)
|
||||
v6.AddArg(ptr)
|
||||
v5.AddArg(v6)
|
||||
v4.AddArg(v5)
|
||||
v2.AddArg2(v3, v4)
|
||||
v.AddArg3(v0, v2, mem)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValueMIPS64_OpAvg64u(v *Value) bool {
|
||||
v_1 := v.Args[1]
|
||||
v_0 := v.Args[0]
|
||||
|
||||
@ -4250,25 +4250,25 @@ func InitTables() {
|
||||
s.vars[memVar] = s.newValue3(ssa.OpAtomicAnd8, types.TypeMem, args[0], args[1], s.mem())
|
||||
return nil
|
||||
},
|
||||
sys.AMD64, sys.MIPS, sys.PPC64, sys.RISCV64, sys.S390X)
|
||||
sys.AMD64, sys.MIPS, sys.MIPS64, sys.PPC64, sys.RISCV64, sys.S390X)
|
||||
addF("runtime/internal/atomic", "And",
|
||||
func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
|
||||
s.vars[memVar] = s.newValue3(ssa.OpAtomicAnd32, types.TypeMem, args[0], args[1], s.mem())
|
||||
return nil
|
||||
},
|
||||
sys.AMD64, sys.MIPS, sys.PPC64, sys.RISCV64, sys.S390X)
|
||||
sys.AMD64, sys.MIPS, sys.MIPS64, sys.PPC64, sys.RISCV64, sys.S390X)
|
||||
addF("runtime/internal/atomic", "Or8",
|
||||
func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
|
||||
s.vars[memVar] = s.newValue3(ssa.OpAtomicOr8, types.TypeMem, args[0], args[1], s.mem())
|
||||
return nil
|
||||
},
|
||||
sys.AMD64, sys.ARM64, sys.MIPS, sys.PPC64, sys.RISCV64, sys.S390X)
|
||||
sys.AMD64, sys.ARM64, sys.MIPS, sys.MIPS64, sys.PPC64, sys.RISCV64, sys.S390X)
|
||||
addF("runtime/internal/atomic", "Or",
|
||||
func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value {
|
||||
s.vars[memVar] = s.newValue3(ssa.OpAtomicOr32, types.TypeMem, args[0], args[1], s.mem())
|
||||
return nil
|
||||
},
|
||||
sys.AMD64, sys.MIPS, sys.PPC64, sys.RISCV64, sys.S390X)
|
||||
sys.AMD64, sys.MIPS, sys.MIPS64, sys.PPC64, sys.RISCV64, sys.S390X)
|
||||
|
||||
atomicAndOrEmitterARM64 := func(s *state, n *ir.CallExpr, args []*ssa.Value, op ssa.Op, typ types.Kind) {
|
||||
s.vars[memVar] = s.newValue3(op, types.TypeMem, args[0], args[1], s.mem())
|
||||
|
||||
Loading…
Reference in New Issue
Block a user