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cmd/compile: add AMD64 parameter register defs, Arg ops, plumb to ssa.Config
This is partial plumbing recycled from the original register abi test work; these are the parts that translate easily. Some other bits are deferred till later when they are ready to be used. For #40724. Change-Id: Ica8c55a4526793446189725a2bc3839124feb38f Reviewed-on: https://go-review.googlesource.com/c/go/+/260539 Trust: David Chase <drchase@google.com> Reviewed-by: Cherry Zhang <cherryyz@google.com>
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@ -5,6 +5,7 @@
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package ssa
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import (
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"cmd/compile/internal/abi"
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"cmd/compile/internal/base"
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"cmd/compile/internal/ir"
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"cmd/compile/internal/types"
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@ -21,29 +22,33 @@ type Config struct {
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PtrSize int64 // 4 or 8; copy of cmd/internal/sys.Arch.PtrSize
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RegSize int64 // 4 or 8; copy of cmd/internal/sys.Arch.RegSize
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Types Types
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lowerBlock blockRewriter // lowering function
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lowerValue valueRewriter // lowering function
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splitLoad valueRewriter // function for splitting merged load ops; only used on some architectures
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registers []Register // machine registers
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gpRegMask regMask // general purpose integer register mask
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fpRegMask regMask // floating point register mask
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fp32RegMask regMask // floating point register mask
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fp64RegMask regMask // floating point register mask
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specialRegMask regMask // special register mask
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GCRegMap []*Register // garbage collector register map, by GC register index
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FPReg int8 // register number of frame pointer, -1 if not used
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LinkReg int8 // register number of link register if it is a general purpose register, -1 if not used
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hasGReg bool // has hardware g register
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ctxt *obj.Link // Generic arch information
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optimize bool // Do optimization
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noDuffDevice bool // Don't use Duff's device
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useSSE bool // Use SSE for non-float operations
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useAvg bool // Use optimizations that need Avg* operations
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useHmul bool // Use optimizations that need Hmul* operations
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SoftFloat bool //
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Race bool // race detector enabled
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BigEndian bool //
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UseFMA bool // Use hardware FMA operation
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lowerBlock blockRewriter // lowering function
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lowerValue valueRewriter // lowering function
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splitLoad valueRewriter // function for splitting merged load ops; only used on some architectures
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registers []Register // machine registers
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gpRegMask regMask // general purpose integer register mask
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fpRegMask regMask // floating point register mask
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fp32RegMask regMask // floating point register mask
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fp64RegMask regMask // floating point register mask
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specialRegMask regMask // special register mask
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intParamRegs []int8 // register numbers of integer param (in/out) registers
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floatParamRegs []int8 // register numbers of floating param (in/out) registers
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ABI1 *abi.ABIConfig // "ABIInternal" under development // TODO change comment when this becomes current
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ABI0 *abi.ABIConfig
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GCRegMap []*Register // garbage collector register map, by GC register index
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FPReg int8 // register number of frame pointer, -1 if not used
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LinkReg int8 // register number of link register if it is a general purpose register, -1 if not used
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hasGReg bool // has hardware g register
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ctxt *obj.Link // Generic arch information
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optimize bool // Do optimization
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noDuffDevice bool // Don't use Duff's device
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useSSE bool // Use SSE for non-float operations
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useAvg bool // Use optimizations that need Avg* operations
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useHmul bool // Use optimizations that need Hmul* operations
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SoftFloat bool //
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Race bool // race detector enabled
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BigEndian bool //
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UseFMA bool // Use hardware FMA operation
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}
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type (
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@ -195,6 +200,8 @@ func NewConfig(arch string, types Types, ctxt *obj.Link, optimize bool) *Config
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c.gpRegMask = gpRegMaskAMD64
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c.fpRegMask = fpRegMaskAMD64
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c.specialRegMask = specialRegMaskAMD64
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c.intParamRegs = paramIntRegAMD64
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c.floatParamRegs = paramFloatRegAMD64
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c.FPReg = framepointerRegAMD64
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c.LinkReg = linkRegAMD64
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c.hasGReg = base.Flag.ABIWrap
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@ -326,6 +333,9 @@ func NewConfig(arch string, types Types, ctxt *obj.Link, optimize bool) *Config
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c.useSSE = true
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c.UseFMA = true
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c.ABI0 = abi.NewABIConfig(0, 0)
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c.ABI1 = abi.NewABIConfig(len(c.intParamRegs), len(c.floatParamRegs))
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// On Plan 9, floating point operations are not allowed in note handler.
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if objabi.GOOS == "plan9" {
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// Don't use FMA on Plan 9
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@ -2,6 +2,7 @@
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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//go:build ignore
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// +build ignore
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package main
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@ -929,16 +930,18 @@ func init() {
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}
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archs = append(archs, arch{
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name: "AMD64",
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pkg: "cmd/internal/obj/x86",
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genfile: "../../amd64/ssa.go",
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ops: AMD64ops,
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blocks: AMD64blocks,
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regnames: regNamesAMD64,
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gpregmask: gp,
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fpregmask: fp,
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specialregmask: x15,
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framepointerreg: int8(num["BP"]),
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linkreg: -1, // not used
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name: "AMD64",
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pkg: "cmd/internal/obj/x86",
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genfile: "../../amd64/ssa.go",
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ops: AMD64ops,
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blocks: AMD64blocks,
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regnames: regNamesAMD64,
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ParamIntRegNames: "AX BX CX DI SI R8 R9 R10 R11",
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ParamFloatRegNames: "X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14",
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gpregmask: gp,
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fpregmask: fp,
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specialregmask: x15,
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framepointerreg: int8(num["BP"]),
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linkreg: -1, // not used
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})
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}
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@ -2,6 +2,7 @@
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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//go:build ignore
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// +build ignore
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package main
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@ -332,6 +333,11 @@ var genericOps = []opData{
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{name: "InitMem", zeroWidth: true}, // memory input to the function.
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{name: "Arg", aux: "SymOff", symEffect: "Read", zeroWidth: true}, // argument to the function. aux=GCNode of arg, off = offset in that arg.
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// Like Arg, these are generic ops that survive lowering. AuxInt is a register index, and the actual output register for each index is defined by the architecture.
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// AuxInt = integer argument index (not a register number). ABI-specified spill loc obtained from function
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{name: "ArgIntReg", aux: "Int8", zeroWidth: true}, // argument to the function in an int reg.
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{name: "ArgFloatReg", aux: "Int8", zeroWidth: true}, // argument to the function in a float reg.
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// The address of a variable. arg0 is the base pointer.
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// If the variable is a global, the base pointer will be SB and
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// the Aux field will be a *obj.LSym.
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@ -2,6 +2,7 @@
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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//go:build ignore
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// +build ignore
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// The gen command generates Go code (in the parent directory) for all
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@ -30,21 +31,23 @@ import (
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// apart from type names, and avoid awkward func parameters like "arch arch".
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type arch struct {
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name string
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pkg string // obj package to import for this arch.
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genfile string // source file containing opcode code generation.
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ops []opData
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blocks []blockData
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regnames []string
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gpregmask regMask
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fpregmask regMask
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fp32regmask regMask
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fp64regmask regMask
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specialregmask regMask
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framepointerreg int8
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linkreg int8
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generic bool
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imports []string
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name string
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pkg string // obj package to import for this arch.
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genfile string // source file containing opcode code generation.
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ops []opData
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blocks []blockData
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regnames []string
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ParamIntRegNames string
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ParamFloatRegNames string
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gpregmask regMask
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fpregmask regMask
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fp32regmask regMask
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fp64regmask regMask
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specialregmask regMask
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framepointerreg int8
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linkreg int8
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generic bool
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imports []string
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}
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type opData struct {
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@ -412,7 +415,9 @@ func genOp() {
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}
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fmt.Fprintf(w, "var registers%s = [...]Register {\n", a.name)
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var gcRegN int
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num := map[string]int8{}
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for i, r := range a.regnames {
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num[r] = int8(i)
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pkg := a.pkg[len("cmd/internal/obj/"):]
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var objname string // name in cmd/internal/obj/$ARCH
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switch r {
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@ -435,11 +440,38 @@ func genOp() {
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}
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fmt.Fprintf(w, " {%d, %s, %d, \"%s\"},\n", i, objname, gcRegIdx, r)
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}
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parameterRegisterList := func(paramNamesString string) []int8 {
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paramNamesString = strings.TrimSpace(paramNamesString)
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if paramNamesString == "" {
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return nil
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}
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paramNames := strings.Split(paramNamesString, " ")
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var paramRegs []int8
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for _, regName := range paramNames {
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if regName == "" {
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// forgive extra spaces
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continue
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}
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if regNum, ok := num[regName]; ok {
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paramRegs = append(paramRegs, regNum)
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delete(num, regName)
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} else {
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log.Fatalf("parameter register %s for architecture %s not a register name (or repeated in parameter list)", regName, a.name)
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}
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}
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return paramRegs
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}
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paramIntRegs := parameterRegisterList(a.ParamIntRegNames)
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paramFloatRegs := parameterRegisterList(a.ParamFloatRegNames)
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if gcRegN > 32 {
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// Won't fit in a uint32 mask.
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log.Fatalf("too many GC registers (%d > 32) on %s", gcRegN, a.name)
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}
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fmt.Fprintln(w, "}")
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fmt.Fprintf(w, "var paramIntReg%s = %#v\n", a.name, paramIntRegs)
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fmt.Fprintf(w, "var paramFloatReg%s = %#v\n", a.name, paramFloatRegs)
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fmt.Fprintf(w, "var gpRegMask%s = regMask(%d)\n", a.name, a.gpregmask)
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fmt.Fprintf(w, "var fpRegMask%s = regMask(%d)\n", a.name, a.fpregmask)
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if a.fp32regmask != 0 {
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@ -79,6 +79,7 @@ type AuxCall struct {
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Fn *obj.LSym
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args []Param // Includes receiver for method calls. Does NOT include hidden closure pointer.
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results []Param
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reg *regInfo // regInfo for this call // TODO for now nil means ignore
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}
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// ResultForOffset returns the index of the result at a particular offset among the results
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@ -186,16 +187,19 @@ func (a *AuxCall) String() string {
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// StaticAuxCall returns an AuxCall for a static call.
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func StaticAuxCall(sym *obj.LSym, args []Param, results []Param) *AuxCall {
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// TODO Create regInfo for AuxCall
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return &AuxCall{Fn: sym, args: args, results: results}
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}
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// InterfaceAuxCall returns an AuxCall for an interface call.
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func InterfaceAuxCall(args []Param, results []Param) *AuxCall {
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// TODO Create regInfo for AuxCall
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return &AuxCall{Fn: nil, args: args, results: results}
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}
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// ClosureAuxCall returns an AuxCall for a closure call.
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func ClosureAuxCall(args []Param, results []Param) *AuxCall {
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// TODO Create regInfo for AuxCall
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return &AuxCall{Fn: nil, args: args, results: results}
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}
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@ -2747,6 +2747,8 @@ const (
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OpConstSlice
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OpInitMem
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OpArg
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OpArgIntReg
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OpArgFloatReg
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OpAddr
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OpLocalAddr
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OpSP
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@ -35253,6 +35255,20 @@ var opcodeTable = [...]opInfo{
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symEffect: SymRead,
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generic: true,
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},
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{
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name: "ArgIntReg",
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auxType: auxInt8,
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argLen: 0,
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zeroWidth: true,
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generic: true,
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},
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{
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name: "ArgFloatReg",
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auxType: auxInt8,
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argLen: 0,
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zeroWidth: true,
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generic: true,
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},
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{
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name: "Addr",
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auxType: auxSym,
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@ -36141,6 +36157,8 @@ var registers386 = [...]Register{
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{15, x86.REG_X7, -1, "X7"},
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{16, 0, -1, "SB"},
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}
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var paramIntReg386 = []int8(nil)
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var paramFloatReg386 = []int8(nil)
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var gpRegMask386 = regMask(239)
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var fpRegMask386 = regMask(65280)
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var specialRegMask386 = regMask(0)
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@ -36181,6 +36199,8 @@ var registersAMD64 = [...]Register{
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{31, x86.REG_X15, -1, "X15"},
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{32, 0, -1, "SB"},
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}
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var paramIntRegAMD64 = []int8{0, 3, 1, 7, 6, 8, 9, 10, 11}
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var paramFloatRegAMD64 = []int8{16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30}
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var gpRegMaskAMD64 = regMask(49135)
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var fpRegMaskAMD64 = regMask(2147418112)
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var specialRegMaskAMD64 = regMask(2147483648)
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@ -36221,6 +36241,8 @@ var registersARM = [...]Register{
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{31, arm.REG_F15, -1, "F15"},
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{32, 0, -1, "SB"},
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}
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var paramIntRegARM = []int8(nil)
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var paramFloatRegARM = []int8(nil)
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var gpRegMaskARM = regMask(21503)
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var fpRegMaskARM = regMask(4294901760)
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var specialRegMaskARM = regMask(0)
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@ -36292,6 +36314,8 @@ var registersARM64 = [...]Register{
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{62, arm64.REG_F31, -1, "F31"},
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{63, 0, -1, "SB"},
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}
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var paramIntRegARM64 = []int8(nil)
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var paramFloatRegARM64 = []int8(nil)
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var gpRegMaskARM64 = regMask(670826495)
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var fpRegMaskARM64 = regMask(9223372034707292160)
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var specialRegMaskARM64 = regMask(0)
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@ -36347,6 +36371,8 @@ var registersMIPS = [...]Register{
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{46, mips.REG_LO, -1, "LO"},
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{47, 0, -1, "SB"},
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}
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var paramIntRegMIPS = []int8(nil)
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var paramFloatRegMIPS = []int8(nil)
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var gpRegMaskMIPS = regMask(335544318)
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var fpRegMaskMIPS = regMask(35183835217920)
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var specialRegMaskMIPS = regMask(105553116266496)
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@ -36417,6 +36443,8 @@ var registersMIPS64 = [...]Register{
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{61, mips.REG_LO, -1, "LO"},
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{62, 0, -1, "SB"},
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}
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var paramIntRegMIPS64 = []int8(nil)
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var paramFloatRegMIPS64 = []int8(nil)
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var gpRegMaskMIPS64 = regMask(167772158)
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var fpRegMaskMIPS64 = regMask(1152921504338411520)
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var specialRegMaskMIPS64 = regMask(3458764513820540928)
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@ -36488,6 +36516,8 @@ var registersPPC64 = [...]Register{
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{62, ppc64.REG_F30, -1, "F30"},
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{63, ppc64.REG_F31, -1, "F31"},
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}
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var paramIntRegPPC64 = []int8(nil)
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var paramFloatRegPPC64 = []int8(nil)
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var gpRegMaskPPC64 = regMask(1073733624)
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var fpRegMaskPPC64 = regMask(576460743713488896)
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var specialRegMaskPPC64 = regMask(0)
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@ -36559,6 +36589,8 @@ var registersRISCV64 = [...]Register{
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{62, riscv.REG_F31, -1, "F31"},
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{63, 0, -1, "SB"},
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}
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var paramIntRegRISCV64 = []int8(nil)
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var paramFloatRegRISCV64 = []int8(nil)
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var gpRegMaskRISCV64 = regMask(1006632948)
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var fpRegMaskRISCV64 = regMask(9223372034707292160)
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var specialRegMaskRISCV64 = regMask(0)
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@ -36599,6 +36631,8 @@ var registersS390X = [...]Register{
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{31, s390x.REG_F15, -1, "F15"},
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{32, 0, -1, "SB"},
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}
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var paramIntRegS390X = []int8(nil)
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var paramFloatRegS390X = []int8(nil)
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var gpRegMaskS390X = regMask(23551)
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var fpRegMaskS390X = regMask(4294901760)
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var specialRegMaskS390X = regMask(0)
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@ -36657,6 +36691,8 @@ var registersWasm = [...]Register{
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{49, wasm.REGG, -1, "g"},
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{50, 0, -1, "SB"},
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}
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var paramIntRegWasm = []int8(nil)
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var paramFloatRegWasm = []int8(nil)
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var gpRegMaskWasm = regMask(65535)
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var fpRegMaskWasm = regMask(281474976645120)
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var fp32RegMaskWasm = regMask(4294901760)
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@ -112,7 +112,7 @@ const (
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stackDebug = 0
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stackFromSystem = 0 // allocate stacks from system memory instead of the heap
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stackFaultOnFree = 0 // old stacks are mapped noaccess to detect use after free
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stackPoisonCopy = 0 // fill stack that should not be accessed with garbage, to detect bad dereferences during copy
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stackPoisonCopy = 1 // fill stack that should not be accessed with garbage, to detect bad dereferences during copy
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stackNoCache = 0 // disable per-P small stack caches
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// check the BP links during traceback.
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