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runtime: implement asyncPreempt for linux/loong64
Contributors to the loong64 port are: Weining Lu <luweining@loongson.cn> Lei Wang <wanglei@loongson.cn> Lingqin Gong <gonglingqin@loongson.cn> Xiaolin Zhao <zhaoxiaolin@loongson.cn> Meidan Li <limeidan@loongson.cn> Xiaojuan Zhai <zhaixiaojuan@loongson.cn> Qiyuan Pu <puqiyuan@loongson.cn> Guoqi Chen <chenguoqi@loongson.cn> This port has been updated to Go 1.15.6: https://github.com/loongson/go Updates #46229 Change-Id: I7a64e38b15a99816bd74262c02f62dad021cc166 Reviewed-on: https://go-review.googlesource.com/c/go/+/368078 Reviewed-by: Cherry Mui <cherryyz@google.com> Reviewed-by: Ian Lance Taylor <iant@google.com> Auto-Submit: Ian Lance Taylor <iant@google.com> Reviewed-by: David Chase <drchase@google.com> Run-TryBot: Ian Lance Taylor <iant@google.com> TryBot-Result: Gopher Robot <gobot@golang.org>
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@ -80,6 +80,7 @@ var arches = map[string]func(){
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"amd64": genAMD64,
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"arm": genARM,
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"arm64": genARM64,
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"loong64": genLoong64,
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"mips64x": func() { genMIPS(true) },
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"mipsx": func() { genMIPS(false) },
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"ppc64x": genPPC64,
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@ -451,6 +452,46 @@ func genMIPS(_64bit bool) {
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p("JMP (R23)")
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}
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func genLoong64() {
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mov := "MOVV"
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movf := "MOVD"
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add := "ADDV"
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sub := "SUBV"
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r31 := "RSB"
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regsize := 8
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// Add integer registers r4-r21 r23-r29 r31
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// R0 (zero), R30 (REGTMP), R2 (tp), R3 (SP), R22 (g), R1 (LR) are special,
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var l = layout{sp: "R3", stack: regsize} // add slot to save PC of interrupted instruction (in LR)
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for i := 4; i <= 29; i++ {
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if i == 22 {
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continue // R3 is REGSP R22 is g
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}
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reg := fmt.Sprintf("R%d", i)
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l.add(mov, reg, regsize)
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}
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l.add(mov, r31, regsize)
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// Add floating point registers F0-F31.
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for i := 0; i <= 31; i++ {
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reg := fmt.Sprintf("F%d", i)
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l.add(movf, reg, regsize)
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}
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// allocate frame, save PC of interrupted instruction (in LR)
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p(mov+" R1, -%d(R3)", l.stack)
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p(sub+" $%d, R3", l.stack)
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l.save()
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p("CALL ·asyncPreempt2(SB)")
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l.restore()
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p(mov+" %d(R3), R1", l.stack) // sigctxt.pushCall has pushed LR (at interrupt) on stack, restore it
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p(mov + " (R3), R30") // load PC to REGTMP
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p(add+" $%d, R3", l.stack+regsize) // pop frame (including the space pushed by sigctxt.pushCall)
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p("JMP (R30)")
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}
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func genPPC64() {
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// Add integer registers R3-R29
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// R0 (zero), R1 (SP), R30 (g) are special and not saved here.
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129
src/runtime/preempt_loong64.s
Normal file
129
src/runtime/preempt_loong64.s
Normal file
@ -0,0 +1,129 @@
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// Code generated by mkpreempt.go; DO NOT EDIT.
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#include "go_asm.h"
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#include "textflag.h"
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TEXT ·asyncPreempt(SB),NOSPLIT|NOFRAME,$0-0
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MOVV R1, -472(R3)
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SUBV $472, R3
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MOVV R4, 8(R3)
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MOVV R5, 16(R3)
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MOVV R6, 24(R3)
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MOVV R7, 32(R3)
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MOVV R8, 40(R3)
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MOVV R9, 48(R3)
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MOVV R10, 56(R3)
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MOVV R11, 64(R3)
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MOVV R12, 72(R3)
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MOVV R13, 80(R3)
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MOVV R14, 88(R3)
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MOVV R15, 96(R3)
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MOVV R16, 104(R3)
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MOVV R17, 112(R3)
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MOVV R18, 120(R3)
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MOVV R19, 128(R3)
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MOVV R20, 136(R3)
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MOVV R21, 144(R3)
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MOVV R23, 152(R3)
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MOVV R24, 160(R3)
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MOVV R25, 168(R3)
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MOVV R26, 176(R3)
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MOVV R27, 184(R3)
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MOVV R28, 192(R3)
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MOVV R29, 200(R3)
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MOVV RSB, 208(R3)
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MOVD F0, 216(R3)
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MOVD F1, 224(R3)
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MOVD F2, 232(R3)
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MOVD F3, 240(R3)
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MOVD F4, 248(R3)
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MOVD F5, 256(R3)
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MOVD F6, 264(R3)
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MOVD F7, 272(R3)
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MOVD F8, 280(R3)
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MOVD F9, 288(R3)
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MOVD F10, 296(R3)
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MOVD F11, 304(R3)
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MOVD F12, 312(R3)
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MOVD F13, 320(R3)
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MOVD F14, 328(R3)
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MOVD F15, 336(R3)
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MOVD F16, 344(R3)
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MOVD F17, 352(R3)
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MOVD F18, 360(R3)
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MOVD F19, 368(R3)
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MOVD F20, 376(R3)
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MOVD F21, 384(R3)
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MOVD F22, 392(R3)
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MOVD F23, 400(R3)
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MOVD F24, 408(R3)
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MOVD F25, 416(R3)
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MOVD F26, 424(R3)
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MOVD F27, 432(R3)
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MOVD F28, 440(R3)
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MOVD F29, 448(R3)
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MOVD F30, 456(R3)
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MOVD F31, 464(R3)
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CALL ·asyncPreempt2(SB)
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MOVD 464(R3), F31
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MOVD 456(R3), F30
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MOVD 448(R3), F29
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MOVD 440(R3), F28
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MOVD 432(R3), F27
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MOVD 424(R3), F26
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MOVD 416(R3), F25
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MOVD 408(R3), F24
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MOVD 400(R3), F23
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MOVD 392(R3), F22
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MOVD 384(R3), F21
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MOVD 376(R3), F20
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MOVD 368(R3), F19
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MOVD 360(R3), F18
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MOVD 352(R3), F17
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MOVD 344(R3), F16
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MOVD 336(R3), F15
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MOVD 328(R3), F14
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MOVD 320(R3), F13
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MOVD 312(R3), F12
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MOVD 304(R3), F11
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MOVD 296(R3), F10
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MOVD 288(R3), F9
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MOVD 280(R3), F8
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MOVD 272(R3), F7
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MOVD 264(R3), F6
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MOVD 256(R3), F5
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MOVD 248(R3), F4
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MOVD 240(R3), F3
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MOVD 232(R3), F2
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MOVD 224(R3), F1
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MOVD 216(R3), F0
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MOVV 208(R3), RSB
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MOVV 200(R3), R29
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MOVV 192(R3), R28
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MOVV 184(R3), R27
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MOVV 176(R3), R26
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MOVV 168(R3), R25
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MOVV 160(R3), R24
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MOVV 152(R3), R23
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MOVV 144(R3), R21
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MOVV 136(R3), R20
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MOVV 128(R3), R19
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MOVV 120(R3), R18
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MOVV 112(R3), R17
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MOVV 104(R3), R16
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MOVV 96(R3), R15
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MOVV 88(R3), R14
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MOVV 80(R3), R13
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MOVV 72(R3), R12
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MOVV 64(R3), R11
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MOVV 56(R3), R10
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MOVV 48(R3), R9
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MOVV 40(R3), R8
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MOVV 32(R3), R7
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MOVV 24(R3), R6
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MOVV 16(R3), R5
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MOVV 8(R3), R4
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MOVV 472(R3), R1
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MOVV (R3), R30
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ADDV $480, R3
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JMP (R30)
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