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https://github.com/golang/go
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[dev.ssa] cmd/compile/internal/gc: reduce genValue redundancy
Add an asm field to opcodeTable containing the Prog's as field. Then instructions that fill the Prog the same way can be collapsed into a single switch case. I'm still thinking of a better way to reduce redundancy, but I think this might be a good temporary solution to prevent duplication from getting out of control. What do you think? Change-Id: I0c4a0992741f908bd357ee2707edb82e76e4ce61 Reviewed-on: https://go-review.googlesource.com/11130 Reviewed-by: Josh Bleecher Snyder <josharian@gmail.com> Reviewed-by: Keith Randall <khr@golang.org>
This commit is contained in:
Michael Matloob
Michael Matloob
parent
3b817ef8f8
commit
703ef06039
@ -802,7 +802,7 @@ func genValue(v *ssa.Value) {
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p.From.Offset = v.AuxInt
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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case ssa.OpAMD64SHLQ:
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case ssa.OpAMD64SHLQ, ssa.OpAMD64SHRQ, ssa.OpAMD64SARQ:
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x := regnum(v.Args[0])
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r := regnum(v)
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if x != r {
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@ -816,50 +816,12 @@ func genValue(v *ssa.Value) {
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p.To.Reg = r
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x = r
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}
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p := Prog(x86.ASHLQ)
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p := Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = regnum(v.Args[1]) // should be CX
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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case ssa.OpAMD64SHRQ:
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x := regnum(v.Args[0])
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r := regnum(v)
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if x != r {
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if r == x86.REG_CX {
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log.Fatalf("can't implement %s, target and shift both in CX", v.LongString())
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}
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p := Prog(x86.AMOVQ)
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p.From.Type = obj.TYPE_REG
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p.From.Reg = x
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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x = r
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}
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p := Prog(x86.ASHRQ)
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p.From.Type = obj.TYPE_REG
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p.From.Reg = regnum(v.Args[1]) // should be CX
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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case ssa.OpAMD64SARQ:
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x := regnum(v.Args[0])
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r := regnum(v)
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if x != r {
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if r == x86.REG_CX {
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log.Fatalf("can't implement %s, target and shift both in CX", v.LongString())
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}
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p := Prog(x86.AMOVQ)
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p.From.Type = obj.TYPE_REG
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p.From.Reg = x
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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x = r
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}
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p := Prog(x86.ASARQ)
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p.From.Type = obj.TYPE_REG
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p.From.Reg = regnum(v.Args[1]) // should be CX
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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case ssa.OpAMD64SHLQconst:
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case ssa.OpAMD64SHLQconst, ssa.OpAMD64SHRQconst, ssa.OpAMD64SARQconst:
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x := regnum(v.Args[0])
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r := regnum(v)
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if x != r {
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@ -870,43 +832,10 @@ func genValue(v *ssa.Value) {
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p.To.Reg = r
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x = r
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}
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p := Prog(x86.ASHLQ)
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p := Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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case ssa.OpAMD64SHRQconst:
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x := regnum(v.Args[0])
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r := regnum(v)
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if x != r {
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p := Prog(x86.AMOVQ)
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p.From.Type = obj.TYPE_REG
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p.From.Reg = x
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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x = r
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}
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p := Prog(x86.ASHRQ)
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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case ssa.OpAMD64SARQconst:
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x := regnum(v.Args[0])
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r := regnum(v)
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if x != r {
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p := Prog(x86.AMOVQ)
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p.From.Type = obj.TYPE_REG
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p.From.Reg = x
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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x = r
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}
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p := Prog(x86.ASARQ)
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p.From.Type = obj.TYPE_CONST
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p.From.Offset = v.AuxInt
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p.To.Type = obj.TYPE_REG
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p.To.Reg = r
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case ssa.OpAMD64SBBQcarrymask:
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r := regnum(v)
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p := Prog(x86.ASBBQ)
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@ -967,8 +896,8 @@ func genValue(v *ssa.Value) {
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p.From.Offset = v.AuxInt
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p.To.Type = obj.TYPE_REG
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p.To.Reg = regnum(v)
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case ssa.OpAMD64CMPQ:
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p := Prog(x86.ACMPQ)
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case ssa.OpAMD64CMPQ, ssa.OpAMD64TESTB, ssa.OpAMD64TESTQ:
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p := Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_REG
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p.From.Reg = regnum(v.Args[0])
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p.To.Type = obj.TYPE_REG
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@ -979,18 +908,6 @@ func genValue(v *ssa.Value) {
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p.From.Reg = regnum(v.Args[0])
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p.To.Type = obj.TYPE_CONST
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p.To.Offset = v.AuxInt
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case ssa.OpAMD64TESTB:
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p := Prog(x86.ATESTB)
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p.From.Type = obj.TYPE_REG
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p.From.Reg = regnum(v.Args[0])
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p.To.Type = obj.TYPE_REG
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p.To.Reg = regnum(v.Args[1])
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case ssa.OpAMD64TESTQ:
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p := Prog(x86.ATESTQ)
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p.From.Type = obj.TYPE_REG
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p.From.Reg = regnum(v.Args[0])
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p.To.Type = obj.TYPE_REG
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p.To.Reg = regnum(v.Args[1])
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case ssa.OpAMD64MOVQconst:
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x := regnum(v)
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p := Prog(x86.AMOVQ)
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@ -998,15 +915,8 @@ func genValue(v *ssa.Value) {
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p.From.Offset = v.AuxInt
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p.To.Type = obj.TYPE_REG
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p.To.Reg = x
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case ssa.OpAMD64MOVQload:
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p := Prog(x86.AMOVQ)
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = regnum(v.Args[0])
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p.From.Offset = v.AuxInt
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p.To.Type = obj.TYPE_REG
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p.To.Reg = regnum(v)
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case ssa.OpAMD64MOVBload:
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p := Prog(x86.AMOVB)
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case ssa.OpAMD64MOVQload, ssa.OpAMD64MOVBload:
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p := Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = regnum(v.Args[0])
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p.From.Offset = v.AuxInt
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@ -4,7 +4,10 @@
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package main
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import "strings"
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import (
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"cmd/internal/obj/x86"
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"strings"
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)
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// copied from ../../amd64/reg.go
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var regNamesAMD64 = []string{
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@ -92,29 +95,29 @@ func init() {
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// TODO: 2-address instructions. Mark ops as needing matching input/output regs.
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var AMD64ops = []opData{
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{name: "ADDQ", reg: gp21}, // arg0 + arg1
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{name: "ADDQconst", reg: gp11}, // arg0 + auxint
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{name: "SUBQ", reg: gp21}, // arg0 - arg1
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{name: "SUBQconst", reg: gp11}, // arg0 - auxint
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{name: "MULQ", reg: gp21}, // arg0 * arg1
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{name: "MULQconst", reg: gp11}, // arg0 * auxint
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{name: "ANDQ", reg: gp21}, // arg0 & arg1
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{name: "ANDQconst", reg: gp11}, // arg0 & auxint
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{name: "SHLQ", reg: gp21shift}, // arg0 << arg1, shift amount is mod 64
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{name: "SHLQconst", reg: gp11}, // arg0 << auxint, shift amount 0-63
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{name: "SHRQ", reg: gp21shift}, // unsigned arg0 >> arg1, shift amount is mod 64
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{name: "SHRQconst", reg: gp11}, // unsigned arg0 >> auxint, shift amount 0-63
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{name: "SARQ", reg: gp21shift}, // signed arg0 >> arg1, shift amount is mod 64
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{name: "SARQconst", reg: gp11}, // signed arg0 >> auxint, shift amount 0-63
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{name: "ADDQ", reg: gp21}, // arg0 + arg1
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{name: "ADDQconst", reg: gp11}, // arg0 + auxint
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{name: "SUBQ", reg: gp21, asm: x86.ASUBQ}, // arg0 - arg1
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{name: "SUBQconst", reg: gp11, asm: x86.ASUBQ}, // arg0 - auxint
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{name: "MULQ", reg: gp21, asm: x86.AIMULQ}, // arg0 * arg1
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{name: "MULQconst", reg: gp11, asm: x86.AIMULQ}, // arg0 * auxint
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{name: "ANDQ", reg: gp21, asm: x86.AANDQ}, // arg0 & arg1
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{name: "ANDQconst", reg: gp11, asm: x86.AANDQ}, // arg0 & auxint
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{name: "SHLQ", reg: gp21shift, asm: x86.ASHLQ}, // arg0 << arg1, shift amount is mod 64
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{name: "SHLQconst", reg: gp11, asm: x86.ASHLQ}, // arg0 << auxint, shift amount 0-63
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{name: "SHRQ", reg: gp21shift, asm: x86.ASHRQ}, // unsigned arg0 >> arg1, shift amount is mod 64
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{name: "SHRQconst", reg: gp11, asm: x86.ASHRQ}, // unsigned arg0 >> auxint, shift amount 0-63
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{name: "SARQ", reg: gp21shift, asm: x86.ASARQ}, // signed arg0 >> arg1, shift amount is mod 64
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{name: "SARQconst", reg: gp11, asm: x86.ASARQ}, // signed arg0 >> auxint, shift amount 0-63
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{name: "NEGQ", reg: gp11}, // -arg0
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{name: "CMPQ", reg: gp2flags}, // arg0 compare to arg1
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{name: "CMPQconst", reg: gp1flags}, // arg0 compare to auxint
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{name: "TESTQ", reg: gp2flags}, // (arg0 & arg1) compare to 0
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{name: "TESTB", reg: gp2flags}, // (arg0 & arg1) compare to 0
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{name: "CMPQ", reg: gp2flags, asm: x86.ACMPQ}, // arg0 compare to arg1
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{name: "CMPQconst", reg: gp1flags, asm: x86.ACMPQ}, // arg0 compare to auxint
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{name: "TESTQ", reg: gp2flags, asm: x86.ATESTQ}, // (arg0 & arg1) compare to 0
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{name: "TESTB", reg: gp2flags, asm: x86.ATESTB}, // (arg0 & arg1) compare to 0
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{name: "SBBQcarrymask", reg: flagsgp1}, // (int64)(-1) if carry is set, 0 if carry is clear.
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{name: "SBBQcarrymask", reg: flagsgp1, asm: x86.ASBBQ}, // (int64)(-1) if carry is set, 0 if carry is clear.
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{name: "SETEQ", reg: flagsgp}, // extract == condition from arg0
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{name: "SETNE", reg: flagsgp}, // extract != condition from arg0
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@ -132,14 +135,14 @@ func init() {
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{name: "LEAQ8", reg: gp21}, // arg0 + 8*arg1 + auxint
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{name: "LEAQglobal", reg: gp01}, // no args. address of aux.(*gc.Sym)
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{name: "MOVBload", reg: gpload}, // load byte from arg0+auxint. arg1=mem
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{name: "MOVBQZXload", reg: gpload}, // ditto, extend to uint64
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{name: "MOVBQSXload", reg: gpload}, // ditto, extend to int64
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{name: "MOVQload", reg: gpload}, // load 8 bytes from arg0+auxint. arg1=mem
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{name: "MOVQloadidx8", reg: gploadidx}, // load 8 bytes from arg0+8*arg1+auxint. arg2=mem
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{name: "MOVBstore", reg: gpstore}, // store byte in arg1 to arg0+auxint. arg2=mem
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{name: "MOVQstore", reg: gpstore}, // store 8 bytes in arg1 to arg0+auxint. arg2=mem
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{name: "MOVQstoreidx8", reg: gpstoreidx}, // store 8 bytes in arg2 to arg0+8*arg1+auxint. arg3=mem
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{name: "MOVBload", reg: gpload}, // load byte from arg0+auxint. arg1=mem
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{name: "MOVBQZXload", reg: gpload}, // ditto, extend to uint64
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{name: "MOVBQSXload", reg: gpload}, // ditto, extend to int64
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{name: "MOVQload", reg: gpload}, // load 8 bytes from arg0+auxint. arg1=mem
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{name: "MOVQloadidx8", reg: gploadidx}, // load 8 bytes from arg0+8*arg1+auxint. arg2=mem
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{name: "MOVBstore", reg: gpstore, asm: x86.AMOVB}, // store byte in arg1 to arg0+auxint. arg2=mem
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{name: "MOVQstore", reg: gpstore, asm: x86.AMOVQ}, // store 8 bytes in arg1 to arg0+auxint. arg2=mem
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{name: "MOVQstoreidx8", reg: gpstoreidx}, // store 8 bytes in arg2 to arg0+8*arg1+auxint. arg3=mem
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// Load/store from global. Same as the above loads, but arg0 is missing and
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// aux is a GlobalOffset instead of an int64.
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@ -152,7 +155,7 @@ func init() {
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{name: "REPMOVSB", reg: regInfo{[]regMask{buildReg("DI"), buildReg("SI"), buildReg("CX")}, buildReg("DI SI CX"), nil}}, // move arg2 bytes from arg1 to arg0. arg3=mem, returns memory
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{name: "ADDL", reg: gp21}, // arg0+arg1
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{name: "ADDL", reg: gp21, asm: x86.AADDL}, // arg0+arg1
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// (InvertFlags (CMPQ a b)) == (CMPQ b a)
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// So if we want (SETL (CMPQ a b)) but we can't do that because a is a constant,
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@ -9,6 +9,8 @@ package main
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import (
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"bytes"
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"cmd/internal/obj"
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"cmd/internal/obj/x86"
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"fmt"
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"go/format"
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"io/ioutil"
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@ -25,6 +27,7 @@ type arch struct {
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type opData struct {
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name string
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reg regInfo
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asm int16
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}
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type blockData struct {
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@ -60,12 +63,15 @@ func main() {
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genOp()
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genLower()
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}
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func genOp() {
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w := new(bytes.Buffer)
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fmt.Fprintf(w, "// autogenerated: do not edit!\n")
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fmt.Fprintf(w, "// generated from gen/*Ops.go\n")
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fmt.Fprintln(w, "package ssa")
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fmt.Fprintln(w, "import \"cmd/internal/obj/x86\"")
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// generate Block* declarations
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fmt.Fprintln(w, "const (")
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fmt.Fprintln(w, "blockInvalid BlockKind = iota")
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@ -108,6 +114,9 @@ func genOp() {
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for _, v := range a.ops {
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fmt.Fprintln(w, "{")
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fmt.Fprintf(w, "name:\"%s\",\n", v.name)
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if v.asm != 0 {
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fmt.Fprintf(w, "asm: x86.A%s,\n", x86.Anames[v.asm-obj.ABaseAMD64])
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}
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fmt.Fprintln(w, "reg:regInfo{")
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fmt.Fprintln(w, "inputs: []regMask{")
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for _, r := range v.reg.inputs {
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@ -129,6 +138,8 @@ func genOp() {
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}
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fmt.Fprintln(w, "}")
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fmt.Fprintln(w, "func (o Op) Asm() int {return opcodeTable[o].asm}")
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// generate op string method
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fmt.Fprintln(w, "func (o Op) String() string {return opcodeTable[o].name }")
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@ -14,6 +14,7 @@ type Op int32
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type opInfo struct {
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name string
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asm int
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reg regInfo
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generic bool // this is a generic (arch-independent) opcode
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}
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@ -2,6 +2,8 @@
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// generated from gen/*Ops.go
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package ssa
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import "cmd/internal/obj/x86"
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const (
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blockInvalid BlockKind = iota
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@ -164,6 +166,7 @@ var opcodeTable = [...]opInfo{
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},
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{
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name: "SUBQ",
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asm: x86.ASUBQ,
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reg: regInfo{
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inputs: []regMask{
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4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .FP
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@ -177,6 +180,7 @@ var opcodeTable = [...]opInfo{
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},
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{
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name: "SUBQconst",
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asm: x86.ASUBQ,
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reg: regInfo{
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inputs: []regMask{
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4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .FP
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@ -189,6 +193,7 @@ var opcodeTable = [...]opInfo{
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},
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{
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name: "MULQ",
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asm: x86.AIMULQ,
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reg: regInfo{
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inputs: []regMask{
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4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .FP
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@ -202,6 +207,7 @@ var opcodeTable = [...]opInfo{
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},
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{
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name: "MULQconst",
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asm: x86.AIMULQ,
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reg: regInfo{
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inputs: []regMask{
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4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .FP
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@ -214,6 +220,7 @@ var opcodeTable = [...]opInfo{
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},
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{
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name: "ANDQ",
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asm: x86.AANDQ,
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reg: regInfo{
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inputs: []regMask{
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4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .FP
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@ -227,6 +234,7 @@ var opcodeTable = [...]opInfo{
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},
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{
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name: "ANDQconst",
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asm: x86.AANDQ,
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reg: regInfo{
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inputs: []regMask{
|
||||
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .FP
|
||||
@ -239,6 +247,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
{
|
||||
name: "SHLQ",
|
||||
asm: x86.ASHLQ,
|
||||
reg: regInfo{
|
||||
inputs: []regMask{
|
||||
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .FP
|
||||
@ -252,6 +261,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
{
|
||||
name: "SHLQconst",
|
||||
asm: x86.ASHLQ,
|
||||
reg: regInfo{
|
||||
inputs: []regMask{
|
||||
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .FP
|
||||
@ -264,6 +274,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
{
|
||||
name: "SHRQ",
|
||||
asm: x86.ASHRQ,
|
||||
reg: regInfo{
|
||||
inputs: []regMask{
|
||||
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .FP
|
||||
@ -277,6 +288,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
{
|
||||
name: "SHRQconst",
|
||||
asm: x86.ASHRQ,
|
||||
reg: regInfo{
|
||||
inputs: []regMask{
|
||||
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .FP
|
||||
@ -289,6 +301,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
{
|
||||
name: "SARQ",
|
||||
asm: x86.ASARQ,
|
||||
reg: regInfo{
|
||||
inputs: []regMask{
|
||||
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .FP
|
||||
@ -302,6 +315,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
{
|
||||
name: "SARQconst",
|
||||
asm: x86.ASARQ,
|
||||
reg: regInfo{
|
||||
inputs: []regMask{
|
||||
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .FP
|
||||
@ -326,6 +340,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
{
|
||||
name: "CMPQ",
|
||||
asm: x86.ACMPQ,
|
||||
reg: regInfo{
|
||||
inputs: []regMask{
|
||||
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .FP
|
||||
@ -339,6 +354,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
{
|
||||
name: "CMPQconst",
|
||||
asm: x86.ACMPQ,
|
||||
reg: regInfo{
|
||||
inputs: []regMask{
|
||||
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .FP
|
||||
@ -351,6 +367,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
{
|
||||
name: "TESTQ",
|
||||
asm: x86.ATESTQ,
|
||||
reg: regInfo{
|
||||
inputs: []regMask{
|
||||
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .FP
|
||||
@ -364,6 +381,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
{
|
||||
name: "TESTB",
|
||||
asm: x86.ATESTB,
|
||||
reg: regInfo{
|
||||
inputs: []regMask{
|
||||
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .FP
|
||||
@ -377,6 +395,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
{
|
||||
name: "SBBQcarrymask",
|
||||
asm: x86.ASBBQ,
|
||||
reg: regInfo{
|
||||
inputs: []regMask{
|
||||
8589934592, // .FLAGS
|
||||
@ -613,6 +632,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
{
|
||||
name: "MOVBstore",
|
||||
asm: x86.AMOVB,
|
||||
reg: regInfo{
|
||||
inputs: []regMask{
|
||||
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .FP
|
||||
@ -625,6 +645,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
{
|
||||
name: "MOVQstore",
|
||||
asm: x86.AMOVQ,
|
||||
reg: regInfo{
|
||||
inputs: []regMask{
|
||||
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .FP
|
||||
@ -698,6 +719,7 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
{
|
||||
name: "ADDL",
|
||||
asm: x86.AADDL,
|
||||
reg: regInfo{
|
||||
inputs: []regMask{
|
||||
4295032831, // .AX .CX .DX .BX .SP .BP .SI .DI .R8 .R9 .R10 .R11 .R12 .R13 .R14 .R15 .FP
|
||||
@ -1044,4 +1066,5 @@ var opcodeTable = [...]opInfo{
|
||||
},
|
||||
}
|
||||
|
||||
func (o Op) Asm() int { return opcodeTable[o].asm }
|
||||
func (o Op) String() string { return opcodeTable[o].name }
|
||||
|
||||
Loading…
Reference in New Issue
Block a user