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https://github.com/golang/go
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cmd/compile: MOVBload and MOVBQZXload are the same op
No need to have both ops when they do the same thing. Just declare MOVBload to zero extend and we can get rid of MOVBQZXload. Same for W and L. Kind of a followon cleanup for https://go-review.googlesource.com/c/19506/ Should enable an easier fix for #14920 Change-Id: I7cfac909a8ba387f433a6ae75c050740ebb34d42 Reviewed-on: https://go-review.googlesource.com/21004 Run-TryBot: Keith Randall <khr@golang.org> TryBot-Result: Gobot Gobot <gobot@golang.org> Reviewed-by: Brad Fitzpatrick <bradfitz@golang.org>
This commit is contained in:
Keith Randall
parent
5cdb3d0321
commit
68e86e6dfa
@ -660,7 +660,7 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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p.From.Val = math.Float64frombits(uint64(v.AuxInt))
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p.To.Type = obj.TYPE_REG
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p.To.Reg = x
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case ssa.OpAMD64MOVQload, ssa.OpAMD64MOVSSload, ssa.OpAMD64MOVSDload, ssa.OpAMD64MOVLload, ssa.OpAMD64MOVWload, ssa.OpAMD64MOVBload, ssa.OpAMD64MOVBQSXload, ssa.OpAMD64MOVBQZXload, ssa.OpAMD64MOVWQSXload, ssa.OpAMD64MOVWQZXload, ssa.OpAMD64MOVLQSXload, ssa.OpAMD64MOVLQZXload, ssa.OpAMD64MOVOload:
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case ssa.OpAMD64MOVQload, ssa.OpAMD64MOVSSload, ssa.OpAMD64MOVSDload, ssa.OpAMD64MOVLload, ssa.OpAMD64MOVWload, ssa.OpAMD64MOVBload, ssa.OpAMD64MOVBQSXload, ssa.OpAMD64MOVWQSXload, ssa.OpAMD64MOVLQSXload, ssa.OpAMD64MOVOload:
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p := gc.Prog(v.Op.Asm())
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p.From.Type = obj.TYPE_MEM
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p.From.Reg = gc.SSARegNum(v.Args[0])
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@ -1044,8 +1044,7 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
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switch w.Op {
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case ssa.OpAMD64MOVQload, ssa.OpAMD64MOVLload, ssa.OpAMD64MOVWload, ssa.OpAMD64MOVBload,
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ssa.OpAMD64MOVQstore, ssa.OpAMD64MOVLstore, ssa.OpAMD64MOVWstore, ssa.OpAMD64MOVBstore,
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ssa.OpAMD64MOVBQSXload, ssa.OpAMD64MOVBQZXload, ssa.OpAMD64MOVWQSXload,
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ssa.OpAMD64MOVWQZXload, ssa.OpAMD64MOVLQSXload, ssa.OpAMD64MOVLQZXload,
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ssa.OpAMD64MOVBQSXload, ssa.OpAMD64MOVWQSXload, ssa.OpAMD64MOVLQSXload,
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ssa.OpAMD64MOVSSload, ssa.OpAMD64MOVSDload, ssa.OpAMD64MOVOload,
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ssa.OpAMD64MOVSSstore, ssa.OpAMD64MOVSDstore, ssa.OpAMD64MOVOstore:
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if w.Args[0] == v.Args[0] && w.Aux == nil && w.AuxInt >= 0 && w.AuxInt < minZeroPage {
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@ -619,11 +619,15 @@
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// This prevents a single load from being split into multiple loads
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// which then might return different values. See test/atomicload.go.
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(MOVBQSX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 -> @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
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(MOVBQZX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 -> @x.Block (MOVBQZXload <v.Type> [off] {sym} ptr mem)
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(MOVBQZX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 -> @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
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(MOVWQSX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 -> @x.Block (MOVWQSXload <v.Type> [off] {sym} ptr mem)
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(MOVWQZX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 -> @x.Block (MOVWQZXload <v.Type> [off] {sym} ptr mem)
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(MOVWQZX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 -> @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
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(MOVLQSX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 -> @x.Block (MOVLQSXload <v.Type> [off] {sym} ptr mem)
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(MOVLQZX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 -> @x.Block (MOVLQZXload <v.Type> [off] {sym} ptr mem)
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(MOVLQZX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 -> @x.Block (MOVLload <v.Type> [off] {sym} ptr mem)
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(MOVBQZX x:(MOVBloadidx1 [off] {sym} ptr idx mem)) && x.Uses == 1 -> @x.Block (MOVBloadidx1 <v.Type> [off] {sym} ptr idx mem)
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(MOVWQZX x:(MOVWloadidx2 [off] {sym} ptr idx mem)) && x.Uses == 1 -> @x.Block (MOVWloadidx2 <v.Type> [off] {sym} ptr idx mem)
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(MOVLQZX x:(MOVLloadidx4 [off] {sym} ptr idx mem)) && x.Uses == 1 -> @x.Block (MOVLloadidx4 <v.Type> [off] {sym} ptr idx mem)
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// replace load from same location as preceding store with copy
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(MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x
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@ -705,12 +709,6 @@
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(MOVOload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
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(MOVOload [off1+off2] {mergeSym(sym1,sym2)} base mem)
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(MOVBQZXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
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(MOVBQZXload [off1+off2] {mergeSym(sym1,sym2)} base mem)
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(MOVWQZXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
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(MOVWQZXload [off1+off2] {mergeSym(sym1,sym2)} base mem)
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(MOVLQZXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
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(MOVLQZXload [off1+off2] {mergeSym(sym1,sym2)} base mem)
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(MOVBQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
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(MOVBQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem)
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(MOVWQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
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@ -1197,21 +1195,21 @@
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// Combining byte loads into larger (unaligned) loads.
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// There are many ways these combinations could occur. This is
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// designed to match the way encoding/binary.LittleEndian does it.
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(ORW x:(MOVBQZXload [i] {s} p mem)
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(SHLWconst [8] (MOVBQZXload [i+1] {s} p mem))) -> @x.Block (MOVWload [i] {s} p mem)
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(ORW x:(MOVBload [i] {s} p mem)
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(SHLWconst [8] (MOVBload [i+1] {s} p mem))) -> @x.Block (MOVWload [i] {s} p mem)
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(ORL (ORL (ORL
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x:(MOVBQZXload [i] {s} p mem)
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(SHLLconst [8] (MOVBQZXload [i+1] {s} p mem)))
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(SHLLconst [16] (MOVBQZXload [i+2] {s} p mem)))
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(SHLLconst [24] (MOVBQZXload [i+3] {s} p mem))) -> @x.Block (MOVLload [i] {s} p mem)
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x:(MOVBload [i] {s} p mem)
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(SHLLconst [8] (MOVBload [i+1] {s} p mem)))
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(SHLLconst [16] (MOVBload [i+2] {s} p mem)))
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(SHLLconst [24] (MOVBload [i+3] {s} p mem))) -> @x.Block (MOVLload [i] {s} p mem)
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(ORQ (ORQ (ORQ (ORQ (ORQ (ORQ (ORQ
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x:(MOVBQZXload [i] {s} p mem)
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(SHLQconst [8] (MOVBQZXload [i+1] {s} p mem)))
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(SHLQconst [16] (MOVBQZXload [i+2] {s} p mem)))
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(SHLQconst [24] (MOVBQZXload [i+3] {s} p mem)))
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(SHLQconst [32] (MOVBQZXload [i+4] {s} p mem)))
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(SHLQconst [40] (MOVBQZXload [i+5] {s} p mem)))
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(SHLQconst [48] (MOVBQZXload [i+6] {s} p mem)))
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(SHLQconst [56] (MOVBQZXload [i+7] {s} p mem))) -> @x.Block (MOVQload [i] {s} p mem)
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x:(MOVBload [i] {s} p mem)
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(SHLQconst [8] (MOVBload [i+1] {s} p mem)))
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(SHLQconst [16] (MOVBload [i+2] {s} p mem)))
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(SHLQconst [24] (MOVBload [i+3] {s} p mem)))
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(SHLQconst [32] (MOVBload [i+4] {s} p mem)))
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(SHLQconst [40] (MOVBload [i+5] {s} p mem)))
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(SHLQconst [48] (MOVBload [i+6] {s} p mem)))
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(SHLQconst [56] (MOVBload [i+7] {s} p mem))) -> @x.Block (MOVQload [i] {s} p mem)
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@ -367,15 +367,12 @@ func init() {
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// Note: LEAQ{1,2,4,8} must not have OpSB as either argument.
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// auxint+aux == add auxint and the offset of the symbol in aux (if any) to the effective address
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{name: "MOVBload", argLength: 2, reg: gpload, asm: "MOVBLZX", aux: "SymOff", typ: "UInt8"}, // load byte from arg0+auxint+aux. arg1=mem
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{name: "MOVBQSXload", argLength: 2, reg: gpload, asm: "MOVBQSX", aux: "SymOff"}, // ditto, extend to int64
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{name: "MOVBQZXload", argLength: 2, reg: gpload, asm: "MOVBLZX", aux: "SymOff"}, // ditto, extend to uint64
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{name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVWLZX", aux: "SymOff", typ: "UInt16"}, // load 2 bytes from arg0+auxint+aux. arg1=mem
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{name: "MOVWQSXload", argLength: 2, reg: gpload, asm: "MOVWQSX", aux: "SymOff"}, // ditto, extend to int64
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{name: "MOVWQZXload", argLength: 2, reg: gpload, asm: "MOVWLZX", aux: "SymOff"}, // ditto, extend to uint64
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{name: "MOVLload", argLength: 2, reg: gpload, asm: "MOVL", aux: "SymOff", typ: "UInt32"}, // load 4 bytes from arg0+auxint+aux. arg1=mem
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{name: "MOVLQSXload", argLength: 2, reg: gpload, asm: "MOVLQSX", aux: "SymOff"}, // ditto, extend to int64
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{name: "MOVLQZXload", argLength: 2, reg: gpload, asm: "MOVL", aux: "SymOff"}, // ditto, extend to uint64
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{name: "MOVBload", argLength: 2, reg: gpload, asm: "MOVBLZX", aux: "SymOff", typ: "UInt8"}, // load byte from arg0+auxint+aux. arg1=mem. Zero extend.
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{name: "MOVBQSXload", argLength: 2, reg: gpload, asm: "MOVBQSX", aux: "SymOff"}, // ditto, sign extend to int64
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{name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVWLZX", aux: "SymOff", typ: "UInt16"}, // load 2 bytes from arg0+auxint+aux. arg1=mem. Zero extend.
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{name: "MOVWQSXload", argLength: 2, reg: gpload, asm: "MOVWQSX", aux: "SymOff"}, // ditto, sign extend to int64
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{name: "MOVLload", argLength: 2, reg: gpload, asm: "MOVL", aux: "SymOff", typ: "UInt32"}, // load 4 bytes from arg0+auxint+aux. arg1=mem. Zero extend.
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{name: "MOVLQSXload", argLength: 2, reg: gpload, asm: "MOVLQSX", aux: "SymOff"}, // ditto, sign extend to int64
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{name: "MOVQload", argLength: 2, reg: gpload, asm: "MOVQ", aux: "SymOff", typ: "UInt64"}, // load 8 bytes from arg0+auxint+aux. arg1=mem
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{name: "MOVBstore", argLength: 3, reg: gpstore, asm: "MOVB", aux: "SymOff", typ: "Mem"}, // store byte in arg1 to arg0+auxint+aux. arg2=mem
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{name: "MOVWstore", argLength: 3, reg: gpstore, asm: "MOVW", aux: "SymOff", typ: "Mem"}, // store 2 bytes in arg1 to arg0+auxint+aux. arg2=mem
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@ -261,13 +261,10 @@ const (
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OpAMD64LEAQ8
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OpAMD64MOVBload
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OpAMD64MOVBQSXload
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OpAMD64MOVBQZXload
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OpAMD64MOVWload
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OpAMD64MOVWQSXload
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OpAMD64MOVWQZXload
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OpAMD64MOVLload
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OpAMD64MOVLQSXload
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OpAMD64MOVLQZXload
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OpAMD64MOVQload
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OpAMD64MOVBstore
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OpAMD64MOVWstore
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@ -3393,20 +3390,6 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "MOVBQZXload",
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auxType: auxSymOff,
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argLen: 2,
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asm: x86.AMOVBLZX,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
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},
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outputs: []regMask{
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65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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},
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},
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},
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{
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name: "MOVWload",
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auxType: auxSymOff,
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@ -3435,20 +3418,6 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "MOVWQZXload",
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auxType: auxSymOff,
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argLen: 2,
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asm: x86.AMOVWLZX,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
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},
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outputs: []regMask{
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65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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},
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},
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},
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{
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name: "MOVLload",
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auxType: auxSymOff,
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@ -3477,20 +3446,6 @@ var opcodeTable = [...]opInfo{
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},
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},
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},
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{
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name: "MOVLQZXload",
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auxType: auxSymOff,
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argLen: 2,
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asm: x86.AMOVL,
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reg: regInfo{
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inputs: []inputInfo{
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{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
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},
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outputs: []regMask{
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65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
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},
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},
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},
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{
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name: "MOVQload",
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auxType: auxSymOff,
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@ -336,8 +336,6 @@ func rewriteValueAMD64(v *Value, config *Config) bool {
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return rewriteValueAMD64_OpAMD64MOVBQSXload(v, config)
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case OpAMD64MOVBQZX:
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return rewriteValueAMD64_OpAMD64MOVBQZX(v, config)
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case OpAMD64MOVBQZXload:
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return rewriteValueAMD64_OpAMD64MOVBQZXload(v, config)
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case OpAMD64MOVBload:
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return rewriteValueAMD64_OpAMD64MOVBload(v, config)
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case OpAMD64MOVBloadidx1:
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@ -356,8 +354,6 @@ func rewriteValueAMD64(v *Value, config *Config) bool {
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return rewriteValueAMD64_OpAMD64MOVLQSXload(v, config)
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case OpAMD64MOVLQZX:
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return rewriteValueAMD64_OpAMD64MOVLQZX(v, config)
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case OpAMD64MOVLQZXload:
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return rewriteValueAMD64_OpAMD64MOVLQZXload(v, config)
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case OpAMD64MOVLload:
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return rewriteValueAMD64_OpAMD64MOVLload(v, config)
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case OpAMD64MOVLloadidx4:
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@ -408,8 +404,6 @@ func rewriteValueAMD64(v *Value, config *Config) bool {
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return rewriteValueAMD64_OpAMD64MOVWQSXload(v, config)
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case OpAMD64MOVWQZX:
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return rewriteValueAMD64_OpAMD64MOVWQZX(v, config)
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case OpAMD64MOVWQZXload:
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return rewriteValueAMD64_OpAMD64MOVWQZXload(v, config)
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case OpAMD64MOVWload:
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return rewriteValueAMD64_OpAMD64MOVWload(v, config)
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case OpAMD64MOVWloadidx2:
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@ -5800,7 +5794,7 @@ func rewriteValueAMD64_OpAMD64MOVBQZX(v *Value, config *Config) bool {
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_ = b
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// match: (MOVBQZX x:(MOVBload [off] {sym} ptr mem))
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// cond: x.Uses == 1
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// result: @x.Block (MOVBQZXload <v.Type> [off] {sym} ptr mem)
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// result: @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
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for {
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x := v.Args[0]
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if x.Op != OpAMD64MOVBload {
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@ -5814,7 +5808,7 @@ func rewriteValueAMD64_OpAMD64MOVBQZX(v *Value, config *Config) bool {
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break
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}
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b = x.Block
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v0 := b.NewValue0(v.Line, OpAMD64MOVBQZXload, v.Type)
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v0 := b.NewValue0(v.Line, OpAMD64MOVBload, v.Type)
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v.reset(OpCopy)
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v.AddArg(v0)
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v0.AuxInt = off
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@ -5823,6 +5817,33 @@ func rewriteValueAMD64_OpAMD64MOVBQZX(v *Value, config *Config) bool {
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v0.AddArg(mem)
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return true
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}
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// match: (MOVBQZX x:(MOVBloadidx1 [off] {sym} ptr idx mem))
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// cond: x.Uses == 1
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// result: @x.Block (MOVBloadidx1 <v.Type> [off] {sym} ptr idx mem)
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for {
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x := v.Args[0]
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if x.Op != OpAMD64MOVBloadidx1 {
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break
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}
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off := x.AuxInt
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sym := x.Aux
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ptr := x.Args[0]
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idx := x.Args[1]
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mem := x.Args[2]
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if !(x.Uses == 1) {
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break
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}
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b = x.Block
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v0 := b.NewValue0(v.Line, OpAMD64MOVBloadidx1, v.Type)
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v.reset(OpCopy)
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v.AddArg(v0)
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v0.AuxInt = off
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v0.Aux = sym
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v0.AddArg(ptr)
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v0.AddArg(idx)
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v0.AddArg(mem)
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return true
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}
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// match: (MOVBQZX (ANDBconst [c] x))
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// cond:
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// result: (ANDQconst [c & 0xff] x)
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@ -5840,35 +5861,6 @@ func rewriteValueAMD64_OpAMD64MOVBQZX(v *Value, config *Config) bool {
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}
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return false
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}
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func rewriteValueAMD64_OpAMD64MOVBQZXload(v *Value, config *Config) bool {
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b := v.Block
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_ = b
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// match: (MOVBQZXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
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// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
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// result: (MOVBQZXload [off1+off2] {mergeSym(sym1,sym2)} base mem)
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for {
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off1 := v.AuxInt
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sym1 := v.Aux
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v_0 := v.Args[0]
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if v_0.Op != OpAMD64LEAQ {
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break
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}
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off2 := v_0.AuxInt
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sym2 := v_0.Aux
|
||||
base := v_0.Args[0]
|
||||
mem := v.Args[1]
|
||||
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpAMD64MOVBQZXload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = mergeSym(sym1, sym2)
|
||||
v.AddArg(base)
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValueAMD64_OpAMD64MOVBload(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
@ -6501,7 +6493,7 @@ func rewriteValueAMD64_OpAMD64MOVLQZX(v *Value, config *Config) bool {
|
||||
_ = b
|
||||
// match: (MOVLQZX x:(MOVLload [off] {sym} ptr mem))
|
||||
// cond: x.Uses == 1
|
||||
// result: @x.Block (MOVLQZXload <v.Type> [off] {sym} ptr mem)
|
||||
// result: @x.Block (MOVLload <v.Type> [off] {sym} ptr mem)
|
||||
for {
|
||||
x := v.Args[0]
|
||||
if x.Op != OpAMD64MOVLload {
|
||||
@ -6515,7 +6507,7 @@ func rewriteValueAMD64_OpAMD64MOVLQZX(v *Value, config *Config) bool {
|
||||
break
|
||||
}
|
||||
b = x.Block
|
||||
v0 := b.NewValue0(v.Line, OpAMD64MOVLQZXload, v.Type)
|
||||
v0 := b.NewValue0(v.Line, OpAMD64MOVLload, v.Type)
|
||||
v.reset(OpCopy)
|
||||
v.AddArg(v0)
|
||||
v0.AuxInt = off
|
||||
@ -6524,6 +6516,33 @@ func rewriteValueAMD64_OpAMD64MOVLQZX(v *Value, config *Config) bool {
|
||||
v0.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
// match: (MOVLQZX x:(MOVLloadidx4 [off] {sym} ptr idx mem))
|
||||
// cond: x.Uses == 1
|
||||
// result: @x.Block (MOVLloadidx4 <v.Type> [off] {sym} ptr idx mem)
|
||||
for {
|
||||
x := v.Args[0]
|
||||
if x.Op != OpAMD64MOVLloadidx4 {
|
||||
break
|
||||
}
|
||||
off := x.AuxInt
|
||||
sym := x.Aux
|
||||
ptr := x.Args[0]
|
||||
idx := x.Args[1]
|
||||
mem := x.Args[2]
|
||||
if !(x.Uses == 1) {
|
||||
break
|
||||
}
|
||||
b = x.Block
|
||||
v0 := b.NewValue0(v.Line, OpAMD64MOVLloadidx4, v.Type)
|
||||
v.reset(OpCopy)
|
||||
v.AddArg(v0)
|
||||
v0.AuxInt = off
|
||||
v0.Aux = sym
|
||||
v0.AddArg(ptr)
|
||||
v0.AddArg(idx)
|
||||
v0.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
// match: (MOVLQZX (ANDLconst [c] x))
|
||||
// cond: c & 0x80000000 == 0
|
||||
// result: (ANDQconst [c & 0x7fffffff] x)
|
||||
@ -6544,35 +6563,6 @@ func rewriteValueAMD64_OpAMD64MOVLQZX(v *Value, config *Config) bool {
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValueAMD64_OpAMD64MOVLQZXload(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (MOVLQZXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
|
||||
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
|
||||
// result: (MOVLQZXload [off1+off2] {mergeSym(sym1,sym2)} base mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym1 := v.Aux
|
||||
v_0 := v.Args[0]
|
||||
if v_0.Op != OpAMD64LEAQ {
|
||||
break
|
||||
}
|
||||
off2 := v_0.AuxInt
|
||||
sym2 := v_0.Aux
|
||||
base := v_0.Args[0]
|
||||
mem := v.Args[1]
|
||||
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpAMD64MOVLQZXload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = mergeSym(sym1, sym2)
|
||||
v.AddArg(base)
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValueAMD64_OpAMD64MOVLload(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
@ -8207,7 +8197,7 @@ func rewriteValueAMD64_OpAMD64MOVWQZX(v *Value, config *Config) bool {
|
||||
_ = b
|
||||
// match: (MOVWQZX x:(MOVWload [off] {sym} ptr mem))
|
||||
// cond: x.Uses == 1
|
||||
// result: @x.Block (MOVWQZXload <v.Type> [off] {sym} ptr mem)
|
||||
// result: @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
|
||||
for {
|
||||
x := v.Args[0]
|
||||
if x.Op != OpAMD64MOVWload {
|
||||
@ -8221,7 +8211,7 @@ func rewriteValueAMD64_OpAMD64MOVWQZX(v *Value, config *Config) bool {
|
||||
break
|
||||
}
|
||||
b = x.Block
|
||||
v0 := b.NewValue0(v.Line, OpAMD64MOVWQZXload, v.Type)
|
||||
v0 := b.NewValue0(v.Line, OpAMD64MOVWload, v.Type)
|
||||
v.reset(OpCopy)
|
||||
v.AddArg(v0)
|
||||
v0.AuxInt = off
|
||||
@ -8230,6 +8220,33 @@ func rewriteValueAMD64_OpAMD64MOVWQZX(v *Value, config *Config) bool {
|
||||
v0.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
// match: (MOVWQZX x:(MOVWloadidx2 [off] {sym} ptr idx mem))
|
||||
// cond: x.Uses == 1
|
||||
// result: @x.Block (MOVWloadidx2 <v.Type> [off] {sym} ptr idx mem)
|
||||
for {
|
||||
x := v.Args[0]
|
||||
if x.Op != OpAMD64MOVWloadidx2 {
|
||||
break
|
||||
}
|
||||
off := x.AuxInt
|
||||
sym := x.Aux
|
||||
ptr := x.Args[0]
|
||||
idx := x.Args[1]
|
||||
mem := x.Args[2]
|
||||
if !(x.Uses == 1) {
|
||||
break
|
||||
}
|
||||
b = x.Block
|
||||
v0 := b.NewValue0(v.Line, OpAMD64MOVWloadidx2, v.Type)
|
||||
v.reset(OpCopy)
|
||||
v.AddArg(v0)
|
||||
v0.AuxInt = off
|
||||
v0.Aux = sym
|
||||
v0.AddArg(ptr)
|
||||
v0.AddArg(idx)
|
||||
v0.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
// match: (MOVWQZX (ANDWconst [c] x))
|
||||
// cond:
|
||||
// result: (ANDQconst [c & 0xffff] x)
|
||||
@ -8247,35 +8264,6 @@ func rewriteValueAMD64_OpAMD64MOVWQZX(v *Value, config *Config) bool {
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValueAMD64_OpAMD64MOVWQZXload(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
// match: (MOVWQZXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
|
||||
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
|
||||
// result: (MOVWQZXload [off1+off2] {mergeSym(sym1,sym2)} base mem)
|
||||
for {
|
||||
off1 := v.AuxInt
|
||||
sym1 := v.Aux
|
||||
v_0 := v.Args[0]
|
||||
if v_0.Op != OpAMD64LEAQ {
|
||||
break
|
||||
}
|
||||
off2 := v_0.AuxInt
|
||||
sym2 := v_0.Aux
|
||||
base := v_0.Args[0]
|
||||
mem := v.Args[1]
|
||||
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
|
||||
break
|
||||
}
|
||||
v.reset(OpAMD64MOVWQZXload)
|
||||
v.AuxInt = off1 + off2
|
||||
v.Aux = mergeSym(sym1, sym2)
|
||||
v.AddArg(base)
|
||||
v.AddArg(mem)
|
||||
return true
|
||||
}
|
||||
return false
|
||||
}
|
||||
func rewriteValueAMD64_OpAMD64MOVWload(v *Value, config *Config) bool {
|
||||
b := v.Block
|
||||
_ = b
|
||||
@ -10198,7 +10186,7 @@ func rewriteValueAMD64_OpAMD64ORL(v *Value, config *Config) bool {
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
// match: (ORL (ORL (ORL x:(MOVBQZXload [i] {s} p mem) (SHLLconst [8] (MOVBQZXload [i+1] {s} p mem))) (SHLLconst [16] (MOVBQZXload [i+2] {s} p mem))) (SHLLconst [24] (MOVBQZXload [i+3] {s} p mem)))
|
||||
// match: (ORL (ORL (ORL x:(MOVBload [i] {s} p mem) (SHLLconst [8] (MOVBload [i+1] {s} p mem))) (SHLLconst [16] (MOVBload [i+2] {s} p mem))) (SHLLconst [24] (MOVBload [i+3] {s} p mem)))
|
||||
// cond:
|
||||
// result: @x.Block (MOVLload [i] {s} p mem)
|
||||
for {
|
||||
@ -10211,7 +10199,7 @@ func rewriteValueAMD64_OpAMD64ORL(v *Value, config *Config) bool {
|
||||
break
|
||||
}
|
||||
x := v_0_0.Args[0]
|
||||
if x.Op != OpAMD64MOVBQZXload {
|
||||
if x.Op != OpAMD64MOVBload {
|
||||
break
|
||||
}
|
||||
i := x.AuxInt
|
||||
@ -10226,7 +10214,7 @@ func rewriteValueAMD64_OpAMD64ORL(v *Value, config *Config) bool {
|
||||
break
|
||||
}
|
||||
v_0_0_1_0 := v_0_0_1.Args[0]
|
||||
if v_0_0_1_0.Op != OpAMD64MOVBQZXload {
|
||||
if v_0_0_1_0.Op != OpAMD64MOVBload {
|
||||
break
|
||||
}
|
||||
if v_0_0_1_0.AuxInt != i+1 {
|
||||
@ -10249,7 +10237,7 @@ func rewriteValueAMD64_OpAMD64ORL(v *Value, config *Config) bool {
|
||||
break
|
||||
}
|
||||
v_0_1_0 := v_0_1.Args[0]
|
||||
if v_0_1_0.Op != OpAMD64MOVBQZXload {
|
||||
if v_0_1_0.Op != OpAMD64MOVBload {
|
||||
break
|
||||
}
|
||||
if v_0_1_0.AuxInt != i+2 {
|
||||
@ -10272,7 +10260,7 @@ func rewriteValueAMD64_OpAMD64ORL(v *Value, config *Config) bool {
|
||||
break
|
||||
}
|
||||
v_1_0 := v_1.Args[0]
|
||||
if v_1_0.Op != OpAMD64MOVBQZXload {
|
||||
if v_1_0.Op != OpAMD64MOVBload {
|
||||
break
|
||||
}
|
||||
if v_1_0.AuxInt != i+3 {
|
||||
@ -10396,7 +10384,7 @@ func rewriteValueAMD64_OpAMD64ORQ(v *Value, config *Config) bool {
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
// match: (ORQ (ORQ (ORQ (ORQ (ORQ (ORQ (ORQ x:(MOVBQZXload [i] {s} p mem) (SHLQconst [8] (MOVBQZXload [i+1] {s} p mem))) (SHLQconst [16] (MOVBQZXload [i+2] {s} p mem))) (SHLQconst [24] (MOVBQZXload [i+3] {s} p mem))) (SHLQconst [32] (MOVBQZXload [i+4] {s} p mem))) (SHLQconst [40] (MOVBQZXload [i+5] {s} p mem))) (SHLQconst [48] (MOVBQZXload [i+6] {s} p mem))) (SHLQconst [56] (MOVBQZXload [i+7] {s} p mem)))
|
||||
// match: (ORQ (ORQ (ORQ (ORQ (ORQ (ORQ (ORQ x:(MOVBload [i] {s} p mem) (SHLQconst [8] (MOVBload [i+1] {s} p mem))) (SHLQconst [16] (MOVBload [i+2] {s} p mem))) (SHLQconst [24] (MOVBload [i+3] {s} p mem))) (SHLQconst [32] (MOVBload [i+4] {s} p mem))) (SHLQconst [40] (MOVBload [i+5] {s} p mem))) (SHLQconst [48] (MOVBload [i+6] {s} p mem))) (SHLQconst [56] (MOVBload [i+7] {s} p mem)))
|
||||
// cond:
|
||||
// result: @x.Block (MOVQload [i] {s} p mem)
|
||||
for {
|
||||
@ -10425,7 +10413,7 @@ func rewriteValueAMD64_OpAMD64ORQ(v *Value, config *Config) bool {
|
||||
break
|
||||
}
|
||||
x := v_0_0_0_0_0_0.Args[0]
|
||||
if x.Op != OpAMD64MOVBQZXload {
|
||||
if x.Op != OpAMD64MOVBload {
|
||||
break
|
||||
}
|
||||
i := x.AuxInt
|
||||
@ -10440,7 +10428,7 @@ func rewriteValueAMD64_OpAMD64ORQ(v *Value, config *Config) bool {
|
||||
break
|
||||
}
|
||||
v_0_0_0_0_0_0_1_0 := v_0_0_0_0_0_0_1.Args[0]
|
||||
if v_0_0_0_0_0_0_1_0.Op != OpAMD64MOVBQZXload {
|
||||
if v_0_0_0_0_0_0_1_0.Op != OpAMD64MOVBload {
|
||||
break
|
||||
}
|
||||
if v_0_0_0_0_0_0_1_0.AuxInt != i+1 {
|
||||
@ -10463,7 +10451,7 @@ func rewriteValueAMD64_OpAMD64ORQ(v *Value, config *Config) bool {
|
||||
break
|
||||
}
|
||||
v_0_0_0_0_0_1_0 := v_0_0_0_0_0_1.Args[0]
|
||||
if v_0_0_0_0_0_1_0.Op != OpAMD64MOVBQZXload {
|
||||
if v_0_0_0_0_0_1_0.Op != OpAMD64MOVBload {
|
||||
break
|
||||
}
|
||||
if v_0_0_0_0_0_1_0.AuxInt != i+2 {
|
||||
@ -10486,7 +10474,7 @@ func rewriteValueAMD64_OpAMD64ORQ(v *Value, config *Config) bool {
|
||||
break
|
||||
}
|
||||
v_0_0_0_0_1_0 := v_0_0_0_0_1.Args[0]
|
||||
if v_0_0_0_0_1_0.Op != OpAMD64MOVBQZXload {
|
||||
if v_0_0_0_0_1_0.Op != OpAMD64MOVBload {
|
||||
break
|
||||
}
|
||||
if v_0_0_0_0_1_0.AuxInt != i+3 {
|
||||
@ -10509,7 +10497,7 @@ func rewriteValueAMD64_OpAMD64ORQ(v *Value, config *Config) bool {
|
||||
break
|
||||
}
|
||||
v_0_0_0_1_0 := v_0_0_0_1.Args[0]
|
||||
if v_0_0_0_1_0.Op != OpAMD64MOVBQZXload {
|
||||
if v_0_0_0_1_0.Op != OpAMD64MOVBload {
|
||||
break
|
||||
}
|
||||
if v_0_0_0_1_0.AuxInt != i+4 {
|
||||
@ -10532,7 +10520,7 @@ func rewriteValueAMD64_OpAMD64ORQ(v *Value, config *Config) bool {
|
||||
break
|
||||
}
|
||||
v_0_0_1_0 := v_0_0_1.Args[0]
|
||||
if v_0_0_1_0.Op != OpAMD64MOVBQZXload {
|
||||
if v_0_0_1_0.Op != OpAMD64MOVBload {
|
||||
break
|
||||
}
|
||||
if v_0_0_1_0.AuxInt != i+5 {
|
||||
@ -10555,7 +10543,7 @@ func rewriteValueAMD64_OpAMD64ORQ(v *Value, config *Config) bool {
|
||||
break
|
||||
}
|
||||
v_0_1_0 := v_0_1.Args[0]
|
||||
if v_0_1_0.Op != OpAMD64MOVBQZXload {
|
||||
if v_0_1_0.Op != OpAMD64MOVBload {
|
||||
break
|
||||
}
|
||||
if v_0_1_0.AuxInt != i+6 {
|
||||
@ -10578,7 +10566,7 @@ func rewriteValueAMD64_OpAMD64ORQ(v *Value, config *Config) bool {
|
||||
break
|
||||
}
|
||||
v_1_0 := v_1.Args[0]
|
||||
if v_1_0.Op != OpAMD64MOVBQZXload {
|
||||
if v_1_0.Op != OpAMD64MOVBload {
|
||||
break
|
||||
}
|
||||
if v_1_0.AuxInt != i+7 {
|
||||
@ -10694,12 +10682,12 @@ func rewriteValueAMD64_OpAMD64ORW(v *Value, config *Config) bool {
|
||||
v.AddArg(x)
|
||||
return true
|
||||
}
|
||||
// match: (ORW x:(MOVBQZXload [i] {s} p mem) (SHLWconst [8] (MOVBQZXload [i+1] {s} p mem)))
|
||||
// match: (ORW x:(MOVBload [i] {s} p mem) (SHLWconst [8] (MOVBload [i+1] {s} p mem)))
|
||||
// cond:
|
||||
// result: @x.Block (MOVWload [i] {s} p mem)
|
||||
for {
|
||||
x := v.Args[0]
|
||||
if x.Op != OpAMD64MOVBQZXload {
|
||||
if x.Op != OpAMD64MOVBload {
|
||||
break
|
||||
}
|
||||
i := x.AuxInt
|
||||
@ -10714,7 +10702,7 @@ func rewriteValueAMD64_OpAMD64ORW(v *Value, config *Config) bool {
|
||||
break
|
||||
}
|
||||
v_1_0 := v_1.Args[0]
|
||||
if v_1_0.Op != OpAMD64MOVBQZXload {
|
||||
if v_1_0.Op != OpAMD64MOVBload {
|
||||
break
|
||||
}
|
||||
if v_1_0.AuxInt != i+1 {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user