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cmd/5g: fix regopt bug in copyprop

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copyau1 was assuming that it could deduce the type of the
middle register p->reg from the type of the left or right
argument: in CMPF F1, F2, the p->reg==2 must be a D_FREG
because p->from is F1, and in CMP R1, R2, the p->reg==2 must
be a D_REG because p->from is R1.

This heuristic fails for CMP $0, R2, which was causing copyau1
not to recognize p->reg==2 as a reference to R2, which was
keeping it from properly renaming the register use when
substituting registers.

cmd/5c has the right approach: look at the opcode p->as to
decide the kind of register. It is unclear where 5g's copyau1
came from; perhaps it was an attempt to avoid expanding 5c's
a2type to include new instructions used only by 5g.

Copy a2type from cmd/5c, expand to include additional instructions,
and make it crash the compiler if asked about an instruction
it does not understand (avoid silent bugs in the future if new
instructions are added).

Should fix current arm build breakage.

While we're here, fix the print statements dumping the pred and
succ info in the asm listing to pass an int arg to %.4ud
(Prog.pc is a vlong now, due to the liblink merge).

TBR=ken2
CC=golang-codereviews
https://golang.org/cl/62730043
This commit is contained in:
Russ Cox 2014-02-13 03:54:55 +00:00
parent 27cb59fdad
commit 684332f47c
4 changed files with 73 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

88
src/cmd/5g/peep.c
View File

@ -1242,35 +1242,79 @@ copyau(Adr *a, Adr *v)
return 0;
}
static int
a2type(Prog *p)
{
if(p->reg == NREG)
return D_NONE;
switch(p->as) {
default:
fatal("a2type: unhandled %P", p);
case AAND:
case AEOR:
case ASUB:
case ARSB:
case AADD:
case AADC:
case ASBC:
case ARSC:
case ATST:
case ATEQ:
case ACMP:
case ACMN:
case AORR:
case ABIC:
case AMVN:
case ASRL:
case ASRA:
case ASLL:
case AMULU:
case ADIVU:
case AMUL:
case ADIV:
case AMOD:
case AMODU:
case AMULA:
case AMULL:
case AMULAL:
case AMULLU:
case AMULALU:
case AMULWT:
case AMULWB:
case AMULAWT:
case AMULAWB:
return D_REG;
case ACMPF:
case ACMPD:
case AADDF:
case AADDD:
case ASUBF:
case ASUBD:
case AMULF:
case AMULD:
case ADIVF:
case ADIVD:
case ASQRTF:
case ASQRTD:
case AABSF:
case AABSD:
return D_FREG;
}
}
/*
* compare v to the center
* register in p (p->reg)
* the trick is that this
* register might be D_REG
* D_FREG. there are basically
* two cases,
* ADD r,r,r
* CMP r,r,
*/
static int
copyau1(Prog *p, Adr *v)
{
if(regtyp(v))
if(p->reg == v->reg) {
if(p->to.type != D_NONE) {
if(v->type == p->to.type)
return 1;
return 0;
}
if(p->from.type != D_NONE) {
if(v->type == p->from.type)
return 1;
return 0;
}
print("copyau1: can't tell %P\n", p);
}
return 0;
if(v->type == D_REG && v->reg == NREG)
return 0;
return p->reg == v->reg && a2type(p) == v->type;
}
/*

6
src/cmd/5g/reg.c
View File

@ -1291,9 +1291,9 @@ dumpit(char *str, Flow *r0, int isreg)
if(r1 != nil) {
print(" pred:");
for(; r1 != nil; r1 = r1->p2link)
print(" %.4ud", r1->prog->pc);
print(" %.4ud", (int)r1->prog->pc);
if(r->p1 != nil)
print(" (and %.4ud)", r->p1->prog->pc);
print(" (and %.4ud)", (int)r->p1->prog->pc);
else
print(" (only)");
print("\n");
@ -1302,7 +1302,7 @@ dumpit(char *str, Flow *r0, int isreg)
// if(r1 != nil) {
// print(" succ:");
// for(; r1 != R; r1 = r1->s1)
// print(" %.4ud", r1->prog->pc);
// print(" %.4ud", (int)r1->prog->pc);
// print("\n");
// }
}

4
src/cmd/6g/reg.c
View File

@ -1174,14 +1174,14 @@ dumpit(char *str, Flow *r0, int isreg)
if(r1 != nil) {
print(" pred:");
for(; r1 != nil; r1 = r1->p2link)
print(" %.4ud", r1->prog->pc);
print(" %.4ud", (int)r1->prog->pc);
print("\n");
}
// r1 = r->s1;
// if(r1 != R) {
// print(" succ:");
// for(; r1 != R; r1 = r1->s1)
// print(" %.4ud", r1->prog->pc);
// print(" %.4ud", (int)r1->prog->pc);
// print("\n");
// }
}

4
src/cmd/8g/reg.c
View File

@ -1139,14 +1139,14 @@ dumpit(char *str, Flow *r0, int isreg)
if(r1 != nil) {
print(" pred:");
for(; r1 != nil; r1 = r->p2link)
print(" %.4ud", r1->prog->pc);
print(" %.4ud", (int)r1->prog->pc);
print("\n");
}
// r1 = r->s1;
// if(r1 != nil) {
// print(" succ:");
// for(; r1 != R; r1 = r1->s1)
// print(" %.4ud", r1->prog->pc);
// print(" %.4ud", (int)r1->prog->pc);
// print("\n");
// }
}